EVAL-AD1837AEB [ADI]
2 ADC, 8 DAC, 96 kHz, 24-Bit Codec; 2 ADC ， DAC， 8 ， 96千赫， 24位编解码器
| 型号： | EVAL-AD1837AEB |
| 厂家： | 
ADI |
| 描述： | 2 ADC, 8 DAC, 96 kHz, 24-Bit Codec |
| 文件： | 总24页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 ADC, 8 DAC,
96 kHz, 24-Bit ꢀ-ꢁ Codec
a
AD1837A
FEATURES
APPLICATIONS
5 V Stereo Audio System with 3.3 V Tolerant
Digital Interface
DVD Video and Audio Players
Home Theater Systems
Supports up to 96 kHz Sample Rates
192 kHz Sample Rate Available on 1 DAC
Supports 16-, 20-, 24-Bit Word Lengths
Multibit ꢀ-ꢁ Modulators with
Perfect Differential Linearity Restoration for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least
Sensitive to Jitter
Single-Ended Outputs
ADCs: –95 dB THD + N, 105 dB SNR and
Dynamic Range
DACs: –92 dB THD + N, 108 dB SNR and
Dynamic Range
On-Chip Volume Controls per Channel with
1024-Step Linear Scale
Automotive Audio Systems
Audio/Visual Receivers
Digital Audio Effects Processors
GENERAL DESCRIPTION
The AD1837A is a high performance single-chip codec featuring
four stereo DACs and one stereo ADC. Each DAC comprises a
high performance digital interpolation filter, a multibit ꢀ-ꢁ
modulator featuring Analog Devices’ patented technology, and a
continuous-time voltage out analog section. Each DAC has inde-
pendent volume control and clickless mute functions. The ADC
comprises two 24-bit conversion channels with multibit S-D
modulators and decimation filters.
The AD1837A also contains an on-chip reference with a nominal
value of 2.25 V.
The AD1837A contains a flexible serial interface that allows for
glueless connection to a variety of DSP chips, AES/EBU receivers,
and sample rate converters. The AD1837A can be configured in
left-justified, right-justified, I2S, or DSP compatible serial modes.
Control of the AD1837A is achieved by means of an SPI compat-
ible serial port. While the AD1837A can be operated from a single
5 V supply, it also features a separate supply pin for its digital inter-
face, which allows the device to be interfaced to other devices using
3.3 V power supplies.
DAC and ADC Software Controllable Clickless Mutes
Digital De-emphasis Processing
Supports 256 ꢂ fS, 512 ꢂ fS, and 768 ꢂ fS Master
Mode Clocks
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S Compatible, and DSP Serial Port
Modes
TDM Interface Mode Supports 8 In/8 Out Using a
Single SHARC® SPORT
The AD1837A is available in a 52-lead MQFP package and is speci-
fied for the industrial temperature range of –40ºC to +85ºC.
52-Lead MQFP Plastic Package
FUNCTIONAL BLOCK DIAGRAM
DVDD DVDD ODVDD ALRCLK ABCLK ASDATA CCLK CLATCH CIN COUT
MCLK
AVDD
PD/RST M/S
AVDD
DLRCLK
DBCLK
CLOCK
CONTROL PORT
OUTL1
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
VOLUME
SERIAL DATA
I/O PORT
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ꢀ-ꢁ
DAC
DIGITAL
FILTER
OUTR1
OUTL2
ꢀ-ꢁ
DAC
DIGITAL
FILTER
OUTR2
OUTL3
ADCLP
ADCLN
ꢀ-ꢁ
DAC
DIGITAL
FILTER
ꢀ-ꢁ
ADC
DIGITAL
FILTER
OUTR3
OUTL4
ꢀ-ꢁ
DAC
DIGITAL
FILTER
ADCRP
ADCRN
ꢀ-ꢁ
ADC
DIGITAL
FILTER
OUTR4
FILTD
FILTR
V
REF
AD1837A
DGND DGND AGND AGND AGND AGND
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
AD1837A–SPECIFICATIONS
TEST CONDITIONS
Supply Voltages (AVDD, DVDD) 5.0 V
Ambient Temperature
Input Clock
ADC Input Signal
DAC Input Signal
Input Sample Rate (fS)
Measurement Bandwidth
Word Width
25∞C
12.288 MHz, (256 ꢂ fS Mode)
1.0078125 kHz, –1 dBFS (Full Scale)
1.0078125 kHz, 0 dBFS (Full Scale)
48 kHz
20 Hz to 20 kHz
24 Bits
Load Capacitance
Load Impedance
100 pF
47 kW
Performance of all channels is identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation
specifications).
Parameter
Min
Typ
Max
Unit
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
24
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)
No Filter
With A-Weighted (48 kHz and 96 kHz)
Total Harmonic Distortion + Noise (THD + N)
fS = 48 kHz
103
105
dB
dB
100
–95
–95
100
0.025
–88.5
–87.5
dB
dB
dB
dB
fS = 96 kHz
Interchannel Isolation
Interchannel Gain Mismatch
Analog Inputs
Differential Input Range (± Full Scale)
Common-Mode Input Voltage
Input Impedance
–2.828
+2.828
V
V
kW
pF
V
2.25
4
15
Input Capacitance
VREF
2.25
DC Accuracy
Gain Error
Gain Drift
±5
35
%
ppm/ºC
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
24
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input)
No Filter
With A-Weighted Filter (48 kHz and 96 kHz)
Total Harmonic Distortion + Noise (48 kHz and 96 kHz)
Interchannel Isolation
103
105
105
108
–92
100
dB
dB
dB
dB
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
±4
0.025
200
%
dB
ppm/∞C
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Maximum Attenuation)
Mute Attenuation
±0.1
0.098
60
–100
±0.1
1.0 (2.8)
180
Degrees
%
dB
dB
De-emphasis Gain Error
dB
Full-Scale Output Voltage at Each Pin (Single-Ended)
Output Resistance at Each Pin
Common-Mode Output Voltage
V rms (V p-p)
W
V
2.25
ADC DECIMATION FILTER, 48 kHz*
Pass Band
21.77
±0.01
26.23
120
kHz
dB
kHz
dB
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
910
ms
–2–
REV. A
AD1837A
Parameter
Min
Typ
Max
Unit
ADC DECIMATION FILTER, 96 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
43.54
±0.01
52.46
120
kHz
dB
kHz
dB
460
ms
DAC INTERPOLATION FILTER, 48 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
21.77
43.54
81.2
kHz
dB
kHz
dB
±0.06
28
55
340
ms
DAC INTERPOLATION FILTER, 96 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
kHz
dB
kHz
dB
±0.06
52
55
160
ms
DAC INTERPOLATION FILTER, 192 kHz*
Pass Band
Pass-Band Ripple
Stop Band
Stop-Band Attenuation
Group Delay
kHz
dB
kHz
dB
±0.06
97
80
110
ms
DIGITAL I/O
Input Voltage High
Input Voltage Low
Output Voltage High
Output Voltage Low
Leakage Current
2.4
V
V
V
V
0.8
ODVDD – 0.4
0.4
±10
mA
POWER SUPPLIES
Supply Voltage (AVDD and DVDD)
Supply Voltage (ODVDD)
Supply Current IANALOG
Supply Current IANALOG, Power-Down
Supply Current IDIGITAL
4.5
3.0
5.0
5.5
DVDD
95
67
74
V
V
mA
mA
mA
mA
84
55
64
1
Supply Current IDIGITAL, Power-Down
Dissipation
4.5
Operation, Both Supplies
Operation, Analog Supply
Operation, Digital Supply
Power-Down, Both Supplies
Power Supply Rejection Ratio
1 kHz, 300 mV p-p Signal at Analog Supply Pins
20 kHz, 300 mV p-p Signal at Analog Supply Pins
740
420
320
280
mW
mW
mW
mW
–70
–75
dB
dB
*Guaranteed by design.
Specifications subject to change without notice.
REV. A
–3–
AD1837A
TIMING SPECIFICATIONS
Parameter
Min
Max
Unit
Comments
MASTER CLOCK AND RESET
tMH
tML
MCLK High
MCLK Low
PD/RST Low
15
15
20
ns
ns
ns
tPDR
SPI® PORT
tCCH
tCCL
tCCP
tCDS
tCDH
tCLS
tCLH
tCOE
CCLK High
CCLK Low
40
40
80
10
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Period
CDATA Setup
CDATA Hold
CLATCH Setup
CLATCH Hold
COUT Enable
COUT Delay
COUT Three-State
To CCLK Rising Edge
From CCLK Rising Edge
To CCLK Rising Edge
From CCLK Rising Edge
From CLATCH Falling Edge
From CCLK Falling Edge
From CLATCH Rising Edge
15
20
25
tCOD
tCOTS
DAC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Slave)
tDBH
tDBL
fDB
DBCLK High
DBCLK Low
60
60
64 ꢂ fS
10
10
ns
ns
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
tDLS
tDLH
tDDS
tDDH
ns
ns
ns
ns
To DBCLK Rising Edge
From DBCLK Rising Edge
To DBCLK Rising Edge
From DBCLK Rising Edge
10
10
Packed 128/256 Modes (Slave)
tDBH
tDBL
fDB
tDLS
tDLH
tDDS
tDDH
DBCLK High
DBCLK Low
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
15
15
256 ꢂ fS
10
10
ns
ns
ns
ns
ns
ns
To DBCLK Rising Edge
From DBCLK Rising Edge
To DBCLK Rising Edge
From DBCLK Rising Edge
10
10
ADC SERIAL PORT (48 kHz and 96 kHz)
Normal Mode (Master)
tABD
tALD
tABDD
ABCLK Delay
ALRCLK Delay
ASDATA Delay
25
5
10
ns
ns
ns
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
Normal Mode (Slave)
tABH
tABL
fAB
ABCLK High
ABCLK Low
ABCLK Frequency
ALRCLK Setup
ALRCLK Hold
ASDATA Delay
60
60
64 ꢂ fS
5
ns
ns
tALS
tALH
tABDD
ns
ns
ns
To ABCLK Rising Edge
From ABCLK Rising Edge
From ABCLK Falling Edge
15
15
Packed 128/256 Mode (Master)
tPABD
tPALD
tPABDD
ABCLK Delay
LRCLK Delay
ASDATA Delay
40
5
10
ns
ns
ns
From MCLK Rising Edge
From ABCLK Falling Edge
From ABCLK Falling Edge
–4–
REV. A
AD1837A
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master, 48 kHz and 96 kHz)
tTBD
BCLK Delay
40
5
10
ns
ns
ns
ns
ns
From MCLK Rising Edge
From BCLK Rising Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
tFSD
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
tTABDD
tTDDS
tTDDH
15
15
TDM256 MODE (Slave, 48 kHz and 96 kHz)
fAB
BCLK Frequency
BCLK High
BCLK Low
FSTDM Setup
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
256 ꢂ fS
17
17
10
10
tTBCH
tTBCL
tTFS
ns
ns
ns
ns
ns
ns
ns
To BCLK Falling Edge
From BCLK Falling Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
tTFH
tTBDD
tTDDS
tTDDH
15
15
15
TDM512 MODE (Master, 48 kHz)
tTBD
tFSD
tTABDD
tTDDS
tTDDH
BCLK Delay
40
5
10
ns
ns
ns
ns
ns
From MCLK Rising Edge
From BCLK Rising Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
FSTDM Delay
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
15
15
TDM512 MODE (Slave, 48 kHz)
fAB
BCLK Frequency
BCLK High
BCLK Low
FSTDM Setup
FSTDM Hold
ASDATA Delay
DSDATA1 Setup
DSDATA1 Hold
512 ꢂ fS
17
17
10
10
tTBCH
tTBCL
tTFS
ns
ns
ns
ns
ns
ns
ns
To BCLK Falling Edge
From BCLK Falling Edge
From BCLK Rising Edge
To BCLK Falling Edge
From BCLK Falling Edge
tTFH
tTBDD
tTDDS
tTDDH
15
15
15
AUXILIARY INTERFACE (48 kHz and 96 kHz)
tAXDS
tAXDH
fABP
AAUXDATA Setup
AAUXDATA Hold
AUXBCLK Frequency
10
10
64 ꢂ fS
ns
ns
To AUXBCLK Rising Edge
From AUXBCLK Rising Edge
Slave Mode
tAXBH
tAXBL
tAXLS
tAXLH
AUXBCLK High
AUXBCLK Low
AUXLRCLK Setup
AUXLRCLK Hold
15
15
10
10
ns
ns
ns
ns
To AUXBCLK Rising Edge
From AUXBCLK Rising Edge
Master Mode
tAUXLRCLK
tAUXBCLK
AUXLRCLK Delay
AUXBCLK Delay
15
20
ns
ns
From AUXBCLK Falling Edge
From MCLK Rising Edge
Specifications subject to change without notice.
tMCLK
tMH
MCLK
tML
PD/RST
tPDR
Figure 1. MCLK and PD/RST Timing
REV. A
–5–
AD1837A
ABSOLUTE MAXIMUM RATINGS*
(TA = 25∞C, unless otherwise noted.)
TEMPERATURE RANGE
Parameter
Min
Typ
Max
Unit
AVDD, DVDD, ODVDD to AGND, DGND
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . –0.3 V to ODVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Specifications Guaranteed
Functionality Guaranteed
Storage
25
∞C
∞C
∞C
–40
–65
+85
+150
Industrial (A Version) . . . . . . . . . . . . . . . –40∞C to +85∞C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD1837AAS
–40oC to +85oC
–40oC to +85oC
–40oC to +85oC
52-Lead MQFP
52-Lead MQFP
52-Lead MQFP
52-Lead MQFP
Evaluation Board
S-52-1
S-52-1
S-52-1
S-52-1
AD1837AAS-REEL
AD1837AASZ*
AD1837AASZ-REEL* –40oC to +85oC
EVAL-AD1837AEB
*Z = Pb free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1837A features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–6–
REV. A
AD1837A
PIN CONFIGURATION
48
50 49
47 46 45 44 43 42 41 40
51
52
39 DVDD
1
2
DVDD
CLATCH
CIN
38
37
DBCLK
DLRCLK
3
4
36
35
34
M/S
PD/RST
AGND
NC
AGND
OUTR4
NC
5
6
AD1837A
TOP VIEW
33
32
31
OUTL1
NC
7
(Not to Scale)
8
OUTL4
NC
OUTR1
AGND
AVDD
NC
9
10
11
12
13
30 AGND
29 AVDD
28 OUTR3
27 NC
OUTL2
14 15 16 17 18 19 20 21 22 23 24 25 26
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Input/
Output
Pin Number
Mnemonic
Description
1, 39
2
3
4
DVDD
CLATCH
CIN
PD/RST
AGND
NC
Digital Power Supply. Connect to digital 5 V supply.
Latch Input for Control Data.
Serial Control Input.
Power-Down/Reset.
Analog Ground.
I
I
I
5, 10, 16, 24, 30, 35
6, 12, 25, 31
Not Connected.
7, 13, 26, 32
8, 14, 27, 33
9, 15, 28, 34
11, 19, 29
17
18
20
21
22
OUTLx
NC
OUTRx
AVDD
FILTD
FILTR
ADCLN
ADCLP
ADCRN
ADCRP
M/S
O
O
DACx Left Channel Output.
Not Connected.
DACx Right Channel Output.
Analog Power Supply. Connect to analog 5 V supply.
Filter Capacitor Connection. Recommended 10 mF/100 nF.
Reference Filter Capacitor Connection. Recommended 10 mF/100 nF.
ADC Left Channel Negative Input.
ADC Left Channel Positive Input.
ADC Right Channel Negative Input.
ADC Right Channel Positive Input.
ADC Master/Slave Select.
I
I
I
I
23
36
I
37
38
40, 52
41 to 44
45
46
47
48
49
DLRCLK
DBCLK
DGND
DSDATAx
ABCLK
ALRCLK
MCLK
ODVDD
ASDATA
COUT
CCLK
I/O
I/O
DAC LR Clock.
DAC Bit Clock.
Digital Ground.
DACx Input Data (Left and Right Channels).
ADC Bit Clock.
ADC LR Clock.
Master Clock Input.
Digital Output Driver Power Supply.
ADC Serial Data Output.
Output for Control Data.
I
I/O
I/O
I
O
O
I
50
51
Control Clock Input for Control Data.
REV. A
–7–
AD1837A –Typical Performance Characteristics
5
0
0
–5
–50
–10
–15
–20
–25
–30
–100
–150
0
5
10
15
0
5
10
15
20
FREQUENCY – Hz
FREQUENCY – Normalized to fS
TPC 1. ADC Composite Filter Response
TPC 4. ADC High-Pass Filter Response, fS = 96 kHz
0
5
0
–5
–50
–100
–150
–10
–15
–20
–25
–30
0
50
100
150
200
0
5
10
15
20
FREQUENCY – kHz
FREQUENCY – Hz
TPC 5. DAC Composite Filter Response, fS = 48 kHz
TPC 2. ADC High-Pass Filter Response, fS = 48 kHz
0
0
–50
–100
–150
–50
–100
–150
0
50
100
150
200
0
0.5
1.0
1.5
2.0
FREQUENCY – kHz
FREQUENCY – Normalized to fS
TPC 6. DAC Composite Filter Response, fS = 96 kHz
TPC 3. ADC Composite Filter Response
(Pass-Band Section)
–8–
REV. A
AD1837A
0.2
0.1
0
–50
0
–0.1
–0.2
–100
–150
0
50
100
150
200
0
10
20
30
40
50
FREQUENCY – kHz
FREQUENCY – kHz
TPC 7. DAC Composite Filter Response, fS = 192 kHz
TPC 9. DAC Composite Filter Response, fS = 96 kHz
(Pass-Band Section)
0.10
0.05
0
0.10
0.05
0
–0.05
–0.10
–0.05
–0.10
0
5
10
15
20
0
20
40
60
80
100
FREQUENCY – kHz
FREQUENCY – kHz
TPC 8. DAC Composite Filter Response, fS = 48 kHz
(Pass-Band Section)
TPC 10. DAC Composite Filter Response, fS = 192 kHz
(Pass-Band Section)
REV. A
–9–
AD1837A
TERMINOLOGY
Gain Drift
Dynamic Range
Change in response to a near full-scale input with a change in
temperature, expressed as parts-per-million (ppm) per ∞C.
The ratio of a full-scale input signal to the integrated input noise
in the pass band (20 Hz to 20 kHz), expressed in decibels (dB).
Dynamic range is measured with a –60 dB input signal and is
equal to (S/[THD + N]) + 60 dB. Note that spurious harmonics
are below the noise with a –60 dB input, so the noise level
establishes the dynamic range. The dynamic range is specified
with and without an A-weight filter applied.
Crosstalk (EIAJ Method)
Ratio of response on one channel with a grounded input to a
full-scale 1 kHz sine wave input on the other channel, expressed
in decibels.
Power Supply Rejection
With no analog input, signal present at the output when a
300 mV p-p signal is applied to power supply pins, expressed
in decibels of full scale.
Signal-to-(Total Harmonic Distortion + Noise)
[S/(THD+N)]
The ratio of the root-mean-square (rms) value of the funda-
mental input signal to the rms sum of all other spectral compo-
nents in the pass band, expressed in decibels (dB).
Group Delay
Intuitively, the time interval required for an input pulse to
appear at the converter’s output, expressed in microseconds
(ms). More precisely, the derivative of radian phase with
respect to radian frequency at a given frequency.
Pass Band
The region of the frequency spectrum unaffected by the attenu-
ation of the digital decimator’s filter.
Group Delay Variation
Pass-Band Ripple
The difference in group delays at different input frequencies.
Specified as the difference between largest and the smallest
group delays in the pass band, expressed in microseconds (ms).
The peak-to-peak variation in amplitude response from equal-
amplitude input signal frequencies within the pass band, expressed
in decibels.
Stop Band
ACRONYMS
The region of the frequency spectrum attenuated by the
digital decimator’s filter to the degree specified by stop-band
attenuation.
ADC—Analog-to-Digital Converter.
DAC—Digital-to-Analog Converter.
DSP—Digital Signal Processor.
Gain Error
IMCLK—Internal Master Clock Signal used to clock the ADC
and DAC engines.
With a near full-scale input, the ratio of actual output to expected
output, expressed as a percentage.
MCLK—External Master Clock Signal applied to the AD1837A.
Interchannel Gain Mismatch
With identical near full-scale inputs, the ratio of outputs of the
two stereo channels, expressed in decibels.
–10–
REV. A
AD1837A
FUNCTIONAL OVERVIEW
Table I. Coding Scheme
ADCs
Code
Level
There are two ADC channels in the AD1837A, configured as a
stereo pair. Each ADC has fully differential inputs. The ADC
section can operate at a sample rate of up to 96 kHz. The ADCs
include on-board digital decimation filters with 120 dB stop-band
attenuation and linear phase response, operating at an oversam-
pling ratio of 128 (for 48 kHz operation) or 64 (for 96 kHz
operation).
0111 . . . . 11111
0000 . . . . 00000
1000 . . . . 00000
+FS
0 (Ref Level)
–FS
AD1837A CLOCKING SCHEME
By default, the AD1837A requires an MCLK signal that is
256 times the required sample frequency up to a maximum of
12.288 MHz. The AD1837A uses a clock scaler to double the
clock frequency for internal use. The default setting of the clock
scaler is multiply by two. The clock scaler can also be set to
multiply by 1 (bypass) or multiply by 2/3. The internal MCLK
signal, IMCLK, should not exceed 24.576 MHz in order to
ensure correct operation.
ADC peak level information for each ADC may be read from the
ADC Peak 0 and ADC Peak 1 registers. The data is supplied as
a 6-bit word with a maximum range of 0 dB to –63 dB and a
resolution of 1 dB. The registers will hold peak information until
read; after reading, the registers are reset so that new peak
information can be acquired. Refer to the register description
for details on the format. The two ADC channels have a com-
mon serial bit clock and a left-right framing clock. The clock
signals are all synchronous with the sample rate.
The MCLK of the AD1837A should remain constant during
normal operation of the DAC and ADC. If it is required to
change the MCLK rate, the AD1837A should be reset. Addition-
ally, if MCLK scaler needs to be modified so that the IMCLK
does not exceed 24.576 MHz, this should be done during the
internal reset phase of the AD1837A by programming the bits in
the first 3072 MCLK periods following the reset.
The ADC digital pins, ABCLK and ALRCLK, can be set to
operate as inputs or outputs by connecting the M/S pin to
ODVDD or DGND, respectively. When the pins are set as
outputs, the AD1837A will generate the timing signals. When
the pins are set as inputs, the timing must be generated by
the external audio controller.
Selecting DAC Sampling Rate
DACs
The AD1837A DAC engine has a programmable interpolator
that allows the user to select different interpolation rates
based on the required sample rate and MCLK value avail-
able. Table II shows the settings required for sample rates
based on a fixed MCLK of 12.288 MHz.
The AD1837A has eight DAC channels arranged as four inde-
pendent stereo pairs, with eight single-ended analog outputs for
improved noise and distortion performance. Each channel has
its own independently programmable attenuator, adjustable in
1024 linear steps. Digital inputs are supplied through four serial
data input pins (one for each stereo pair) and a common frame
(DLRCLK) and bit (DBLCK) clock. Alternatively, one of the
packed data modes may be used to access all eight channels on a
single TDM data pin. A stereo replicate feature is included where
the DAC data sent to the first DAC pair is also sent to the
other DACs in the part. The AD1837A can accept DAC data at
a sample rate of 192 kHz on DAC 1 only. The stereo repli-
cate feature can then be used to copy the audio data to the
other DACs.
Table II. DAC Sample Rate Settings
Sample Rate Interpolator Rate DAC Control 1 Register
48 kHz
96 kHz
192 kHz
8x
4x
2x
000000xxxxxxxx00
000000xxxxxxxx01
000000xxxxxxxx10
Selecting an ADC Sample Rate
The AD1837A ADC engine has a programmable decimator
that allows the user to select the sample rate based on the
MCLK value. By default, the output sample rate is IMCLK/
512. To achieve a sample rate of IMCLK/256, the sample
rate bit in the ADC Control 1 register should be set as shown
in Table III.
Each of the output pins sits at a dc level of VREF and swings
±1.4 V for a 0 dB digital input signal. A single op amp third-
order external low-pass filter is recommended to remove high
frequency noise present on the output pins. Note that the use of
op amps with low slew rate or low bandwidth may cause high
frequency noise and tones to fold down into the audio band;
care should be exercised in selecting these components.
Table III. ADC Sample Rate Settings
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little affect
on performance.
Sample Rate
ADC Control 1 Register
IMCLK/512
IMCLK/256
1100000xx0xxxxxx (48 kHz)
1100000xx1xxxxxx (96 kHz)
DAC and ADC Coding
The DAC and ADC output data stream is in a twos comple-
ment encoded format. The word width can be selected from
16 bit, 20 bit, or 24 bit. The coding scheme is detailed
in Table I.
To maintain the highest performance possible, it is recommended
that the clock jitter of the master clock signal be limited to less
than 300 ps rms, measured using the edge-to-edge technique.
Even at these levels, extra noise or tones may appear in the
REV. A
–11–
AD1837A
DAC ENGINE
48kHz/96kHz/192kHz
INTERPOLATION
FILTER
S-D
ANALOG
OUTPUT
DAC
DAC INPUT
MODULATOR
CLOCK SCALING
ꢂ 1
ꢂ 2
MCLK
IMCLK = 24.576MHz
12.288MHz
ꢂ 2/3
ADC ENGINE
48kHz/96kHz
ANALOG
INPUT
OPTIONAL
HPF
DECIMATOR/
FILTER
S-D
ADC OUTPUT
MODULATOR
Figure 2. Modulator Clocking Scheme
tCLS
tCLH
tCCH tCCL
tCCP
CLATCH
CCLK
tCOTS
tCDS tCDH
D9
D9
D8
CIN
D15
D14
D0
tCOE
COUT
D8
D0
tCOD
Figure 3. Format of SPI Timing
DAC outputs if the jitter spectrum contains large spectral peaks.
It is highly recommended that the master clock be generated by
an independent crystal oscillator. In addition, it is especially
important that the clock signal not be passed through an FPGA
or other large digital chip before being applied to the AD1837A.
In most cases, this will induce clock jitter due to the fact that
the clock signal is sharing common power and ground connec-
tions with other unrelated digital output signals.
means of two ferrite beads in series with the bypass capacitor of
each supply. It is important that the analog supply be as clean
as possible.
The internal voltage reference is brought out on the FILTR pin
and should be bypassed as close as possible to the chip, with a
parallel combination of 10 mF and 100 nF. The reference voltage
may be used to bias external op amps to the common-mode
voltage of the analog input and output signal pins. The current
drawn from the VREF pin should be limited to less than 50 mA.
Power-Down and RESET
PD/RST powers down the chip and sets the control registers to
their default settings. After PD/RST is de-asserted, an initialization
routine runs inside the AD1837A to clear all memories to zero.
This initialization lasts for approximately 20 LRCLK intervals.
During this time, it is recommended that no SPI writes occur.
Serial Control Port
The AD1837A has an SPI compatible control port to permit
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal levels from the internal
peak detectors. The SPI control port is a 4-wire serial control port.
The format is similar to the Motorola SPI format except the
input data-word is 16 bits wide. The maximum serial bit clock
frequency is 12.5 MHz and may be completely asynchronous to
the sample rate of the ADCs and DACs. Figure 3 shows the
format of the SPI signal.
Power Supply and Voltage Reference
The AD1837A is designed for 5 V supplies. Separate power
supply pins are provided for the analog and digital sections.
These pins should be bypassed with 100 nF ceramic chip capaci-
tors, as close to the pins as possible, to minimize noise pickup. A
bulk aluminum electrolytic capacitor of at least 22 mF should also
be provided on the same PC board as the codec. For critical appli-
cations, improved performance will be obtained with separate sup-
plies for the analog and digital sections. If this is not possible, it is
recommended that the analog and digital supplies be isolated by
Serial Data Ports—Data Format
The ADC serial data output mode defaults to the popular I2S
format, where the data is delayed by one BCLK interval from
the edge of the LRCLK. By changing Bits 6 to 8 in ADC
–12–
REV. A
AD1837A
Control Register 2, the serial mode can be changed to right-
justified (RJ), left-justified DSP (DSP), or left-justified (LJ).
In the RJ mode, it is necessary to set Bits 4 and 5 to define the
width of the data-word.
The DAC serial data input mode defaults to I2S. By changing
Bits 5, 6, and 7 in DAC Control Register 1, the mode can be
changed to RJ, DSP, LJ, Packed Mode 1, or Packed Mode 2. The
word width defaults to 24 bits but can be changed by reprogram-
ming Bits 3 and 4 in DAC Control Register 1.
Auxiliary (TDM) Mode
A special auxiliary mode is provided to allow three external stereo
ADCs to be interfaced to the AD1837A to provide 8-in/8-out
operation. In addition, this mode supports glueless interface to a
single SHARC® DSP serial port, allowing a SHARC DSP to
access all eight channels of analog I/O. In this special mode,
many pins are redefined; see Table IV for a list of redefined pins.
The auxiliary and the TDM interfaces are independently
configurable to operate as masters or slaves. When the auxiliary
interface is set as a master, by programming the Auxiliary Mode
bit in ADC Control Register 2, AUXLRCLK and AUXBCLK are
generated by the AD1837A. When the auxiliary interface is set
as a slave, AUXLRCLK and AUXBCLK need to be generated
by an external ADC, as shown in Figure 13.
Packed Modes
The AD1837A packed mode allows a DSP or other controller to
write to all DACs and read all ADCs using one input data pin
and one output data pin. Packed Mode 256 refers to the number
of BCLKs in each frame. The LRCLK is low while data from a
left channel DAC or ADC is on the data pin and high while data
from a right channel DAC or ADC is on the data pin. DAC data is
applied on the DSDATA1 pin, and ADC data is available on the
ASDATA pin. Figures 7 to 10 show the timing for the packed
mode. Packed mode is available for 48 kHz and 96 kHz.
The TDM interface can be set to operate as a master or slave by
connecting the M/S pin to DGND or ODVDD, respectively. In
master mode, the FSTDM and BCLK signals are outputs gener-
ated by the AD1837A. In slave mode, FSTDM and BCLK are
inputs and should be generated by the SHARC. Both 48 kHz
and 96 kHz operations are available (based on a 12.288 MHz or
24.576 MHz MCLK) in this mode.
LRCLK
BCLK
LEFT CHANNEL
RIGHT CHANNEL
SDATA
MSB
LSB
MSB
LSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
BCLK
RIGHT CHANNEL
MSB
LSB
MSB
LSB
SDATA
2
I S MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
SDATA
MSB
LSB
MSB
LSB
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE, WHICH IS 2 ꢂ fS
.
3. BCLK FREQUENCY IS NORMALLY 64 ꢂ LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 4. Stereo Serial Modes
REV. A
–13–
AD1837A
ABCLK
tABL
tALS
tABDD
tALH
ALRCLK
ASDATA
LEFT-JUSTIFIED
MODE
MSB
MSB-1
ASDATA
2
I S COMPATIBLE
MODE
MSB
ASDATA
RIGHT-JUSTIFIED
MODE
LSB
MSB
Figure 5. ADC Serial Mode Timing
tDBH
DBCLK
tDBL
tDLS
tDLH
DLRCLK
tDDS
DSDATA
LEFT-JUSTIFIED
MODE
MSB
tDDH
MSB-1
tDDS
MSB
tDDH
DSDATA
2
I S COMPATIBLE
MODE
tDDS
LSB
tDDH
tDDS
MSB
tDDH
DSDATA
RIGHT-JUSTIFIED
MODE
Figure 6. DAC Serial Mode Timing
–14–
REV. A
AD1837A
LRCLK
BCLK
128 BCLKs
16 BCLKs
SLOT 1
LEFT
SLOT 5
RIGHT
ADC DATA
SLOT 2 SLOT 3 SLOT 4
SLOT 7 SLOT 8
SLOT 6
MSB
MSB – 1 MSB – 2
Figure 7a. ADC Packed Mode 128
LRCLK
BCLK
256 BCLKs
32 BCLKs
SLOT 1
LEFT
SLOT 5
RIGHT
ADC DATA
SLOT 2 SLOT 3 SLOT 4
SLOT 7 SLOT 8
SLOT 6
MSB
MSB – 1 MSB – 2
Figure 7b. ADC Packed Mode 256
LRCLK
BCLK
128 BCLKs
16 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
LEFT 1 LEFT 2 LEFT 3 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4
DAC DATA
MSB
MSB – 1 MSB – 2
Figure 8a. DAC Packed Mode 128
LRCLK
BCLK
256 BCLKs
32 BCLKs
SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8
LEFT 1 LEFT 2 LEFT 3 LEFT 4 RIGHT 1 RIGHT 2 RIGHT 3 RIGHT 4
DAC DATA
MSB
MSB – 1 MSB – 2
Figure 8b. DAC Packed Mode 256
REV. A
–15–
AD1837A
tDBH
tABH
DBCLK
ABCLK
tDBL
tDLS
tABL
tALS
DLRCLK
DSDATA
ALRCLK
ASDATA
tDLH
tALH
tABDD
tDDS
MSB
tDDH
MSB – 1
MSB
MSB – 1
Figure 9. ADC Packed Mode Timing
Figure 10. DAC Packed Mode Timing
–16–
REV. A
AD1837A
Table IV. Pin Function Changes in Auxiliary Mode
Pin Name
I2S Mode
Auxiliary Mode
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
DSDATA4 (I)/AAUXDATA3 (I)
ALRCLK (O)
I2S Data Out, Internal ADC
I2S Data In, Internal DAC1
I2S Data In, Internal DAC2
I2S Data In, Internal DAC3
I2S Data In, Internal DAC4
LRCLK for ADC
TDM Data Out to SHARC.
TDM Data In from SHARC.
AUX-I2S Data In 1 (from External ADC).
AUX-I2S Data In 2 (from External ADC).
AUX-I2S Data In 3 (from External ADC).
TDM Frame Sync Out to SHARC (FSTDM).
TDM BCLK Out to SHARC.
ABCLK (O)
BCLK for ADC
DLRCLK (I)/AUXLRCLK (I/O)
LRCLK In/Out Internal DACs
AUX LRCLK In/Out. Driven by external LRCLK from
ADC in slave mode. In master mode, driven by
MCLK/512.
DBCLK (I)/AUXBCLK (I/O)
BCLK In/Out Internal DACs
AUX BCLK In/Out. Driven by external BCLK from ADC
in slave mode. In master mode, driven by MCLK/8.
FSTDM
BCLK
TDM
MSB TDM
MSB TDM
1ST
8TH
ASDATA1
CH
CH
TDM (OUT)
INTERNAL
INTERNAL
AUX_ADC R3
AUX_ADC R2
AUX_ADC R4
MSB TDM
AUX_ADC L4
AUX_ADC L2
AUX_ADC L3
ASDATA
ADC L1
ADC R1
32
MSB TDM
1ST
8TH
DSDATA1
TDM (IN)
CH
CH
INTERNAL
INTERNAL
DAC L2
INTERNAL
DAC L3
INTERNAL
DAC L4
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
INTERNAL
DAC R4
DSDATA1
DAC L1
32
AUX
2
LRCLK I S
RIGHT
LEFT
(FROM AUX ADC NO. 1)
AUX
2
BCLK I S
(FROM AUX ADC NO. 1)
AAUXDATA1 (IN)
2
2
I S – MSB RIGHT
I S – MSB LEFT
(FROM AUX ADC NO. 1)
AAUXDATA2 (IN)
2
2
I S – MSB LEFT
I S – MSB RIGHT
(FROM AUX ADC NO. 2)
AAUXDATA3 (IN)
2
2
I S – MSB LEFT
I S – MSB RIGHT
(FROM AUX ADC NO. 3)
AUX BCLK FREQUENCY IS 64 ꢂ FRAME RATE; TDM BCLK FREQUENCY IS 256 ꢂ FRAME RATE.
Figure 11. Auxiliary Mode Timing
REV. A
–17–
AD1837A
30MHz
SHARC IS ALWAYS
SHARC
RUNNING IN SLAVE MODE
(INTERRUPT DRIVEN).
12.288MHz
LRCLK
BCLK
DATA
MCLK
ADC
NO. 1
SLAVE
LRCLK
BCLK
DATA
MCLK
ADC
NO. 2
ASDATA FSTDM
BCLK DSDATA1
SLAVE
DBCLK/AUXBCLK
DLRCLK/AUXLRCLK
DSDATA2/AAUXDATA1
DSDATA3/AAUXDATA2
DSDATA4/AAUXDATA3
MCLK
LRCLK
BCLK
DATA
MCLK
ADC
NO. 3
AD1837A
MASTER
SLAVE
Figure 12. Auxiliary Mode Connection (Master Mode) to SHARC
30MHz
SHARC IS ALWAYS
SHARC
RUNNING IN SLAVE MODE
(INTERRUPT DRIVEN).
12.288MHz
LRCLK
BCLK
DATA
MCLK
ADC
NO. 1
MASTER
LRCLK
BCLK
DATA
MCLK
ADC
NO. 2
ASDATA FSTDM
BCLK DSDATA1
SLAVE
DBCLK/AUXBCLK
DLRCLK/AUXLRCLK
DSDATA2/AAUXDATA1
DSDATA3/AAUXDATA2
DSDATA4/AAUXDATA3
MCLK
LRCLK
BCLK
DATA
MCLK
ADC
NO. 3
AD1837A
SLAVE
SLAVE
Figure 13. Auxiliary Mode Connection (Slave Mode) to SHARC
–18–
REV. A
AD1837A
CONTROL/STATUS REGISTERS
DAC Volume Control
The AD1837A has 15 control registers, 13 of which are used to
set the operating mode of the part. The other two registers,
ADC Peak 0 and ADC Peak 1, are read-only and should not be
programmed. Each of the registers is 10 bits wide with the
exception of the ADC peak reading registers which are six bits
wide. Writing to a control register requires a 16-bit data frame
to be transmitted. Bits 15 to 12 are the address bits of the
required register. Bit 11 is a read/write bit. Bit 10 is reserved
and should always be programmed to 0. Bits 9 to 0 contain the
10-bit value that is to be written to the register or, in the case of
a read operation, the 10-bit register contents. Figure 3 shows
the format of the SPI read and write operation.
Each DAC in the AD1837A has its own independent volume
control. The volume of each DAC can be adjusted in 1024
linear steps by programming the appropriate register. The
default value for this register is 1023, which provides no attenu-
ation, i.e., full volume.
ADC CONTROL REGISTERS
The AD1837A register map has five registers that are used to
control the functionality and read the status of the ADCs. The
function of the bits in each of these registers is discussed in the
following sections.
ADC Peak Level
These two registers store the peak ADC result from each channel
when the ADC peak readback function is enabled. The peak result
is stored as a 6-bit number from 0 dB to –63 dB in 1 dB steps.
The value contained in the register is reset once it has been read,
allowing for continuous level adjustment as required. Note that
the ADC peak level registers use the 6 MSB in the register to
store the results.
DAC CONTROL REGISTERS
The AD1837A register map has 10 registers that control the
functionality of the DAC section of the part. The function of the
bits in these registers is discussed in the following sections.
Sample Rate
These bits control the sample rate of the DACs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz, 96 kHz, and
192 kHz are available. The MCLK scaling bits in ADC Control 3
should be programmed appropriately, based on the master
clock frequency.
Sample Rate
This bit controls the sample rate of the ADCs. Based on a
24.576 MHz IMCLK, sample rates of 48 kHz and 96 kHz are
available. The MCLK scaling bits in ADC Control Register 3
should be programmed appropriately based on the master clock
frequency.
Power-Down/Reset
This bit controls the power-down status of the DAC section.
By default, normal mode is selected, but by setting this bit, the
digital section of the DAC stage can be put into a low power
mode, thus reducing the digital current. The analog output
section of the DAC stage is not powered down.
ADC Power-Down
This bit controls the power-down status of the ADC section and
operates in a similar manner to the DAC power-down.
High-Pass Filter
DAC Data-Word Width
The ADC signal path has a digital high-pass filter. Enabling this
filter removes the effect of any dc offset in the analog input
signal from the digital output codes.
These two bits set the word width of the DAC data. Compact
disc (CD) compatibility may require 16 bits, but many modern
digital audio formats require 24-bit sample resolution.
ADC Data-Word Width
These two bits set the word width of the ADC data.
DAC Data Format
The AD1837A serial data interface can be configured to be
compatible with a choice of popular interface formats including
I2S, LJ, RJ, or DSP modes. Details of these interface modes
are given in the Serial Data Port section of this data sheet.
ADC Data Format
The AD1837A serial data interface can be configured to be
compatible with a choice of popular interface formats, including
I2S, LJ, RJ, or DSP modes.
De-emphasis
Master/Slave Auxiliary Mode
The AD1837A provides built-in de-emphasis filtering for the
three standard sample rates of 32.0 kHz, 44.1 kHz, and 48 kHz.
When the AD1837A is operating in the auxiliary mode, the
auxiliary ADC control pins, AUXBCLK and AUXLRCLK, that
connect to the external ADCs, can be set to operate as a master
or slave. If the pins are set in slave mode, one of the external
ADCs should provide the LRCLK and BCLK signals.
Mute DAC
Each of the eight DACs in the AD1837A has its own independent
mute control. Setting the appropriate bit mutes the DAC out-
put. The AD1837A uses a clickless mute function that attenuates
the output to approximately –100 dB over a number of cycles.
ADC Peak Readback
Setting this bit enables ADC peak reading. See the ADCs section
for more information.
Stereo Replicate
Setting this bit copies the digital data sent to the stereo pair DAC1
to the three other stereo DACs in the system. This allows all
four stereo DACs to be driven by one digital data stream. Note
that in this mode, DAC data sent to the other DACs is ignored.
REV. A
–19–
AD1837A
Table V. Control Register Map
Register Name Description Type
Register Address
Width
Reset Setting (Hex)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DACCTRL1
DACCTRL2
DACVOL1
DACVOL2
DACVOL3
DACVOL4
DACVOL5
DACVOL6
DACVOL7
DACVOL8
ADCPeak0
ADCPeak1
ADCCTRL1
ADCCTRL2
ADCCTRL3
Reserved
DAC Control 1
DAC Control 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
10
10
10
10
10
10
10
10
10
10
6
000
000
DAC Volume—Left 1
DAC Volume—Right 1
DAC Volume—Left 2
DAC Volume—Right 2
DAC Volume—Left 3
DAC Volume—Right 3
DAC Volume—Left 4
DAC Volume—Right 4
ADC Left Peak
ADC Right Peak
ADC Control 1
ADC Control 2
ADC Control 3
3FF
3FF
3FF
3FF
3FF
3FF
3FF
3FF
000
000
000
000
000
R
6
R/W
R/W
R/W
R/W
10
10
10
10
Reserved
Reserved
Table VI. DAC Control 1
Function
DAC Data-
Word Width
Power-Down
Reset
Address
15, 14, 13, 12 11
0000
R/W RES De-emphasis
DAC Data Format
Sample Rate
10
0
9, 8
7, 6, 5
000 = I2S
001 = RJ
010 = DSP
4, 3
2
1, 0
0
00 = None
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = Normal
1 = Power-Down 01 = 96 kHz
10 = 192 kHz
00 = 48 kHz
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
011 = LJ
11 = 48 kHz
100 = Packed 256
101 = Packed 128
110 = Reserved
111 = Reserved
Table VII. DAC Control 2
Function
MUTE DAC
OUTL4 OUTR3 OUTL3 OUTR2
Stereo
Replicate
Address R/W RES RES
OUTR4
OUTL2 OUTR1 OUTL1
15, 14,
13, 12
11
0
10
0
9
0
8
7
6
5
4
3
2
1
0
0001
0 = Off
0 = On
0 = On
0 = On
0 = On
0 = On
0 = On
0 = On
0 = On
1 = Replicate 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute 1 = Mute
–20–
REV. A
AD1837A
Table VIII. DAC Volume Control
Table IX. ADC Peak
Function
DAC Volume
Function
Four
Address
R/W
11
RES
10
Address
R/W RES Six Data Bits
Fixed Bits
3, 2, 1, 0
0000
15, 14, 13, 12
9, 8, 7, 6, 5, 4, 3, 2, 1, 0
15, 14, 13, 12
11
1
10
0
9, 8, 7, 6, 5, 4
0010 = DACL1
0011 = DACR1
0100 = DACL2
0101 = DACR2
0110 = DACL3
0111 = DACR3
1000 = DACL4
1001 = DACR4
0
0
0000000000 = Mute
0000000001 = 1/1023
0000000010 = 2/1023
1111111110 = 1022/1023
1111111111 = 1023/1023
1010 = Left ADC
1011 = Right ADC
000000 = 0 dBFS
000001 = –1 dBFS
000010 = –2 dBFS These
four bits
are always
zero.
111111 = –63 dBFS
Table X. ADC Control 1
Function
ADC
Sample
Address
R/W
RES
Reserved
Filter
Power-Down
Rate
Reserved
15, 14, 13, 12
1100
11
0
10
0
9
0
8
7
6
5, 4, 3, 2, 1, 0
0 = All Pass
1 = High-Pass
0 = Normal
1 = Power-Down
0 = 48 kHz
1 = 96 kHz
0, 0, 0, 0, 0, 0
0, 0, 0, 0, 0, 0
Table XI. ADC Control 2
Function
R/W
RES
Master/Slave
Aux Mode
ADC
Data Format
ADC Data-
Word Width
ADC MUTE
Address
RES
Reserved
Right
Left
15, 14, 13, 12
1101
11
0
10
0
9
8, 7, 6
000 = I2S
001 = RJ
010 = DSP
5, 4
3, 2
0, 0
1
0
0 = Slave
1 = Master
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = On
1 = Mute
0 = On
1 = Mute
011 = LJ
100 = Packed 256
101 = Packed 128
110 = Auxiliary 256
111 = Auxiliary 512
Table XII. ADC Control 3
Function
DAC
R/W
IMCLK
ADC
ADC
Address
RES RES Reserved Clocking Scaling
Peak Readback
Test Mode
Test Mode
15, 14,
13, 12
11
0
10
0
9, 8
0, 0
7, 6
5
4, 3, 2
1, 0
1110
00 = MCLK ꢀ 2
01 = MCLK
0 = Disabled Peak Readback 000 = Normal Mode 00 = Normal Mode
1 = Enabled Peak Readback All others reserved
All others reserved
10 = MCLK ꢀ 2/3
11 = MCLK ꢀ 2
REV. A
–21–
AD1837A
CASCADE MODE
Dual AD1837A Cascade
With Device 1 set as a master, it will generate the frame-sync
and bit clock signals. These signals are sent to the SHARC and
Device 2 ensuring that both know when to send and receive data.
The AD1837A can be cascaded to an additional AD1837A,
which, in addition to six external stereo ADCs, can be used to
create a 32-channel audio system with 16 inputs and 16 outputs.
The cascade is designed to connect to a SHARC DSP and operates
in a time division multiplexing (TDM) format. Figure 14 shows
the connection diagram for cascade operation. The digital inter-
face for both parts must be set to operate in Auxiliary 512 mode
by programming ADC Control Register 2. AD1837A No. 1 is
set as a master device by connecting the M/S pin to DGND and
AD1837A No.2 is set as a slave device by connecting the M/S to
ODVDD. Both devices should be run from the same MCLK
and PD/RST signals to ensure that they are synchronized.
The cascade can be thought of as two 256-bit shift registers, one
for each device. At the beginning of a sample interval, the shift
registers contain the ADC results from the previous sample
interval. The first shift register (Device 1) clocks data into the
SHARC and also clocks in data from the second shift register
(Device 2). While this is happening, the SHARC is sending
DAC data to the second shift register. By the end of the sample
interval, all 512 bits of ADC data in the shift registers will have
been clocked into the SHARC and been replaced by DAC data,
which is subsequently written to the DACs. Figure 15 shows the
timing diagram for the cascade operation.
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AUX ADC
(SLAVE)
AD1837A NO. 1
(MASTER)
AD1837A NO. 2
(SLAVE)
DRx
RFSx
RCLKx
DSDATA
ASDATA
ALRCLK
ABCLK
ASDATA
ALRCLK
ABCLK
DSDATA
SHARC
(SLAVE)
TFSx
TCLKx
DTx
Figure 14. AD1837A Cascade
256 ABCLKs
256 ABCLKs
TFSx/
RFSx
AD1837A NO. 1 DACs
L3 L4 R1 R2
AD1837A NO. 2 DACs
DTx
L1
L1
L2
L2
R3
R3
R4
R4
L1
L1
L2
L2
L3
L4
R1
R2
R3
R4
R4
AD1837A NO. 1 ADCs
L3 L4 R1 R2
AD1837A NO. 2 ADCs
L3 L4 R1 R2
DRx
R3
ABCLK
LSB
LSB
MSB MSB –1
MSB
DON’T CARE
DTx
DRx
MSB –1
32 ABCLKs
Figure 15. AD1837A Cascade Timing
–22–
REV. A
AD1837A
47ꢄF
600Z
5.76kꢃ
5.76kꢃ
+
AUDIO
INPUT
120pF NPO
100pF
NPO
68pF
NPO
11kꢃ
3.01kꢃ
V
BIAS
(2.25V)
237ꢃ
OP275
ADCxN
11kꢃ
270pF
NPO
V
REF
1nF
NPO
AUDIO
OP275
OUTPUT
604ꢃ
100pF
NPO
2.2nF
560pF
NPO
5.76kꢃ
750kꢃ
5.76kꢃ
NPO
OUTx
1nF
5.62kꢃ
1.5kꢃ
NPO
150pF
NPO
5.62kꢃ
237ꢃ
OP275
ADCxP
V
REF
Figure 16. Typical ADC Input Filter Circuit
Figure 17. Typical DAC Output Filter Circuit
REV. A
–23–
AD1837A
OUTLINE DIMENSIONS
52-Lead Metric Quad Flat Package [MQFP]
(S-52-1)
Dimensions shown in millimeters
13.45
1.03
0.88
0.73
13.20 SQ
12.95
2.45
MAX
39
27
40
26
SEATING
PLANE
10.20
10.00 SQ
9.80
7.80
REF
TOP VIEW
(PINS DOWN)
10ꢅ
6ꢅ
2ꢅ
2.20
2.00
1.80
0.23
0.11
VIEW A
7ꢅ
0ꢅ
PIN 1
0.25
MAX
52
14
0.13 MIN
1
13
COPLANARITY
0.65 BSC
0.40
0.22
COMPLIANT TO JEDEC STANDARDS MS-022-AC.
Revision History
Location
Page
1/04—Data Sheet changed from REV. 0 to REV. A.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Deleted Clock Signals section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Added AD1835A CLOCKING SCHEME section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Added Table II and Table III and renumbered following tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Changes to Auxiliary (TDM Mode) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Changes to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Changes to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Added Figures 7a and 8a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Renumbered Figure 7 and Figure 8 to Figure 7b and Figure 8b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Changes to Table VIII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
–24–
REV. A
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