EVAL-AD1836AEB [ADI]
Multichannel 96 kHz Codec; 多通道96 kHz的编解码器
| 型号： | EVAL-AD1836AEB |
| 厂家： | 
ADI |
| 描述： | Multichannel 96 kHz Codec |
| 文件： | 总24页 (文件大小：1208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multichannel 96 kHz Codec
AD1836A
FEATURES
APPLICATIONS
5 V multichannel audio system
Accepts 16-/18-/20-/24-bit data
Supports 24-bit and 96 kHz sample rate
Multibit Σ-∆ modulators with data directed
scrambling
Home theater systems
Automotive audio systems
DVD recorders
Set-top boxes
Digital audio effects processors
Differential output for optimum performance
ADCs: –92 dB THD + N, 105 dB SNR and dynamic range
DACs: –95 dB THD + N, 108 dB SNR and dynamic range
On-chip volume control with "auto-ramp" function
Programmable gain amplifier for ADC input
Hardware and software controllable clickless mute
Digital de-emphasis processing
Supports 256 × fS, 512 × fS, or 768 × fS master clock
Power-down mode plus soft power-down mode
Flexible serial data port with right justified, left justified, I2S
compatible, and DSP serial port modes
TDM interface mode supports 8 in/8 out using a single
SHARC® SPORT
PRODUCT OVERVIEW
The AD1836A is a high performance, single-chip codec that
provides three stereo DACs and two stereo ADCs using ADI’s
patented multibit Σ-∆ architecture. An SPI® port is included,
allowing a microcontroller to adjust volume and many other
parameters. The AD1836A operates from a 5 V supply, with
provision for a separate output supply to interface with low
voltage external circuitry. The AD1836A is available in a 52-lead
MQFP (PQFP) package.
52-lead MQFP (PQFP) plastic package
FUNCTIONAL BLOCK DIAGRAM
CCLK CDATA CLATCH COUT
MCLK
DLRCLK
DBCLK
CLOCK
CONTROL PORT
DSDATA1
DSDATA2
DSDATA3
SERIAL
DATA
I/O
VOLUME
VOLUME
DAC1L
DAC1R
PORT
DIGITAL
FILTER
Σ-∆
ALRCLK
ABCLK
DAC
ASDATA1
ASDATA2
DAC2L
DAC2R
VOLUME
VOLUME
Σ-∆
DIGITAL
FILTER
DIGITAL
FILTER
Σ-∆
ADC1L
ADC1R
ADC1L
DAC
48kHz/96kHz
48kHz/96kHz
Σ-∆
DIGITAL
FILTER
ADC1R
48kHz/96kHz
48kHz/96kHz
DAC3L
DAC3R
VOLUME
DIGITAL
FILTER
Σ-∆
CAPL1
ADC2L1
DAC
VOLUME
DIGITAL
Σ-∆
ADC2L
48kHz
FILTER
48kHz
PGA
PGA
ADC2L2
CAPL2
CAPR1
ADC2R1
ADC2R2
CAPR2
FILTD
FILTR
Σ-∆
DIGITAL
FILTER
48kHz
ADC2R
48kHz
V
REF
2
2
4
3
PD/RST
AVDD
AGND
DVDD
DGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD1836A
TABLE OF CONTENTS
AD1836A—Specifications............................................................... 3
Serial Control Port ..................................................................... 12
Power Supply and Voltage Reference....................................... 13
Serial Data Ports—Data Format............................................... 13
SPI Control Registers................................................................. 19
Outline Dimensions....................................................................... 23
ESD Caution................................................................................ 23
Ordering Guide .......................................................................... 23
Absolute Maximum Ratings............................................................ 8
Pin Configuration And Pin Functional Descriptions.................. 9
Functional Overview...................................................................... 11
ADCs............................................................................................ 11
DACs ............................................................................................ 11
Clock Signals............................................................................... 11
Reset and Power-Down ............................................................. 12
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD1836A
AD1836A—SPECIFICATIONS
Table 1. Test conditions, unless otherwise noted. Performance of all channels is identical (exclusive of the Interchannel Gain
Mismatch and Interchannel Phase Deviation specifications).
Parameter
Rating
Supply Voltages (AVDD, DVDD)
Ambient Temperature
Master Clock
5 V
25°C
12.288 MHz (48 kHz fS, 256 × fS Mode)
Input Signal
1.000 kHz, 0 dBFS (Full Scale)
Input Sample Rate
Measurement Bandwidth
Word Width
48 kHz
20 Hz to 20 kHz
24 Bits
Load Capacitance (Digital Output)
Load Impedance (Digital Output)
Input Voltage HI
100 pF
2.5 kΩ
2.4 V
Input Voltage LO
0.8 V
Rev. 0 | Page 3 of 24
AD1836A
Table 2. Analog Performance
Parameter
Min Typ
Max Unit
ADC Resolution (all ADCs)
24
Bits
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)1, 2
No Filter (RMS), AD1836AAS
With A-Weighted Filter (RMS), AD1836AAS
No Filter (RMS), AD1836ACS
With A-Weighted Filter (RMS), AD1836ACS
Total Harmonic Distortion + Noise (–1 dBFS)1
Full-Scale Input Voltage (Differential)
Gain Error
97
102
dB
dB
dB
dB
100
94
105
99
97
102
–92
–83
dB
2.18 (6.16)
V rms (V pp)
%
–5.0
–0.1
–10
+5.0
Interchannel Gain Mismatch
Offset Error
+0.1 dB
0
+10
mV
ppm/°C
dB
ANALOG-TO-DIGITAL CONVERTERS
Gain Drift
100
–110
12
Interchannel Isolation
Programmable Input Gain
dB
Gain Step Size
3
dB
CMRR, Direct Input, 100 mV RMS, 1 kHz
CMRR, Direct Input, 100 mV RMS, 20 kHz
CMRR, PGA Differential Input, 100 mV RMS, 1 kHz
CMRR, PGA Differential Input, 100 mV RMS, 20 kHz
Input Resistance
–77
–72
–57
–57
–63
–60
–39
–39
dB
dB
dB
dB
10
kΩ
pF
Input Capacitance
15
Common-Mode Input Volts
Dynamic Range (20 Hz to 20 kHz, –60 dB Input)1, 2
No Filter (RMS), AD1836AAS
With A-Weighted Filter (RMS), AD1836AAS
No Filter (RMS), AD1836ACS
With A-Weighted Filter (RMS), AD1836ACS
Total Harmonic Distortion + Noise (0 dBFS)1
Full-Scale Output Voltage (Differential)
Gain Error
2.25
V
102
105
99
105
dB
108
dB
102
dB
102
105
dB
–95
–85
dB
2.0 (5.6)
V rms (V pp)
%
–6.0
–0.3
15
+6.0
Interchannel Gain Mismatch
Offset Error
+0.3 dB
DIGITAL-TO-ANALOG CONVERTERS
55
95
mV
Gain Drift
150
–110
0.1
ppm/°C
dB
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Max Attenuation)
Max Attenuation
Degrees
%
0.098
60
dB
–100
dB
De-emphasis Gain Error
0.1 dB
Output Resistance at Each Pin
115
Ω
V
V
REF (FILTR), Common-Mode Output
2.2
2.25
2.3
1 Total harmonic distortion + noise and dynamic range typical specifications are for two channels active, max/min are all channels active.
2 Measured with Audio Precision System Two Cascade in rms mode. Averaging mode will show approximately 2 dB better performance.
Rev. 0 | Page 4 of 24
AD1836A
Table 3. Digital I/O
Parameter
Min
Typ
Max
Unit
V
Input Voltage HI (VIH)
2.2
Input Voltage LO (VIL)
0.8
10
10
V
Input Leakage (IIH @ VIH = 2.4 V)
Input Leakage (IIL @ VIL = 0.8 V)
High Level Output Voltage (VOH) IOH = 2 mA
Low Level Output Voltage (VOL) IOL = 2 mA
Input Capacitance
µA
µA
V
V
pF
ODVDD – 0.4
0.5
20
Table 4. Power Supplies
Parameter
Min
4.75
3.0
Typ
Max
Unit
V
Voltage, DVDD and AVDD
5
5.25
5.25
Voltage, ODVDD
3.3/5
108
47
V
Analog Current
mA
mA
mA
mA
mW
mW
mW
mW
dB
Supplies
Analog Current—Power-Down
Digital Current
78
Digital Current—Power-Down
Operation—Both Supplies
Operation—Analog Supplies
Operation—Digital Supplies
Power-Down—Both Supplies
1.5
930
540
390
243
–60
–50
Dissipation
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
Power Supply Rejection Ratio
dB
Table 5. Temperature Range
Parameter
Min
Typ
Max
Unit
Specifications Guaranteed
25
°C
–40
–40
–65
+85
+110
+150
°C Ambient
°C Case
°C
Functionality Guaranteed
Storage
Table 6. Digital Filter @ 44.1 kHz
Parameter
Min
Typ
20
0.0001
Max
Unit
Pass Band
kHz
dB
Pass-Band Ripple
Transition Band
Stop Band
22
kHz
kHz
dB
ADC DECIMATION FILTER
24
Stop-Band Attenuation
Group Delay
120
990.20
20
µs
Pass Band
kHz
dB
Pass-Band Ripple
Transition Band
Stop Band
0.01
22
kHz
kHz
dB
DAC INTERPOLATION FILTER
24
Stop-Band Attenuation
Group Delay
70
446.35
µs
Rev. 0 | Page 5 of 24
AD1836A
Table 7. Timing Specifications
Parameter
Comments
Min
18
Max Unit
tMH
tML
MCLK High
MCLK Low
512 × fS Mode
512 × fS Mode
512 × fS Mode
512 × fS Mode
ns
ns
ns
18
tMCLK MCLK Period
36
MASTER CLOCK AND RESET
fMCLK MCLK Frequency
27
MHz
ns
tPDR
PD/RST Low
5
tPDRR
tCHH
tCHL
tCDS
tCDH
PD/RST Recovery
CCLK High
Reset to Active Output
4500
10
10
5
tMCLK
ns
CCLK Low
ns
CDATA Setup
CDATA Hold
To CCLK Rising
ns
From CCLK Rising
5
ns
tCLS
tCLH
CLATCH Setup
CLATCH Hold
To CCLK Rising
5
5
ns
SPI PORT
From CCLK Falling
From CCLK Falling
From CCLK Falling
From CCLK Falling
From CCLK Falling
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCODE COUT Enable
10
10
tCOD
tCOH
tCOTS
tDBH
tDBL
fDB
COUT Delay
COUT Hold
0
COUT Three-State
DBCLK High
10
15
DBCLK Low
15
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
DBCLK High
64 × fS
DAC SERIAL PORT
(Normal Modes)
tDLS
tDLH
tDDS
tDDH
tDBH
tDBL
fDB
To DBCLK Rising
From DBCLK Rising
To DBCLK Rising
From DBCLK Rising
0
10
0
20
15
DBCLK Low
15
DBCLK Frequency
DLRCLK Setup
DLRCLK Hold
DSDATA Setup
DSDATA Hold
ABCLK Delay
256 × fS
DAC SERIAL PORT
(Packed 128 Mode, Packed 256 Mode)
tDLS
tDLH
tDDS
tDDH
tABD
To DBCLK Rising
0
From DBCLK Rising
10
0
To DBCLK Rising
From DBCLK Rising
20
From MCLK Transition, 256 × fS Mode
From MCLK Rising, 512 × fS Mode
From ABCLK Falling
15
ADC SERIAL PORT
(Normal Modes)
tALS
LRCLK Skew
–2
–2
–2
+2
5
ns
ns
ns
tABDD ASDATA Delay
From ABCLK Falling
tABD
tALS
ABCLK Delay
LRCLK Skew
From MCLK Transition, 256 × fS Mode
From MCLK Rising, 512 × fS Mode
From ABCLK Falling
15
ADC SERIAL PORT
(Packed 128 Mode, Packed 256 Mode)
+2
5
ns
ns
ns
tABDD ASDATA Delay
From ABCLK Falling
tABD
ABCLK Delay
From MCLK Transition, 256 × fS Mode
From MCLK Rising, 512 × fS Mode
From ABCLK Falling
15
tALS
LRCLK Skew
+2
5
ns
ns
ns
ns
ns
ns
ns
ADC SERIAL PORT
(TDM Packed AUX)
tABDD ASDATA Delay
From ABCLK Falling
tDDS
tDDH
DSDATA1 Hold
DSDATA1 Hold
To ABCLK Rising
0
From ABCLK Rising
7
tAXDS AAUXDATA Setup
tAXDH AAUXDATA Hold
tDXDD DAUXDATA Delay
To AUXBCLK Rising
7
AUXILIARY INTERFACE
From AUXBCLK Rising
From AUXBCLK Falling
10
25
Rev. 0 | Page 6 of 24
AD1836A
Table 7. Timing Specifications (Continued)
Parameter
Comments
Min
Max Unit
tXBD
AUXBCLK Delay
From MCLK Transition, 256 × fS Mode
From MCLK Rising, 512 × fS Mode
From AUXBCLK Falling
15
ns
AUXILIARY INTERFACE
(Master Mode)
tXLS
AUXLRCLK Skew
AUXBCLK High
–3
+3
ns
ns
ns
ns
ns
ns
tXBH
tXBL
60
AUXBCLK Low
60
AUXILIARY INTERFACE
fXB
AUXBCLK Frequency
AUXLRCLK Setup
AUXLRCLK Hold
64 × fS
5
(Slave Mode)
tDLS
tDLH
To AUXBCLK Rising
From AUXBCLK Rising
15
Rev. 0 | Page 7 of 24
AD1836A
ABSOLUTE MAXIMUM RATINGS
Table 8. AD1836A Absolute Maximum Ratings
Parameter
Min
–0.3
–0.3
Max
Unit
V
V
Analog (AVDD)
Digital (DVDD)
+6
+6
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Ambient Temperature (Operating)
20
mA
V
V
–0.3
–0.3
–40
AVDD + 0.3
DVDD + 0.3
+85
°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other condition s above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions may affect device reliability.
Table 9. Package Characteristics
Parameter
Min
Typ
45
Max
Unit
°C/W
°C/W
θJA (Thermal Resistance [Junction to Ambient])
θJC (Thermal Resistance [Junction to Case])
18
Rev. 0 | Page 8 of 24
AD1836A
PIN CONFIGURATION AND PIN FUNCTIONAL DESCRIPTIONS
52 51 50 49 48 47 46 45 44 43 42 41 40
1
2
39
38
37
36
35
34
33
32
31
30
29
28
27
DVDD
CDATA
PD/RST
OUTLP3
OUTLN3
OUTLP2
OUTLN2
OUTLP1
OUTLN1
AVDD
DGND
DSDATA1
DBCLK
PIN 1
IDENTIFIER
3
4
DLRCLK
OUTRP3
OUTRN3
OUTRP2
OUTRN2
OUTRP1
OUTRN1
AGND
5
6
7
AD1836A
TOP VIEW
(Not to Scale)
8
9
10
11
12
AGND
FILTD
FILTR
AGND
ADC2INRP/CAPR2
13
14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 2. 52-Lead MQFP
Table 10. Pin Function Descriptions—52-Lead MQFP
Pin No.
In/Out Mnemonic
Description
1
2
3
I
I
I
DVDD
Digital Power Supply. Connect to digital 5 V supply.
Serial Control Input.
Power-Down Reset (Active Low).
CDATA
PD/RST
OUTLP3
OUTLN3
OUTLP2
OUTLN2
OUTLP1
OUTLN1
AVDD
AGND
FILTD
FILTR
AGND
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
DAC 3 Left Positive Output.
DAC 3 Left Negative Output.
DAC 2 Left Positive Output.
DAC 2 Left Negative Output.
DAC 1 Left Positive Output.
DAC 1 Left Negative Output.
Analog Power Supply. Connect to analog 5 V.
Analog Ground.
Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
Voltage Reference Filter Capacitor Connection. Bypass with 10 µF||100 nF to AGND.
Analog Ground.
Analog Power Supply. Connect to analog 5 V supply.
ADC1 Left Positive Input.
ADC1 Left Negative Input.
AVDD
ADC1INLP
ADC1INLN
ADC1INRP
ADC1INRN
ADC1 Right Positive Input.
ADC1 Right Negative Input.
ADC2INLP/CAPL2 ADC2 Left Positive Input (Direct Mode)/ADC2 Left Decoupling Cap (MUX/PGA and PGA Differential Mode).
ADC2INLN/CAPL1 ADC2 Left Negative Input (Direct Mode)/ADC2 Left Decoupling Capacitor
(MUX/PGA and PGA Differential Mode).
22
23
24
25
26
I
I
I
I
I
ADC2INL1
ADC2INL2
ADC2INR2
ADC2INR1
ADC2 Left Input 1 (MUX/PGA Mode)/Left Positive Input (PGA Differential Mode).
ADC2 Left Input 2 (MUX/PGA Mode)/Left Negative Input (PGA Differential Mode).
ADC2 Right Input 2 (MUX/PGA Mode)/Right Negative Input (PGA Differential Mode).
ADC2 Right Input 1 (MUX/PGA Mode)/Right Positive Input (PGA Differential Mode).
ADC2INRN/CAPR1 ADC2 Right Negative Input (Direct Mode)/ADC2 Right Decoupling Capacitor
(MUX/PGA and PGA Differential Mode).
Rev. 0 | Page 9 of 24
AD1836A
Pin No.
In/Out Mnemonic
Description
27
I
ADC2INRP/CAPR2 ADC2 Right Positive Input (Direct Mode)/ADC2 Right Decoupling Capacitor
(MUX/PGA and PGA Differential Mode).
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I
I
AGND
AGND
Analog Ground.
Analog Ground.
O
O
O
O
O
O
I/O
I/O
I
I
I
I
I
OUTRN1
OUTRP1
OUTRN2
OUTRP2
OUTRN3
OUTRP3
DLRCLK
DBCLK
DSDATA1
DGND
DVDD
DSDATA2
DSDATA3
ABCLK
ALRCLK
MCLK
DAC 1 Right Negative Output.
DAC 1 Right Positive Output.
DAC 2 Right Negative Output.
DAC 2 Right Positive Output.
DAC 3 Right Negative Output.
DAC 3 Right Positive Output.
LR Clock for DACs.
Bit Clock for DACs.
DAC Input 1 (Input to DAC 1 L and R).
Digital Ground.
Digital Power Supply. Connect to digital 5 V supply.
DAC Input 2 (Input to DAC 2 L and R).
DAC Input 3 (Input to DAC 3 L and R).
Bit Clock for ADCs.
LR Clock for ADCs.
Master Clock Input.
O
O
I
I
ODVDD
ASDATA1
ASDATA2
COUT
Digital Output Driver Power Supply. Connect to 3.3 V or 5 V logic supply.
ADC Serial Data Output 1 (ADC 1 L and R).
ADC Serial Data Output 2 (ADC 2 L and R).
Output for Control Data.
O
O
O
I
Latch Input for Control Data.
CLATCH
CCLK
DGND
51
52
I
I
Control Clock Input for Control Data.
Digital Ground.
Rev. 0 | Page 10 of 24
AD1836A
FUNCTIONAL OVERVIEW
ADCs
There are four ADC channels in the AD1836A configured as
two independent stereo pairs. One stereo pair is the primary
ADC and has fully differential inputs. The second pair can be
programmed to operate in one of three possible input modes
(programmed via SPI ADC Control Register 3). The ADC
section may also operate at a sample rate of 96 kHz with only
the two primary channels active. The ADCs include an
on-board digital decimation filter with 120 dB stop-band
attenuation and linear phase response, operating at an over-
sampling ratio of 128 (for 4-channel 48 kHz operation) or 64
(for 2-channel 96 kHz operation).
The voltage at the VREF pin, FILTR (~2.25 V), can be used to bias
external op amps that buffer the input signals. See the Power
Supply and Voltage Reference section.
DACs
The AD1836A has six DAC channels arranged as three
independent stereo pairs, with six fully differential analog
outputs for improved noise and distortion performance. Each
channel has its own independently programmable attenuator,
adjustable in 1024 linear steps. Digital inputs are supplied
through three serial data input pins (one for each stereo pair)
and a common frame (DLRCLK) and bit (DBCLK) clock.
Alternatively, one of the “packed data” modes may be used to
access all six channels on a single TDM data pin.
The primary ADC pair should be driven from a differential
signal source for best performance. The input pins of the
primary ADC connect directly to the internal switched
capacitors. To isolate the external driving op amp from the
“glitches” caused by the internal switched capacitors, each input
pin should be isolated by using a series-connected external
100 Ω resistor together with a 1 nF capacitor connected from
each input to ground. This capacitor must be of high quality, for
example, ceramic NPO or polypropylene film.
Each set of differential output pins sits at the dc level of VREF
and swings 1.4 V for a 0 dB digital input signal. A single op
amp third order external low-pass filter is recommended to
remove high frequency noise present on the output pins, as well
as to provide differential-to-single-ended conversion. Note that
the use of op amps with low slew rate or low bandwidth may
cause high frequency noise and tones to fold down into the audio
band; care should be exercised in selecting these components.
The secondary input pair can operate in one of three modes:
•
Direct differential inputs (driven the same way as the
primary ADC inputs described above).
The voltage at the VREF pin, FILTR (~2.25 V), can be used to bias
the external op amps that buffer the output signals. See the
Power Supply and Voltage Reference section.
•
PGA mode with differential inputs. In this mode, the PGA
amplifier can be programmed using the SPI port to give an
input gain of 0 dB to 12 dB in steps of 3 dB. External
capacitors are used after the PGA to supply filtering for the
switched capacitor inputs.
CLOCK SIGNALS
The master clock frequency can be selected for 256, 512, or 768
times the sample rate. The default at power-up is 256 × fS. For
operation at 96 kHz, the master clock frequency should stay at
the same absolute frequency. For example, if the AD1836A is
programmed in 256 × fS, 48 kHz mode, the frequency of the
master clock would be 256 × 48 kHz = 12.288 MHz. If the
AD1836A is then switched to 96 kHz operation (via writing to
the SPI port), the frequency of the master clock should remain
at 12.288 MHz (which is now 128 × fS).
•
Single-ended MUX/PGA mode. In this mode, two single-
ended stereo inputs are provided that can be selected using
the SPI port. Input gain can be programmed from 0 dB to
12 dB in steps of 3 dB. External capacitors are used to
supply filtering for the switched capacitor inputs.
Peak level information for each ADC may be read from the SPI
port through Registers 12 to 15. The data is supplied as a 10-bit
word with a maximum range of 0 dB to –60 dB and a resolution
of 1 dB. The registers hold peak information until read; after
reading, the registers are reset so that new peak information can
be acquired. Refer to the register descriptions for the details on
this format.
The internal clock used in the AD1836A is 512 × fS (48 kHz
mode) or 256 × fS (96 kHz mode). A clock doubler is used to
generate this internal master clock from the external clock in
the 256 × fS and 768 × fS modes.
To maintain the highest performance possible, it is recom-
mended that the clock jitter of the master clock signal be
limited to less than 300 ps rms, measured using the edge-to-
edge technique. Even at these levels, extra noise or tones may
appear in the DAC outputs if the jitter spectrum contains large
spectral peaks. It is highly recommended that an independent
crystal oscillator generate the master clock. In addition, it is
especially important that the clock signal should not be passed
A digital high-pass filter can be switched in line with the ADCs
under SPI control to remove residual dc offsets. It has a 1.3 Hz,
6 dB per octave cutoff at a 44.1 kHz sample rate. The cutoff
frequency will scale directly with sample frequency. Note that it
does not remove these offsets from the peak level measurement.
Rev. 0 | Page 11 of 24
AD1836A
through an FPGA or other large digital chip before being
applied to the AD1836A. In most cases, this will induce clock
jitter due to the fact that the clock signal is sharing common
power and ground connections with other unrelated digital
output signals.
SERIAL CONTROL PORT
The AD1836A has an SPI compatible control port that permits
programming the internal control registers for the ADCs and
DACs and for reading the ADC signal level from the internal
peak detectors. The DAC output levels may be independently
programmed by means of an internal digital attenuator
adjustable in 1024 linear steps.
The six DAC channels use a common serial bit clock to clock in
the serial data and a common left-right framing clock. The four
ADC channels output a common serial bit clock and a left-right
framing clock. The clock signals are all synchronous with the
sample rate.
The SPI control port is a 4-wire serial control port. The format
is similar to the Motorola SPI format except the input data-word
is 16 bits wide. The maximum serial bit clock frequency is 8 MHz
and may be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 3 shows the format of the SPI signal.
RESET AND POWER-DOWN
Reset will power down the chip and set the control registers to
their default settings. After reset is de-asserted, an initialization
routine will run inside the AD1836A to clear all memories to
zero. This initialization lasts for approximately 4500 MCLKs.
All control registers are write-only. They cannot be read back.
The ADC peak registers are read-only. They are reset to zero each
time they are read and are updated at the next sample time.
The power-down bit in the DAC Control Register 1 and ADC
Control Register 1 will power down the respective digital
section. The analog circuitry does not power down. All other
register settings are retained.
Due to an anomaly in the SPI interface, when a write to a DAC
control register follows after a read or a write to an ADC
register, it may not be executed properly. Any such write should
be performed twice.
To avoid possible synchronization problems, if MCLK is 512 fS
or 768 fS, the clock rate should be set in ADC Control Register 3
within the first 3072 MCLK cycles after reset, or DLRCLK and
DBCLK should be withheld until after the internal initialization
completes (see above).
CLATCH
CCLK
CDATA
COUT
D15
D14
D0
D0
D9
D8
Figure 3. Format of SPI Signal
Rev. 0 | Page 12 of 24
AD1836A
POWER SUPPLY AND VOLTAGE REFERENCE
SERIAL DATA PORTS—DATA FORMAT
The AD1836A is designed for 5 V supplies. Separate power
supply pins are provided for the analog and digital sections.
These pins should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize noise
pickup. A bulk aluminum electrolytic capacitor of at least 22 µF
should also be provided on the same PC board as the codec. For
critical applications, improved performance will be obtained
with separate supplies for the analog and digital sections. If this
is not possible, it is recommended that the analog and digital
supplies be isolated by means of a ferrite bead in series with
each supply. It is important that the analog supply be as clean as
possible.
The ADC serial data output mode defaults to the popular I2S
format, where the data is delayed by 1 BCLK interval from the
edge of the LRCLK. By programming Bits 8 and 9 in ADC
Control Register 2, the serial mode can be changed to right
justified (RJ), left justified DSP (DSP), left justified (LJ), Packed
Mode 128, or Packed Mode 256. In the RJ mode, it is necessary
to set Bits 6 and 7 to define the width of the data-word.
The DAC serial data input mode defaults to I2S. By
programming Bits 5, 6, and 7 in DAC Control Register 1, the
mode can be changed to RJ, DSP, LJ, Packed Mode 128, or
Packed Mode 256. The word width defaults to 24 bits but
can be changed by programming Bits 3 and 4 in DAC Control
Register 1. The packed modes accept six channels of data at the
DSDATA1 input pin, which is routed independently to each of
the six internal DACs.
For ease in interfacing to various logic families, the digital
output drivers are supplied from the ODVDD pin. For CMOS
logic, this should be connected to the 5 V digital supply. For
3.3 V logic, it should be connected to the 3.3 V supply. For TTL
levels, it can be tied to either. All digital inputs are compatible
with TTL and CMOS levels.
A special “auxiliary mode” is provided to allow two external
stereo ADCs and one external stereo DAC to be interfaced with
the AD1836A to provide 8 in/8 out operation. In addition, this
mode supports glueless interface to a single SHARC DSP serial
port, allowing a SHARC DSP to access all eight channels of
analog I/O. In this special mode, many pins are redefined; see
Table 11 for a list of redefined pins. Two versions of this mode
are available. In the master mode, the AD1836A provides the
LRCLK and BCLK signals for the external ADCs and DAC. In
the slave mode, external ADC1 provides the LRCLK and BCLK
signals (which must be divided down properly from the
external master clock), and the AD1836A will sync to these
external clocks. In the absence of the external ADC clocks in
slave mode, the ALRCLK and ABCLK outputs of the AD1836A
(TDM frame sync and bit clock) will default to be the same as in
master mode. See
The internal voltage reference VREF is brought out on Pin 13
(FILTR) and should be bypassed as close as possible to the chip,
with a parallel combination of 10 µF and 100 nF. The reference
voltage may be used to bias external op amps to the common-
mode voltage of the input and output signal pins. The current
drawn should be limited to less than 50 µA. This source can be
connected directly to op amp inputs but should be buffered if it
is required to drive resistive networks.
The FILTD pin should be connected to an external grounded
capacitor. This pin is used to reduce the noise of the internal
DAC bias circuitry, thereby reducing the DAC output noise. In
some cases, this capacitor may be eliminated with little effect on
performance.
Figure 9 through Figure 11 for details of these modes. Figure 12
shows the internal signal flow diagram of the auxiliary mode.
The following figures show the serial mode formats.
Rev. 0 | Page 13 of 24
AD1836A
LRCLK
BCLK
LEFT CHANNEL
RIGHT CHANNEL
SDATA
MSB
LSB
MSB
LSB
LEFT JUSTIFIED MODE––16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
BCLK
RIGHT CHANNEL
LSB
I S MODE––16 BITS TO 24 BITS PER CHANNEL
MSB
LSB
MSB
SDATA
2
RIGHT CHANNEL
LEFT CHANNEL
LRCLK
BCLK
MSB
LSB
MSB
LSB
SDATA
RIGHT JUSTIFIED MODE––SELECT NUMBER OF BITS PER CHANNEL
LRCLK
BCLK
MSB
MSB
SDATA
LSB
LSB
DSP MODE––16 BITS TO 24 BITS PER CHANNEL
1/f
S
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT f EXCEPT FOR DSP MODE WHICH IS 2 × f
S
S
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE
Figure 4. Stereo Serial Modes
Rev. 0 | Page 14 of 24
AD1836A
LRCLK
BCLK
DATA
128 BCLKs
32 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
SLOT 4
RIGHT 0
RIGHT 1
LRCLK
BCLK
DATA
MSB
MSB–1
MSB–2
Figure 5. ADC Packed Mode 128
LRCLK
BCLK
DATA
256 BCLKs
32 BCLKs
SLOT 1 SLOT 2
LEFT 0 LEFT 1
SLOT 5 SLOT 6
RIGHT 0 RIGHT 1
SLOT 3 SLOT 4
SLOT 7 SLOT 8
LRCLK
BCLK
DATA
MSB
MSB–1
MSB–2
Figure 6. ADC Packed Mode 256
LRCLK
BCLK
DATA
128 BCLKs
20 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
SLOT 5
RIGHT 1
SLOT 6
RIGHT 0
RIGHT 2
LRCLK
BCLK
DATA
MSB
MSB–1
MSB–2
Figure 7. DAC Packed Mode 128
LRCLK
BCLK
DATA
256 BCLKs
32 BCLKs
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
SLOT 5
SLOT 6
RIGHT 0
RIGHT 1
RIGHT 2
LRCLK
BCLK
DATA
MSB
MSB–1
MSB–2
Figure 8. DAC Packed Mode 256
Rev. 0 | Page 15 of 24
AD1836A
FSTDM
BCLK
TDM
MSB TDM
MSB TDM
1ST
ASDATA1
8TH
CH
CH
TDM (OUT)
INTERNAL
ADC R0
INTERNAL
ADC R1
INTERNAL
INTERNAL
ADC L1
AUX_ADC R1
MSB TDM
AUX_ADC L0 AUX_ADC L1
AUX_ADC R0
ASDATA1
ADC L0
32
MSB TDM
1ST
8TH
DSDATA1
TDM (IN)
CH
CH
INTERNAL
DAC L1
INTERNAL
INTERNAL
AUX_DAC L0
DAC L2
INTERNAL
DAC R0
INTERNAL
DAC R1
INTERNAL
DAC R2
AUX_DAC R0
DSDATA1
DAC L0
32
AUX
2
LRCLK I S
RIGHT
LEFT
(FROM AUX ADC NO. 1)
AUX
2
BCLK I S
(FROM AUX ADC NO. 1)
2
2
AAUXDATA1 (IN)
I S––MSB RIGHT
I S––MSB LEFT
(FROM AUX ADC NO. 1)
AAUXDATA2 (IN)
2
2
I S––MSB RIGHT
I S––MSB LEFT
(FROM AUX ADC NO. 2)
DAUXDATA (OUT)
(TO AUX DAC)
2
2
I S––MSB LEFT
I S––MSB RIGHT
NOTE
AUX BCLK FREQUENCY IS 64 × FRAME RATE; TDM BCLK FREQUENCY IS 256 × FRAME RATE.
FSTDM FOLLOWS AUX LRCLK BY 3 1/2 ± 1/2 TDM BCLK IN BOTH MASTER AND SLAVE MODES.
Figure 9. AUX Mode Timing (Note that the Clocks Are Not to Scale)
Rev. 0 | Page 16 of 24
AD1836A
SHARC IS ALWAYS
SHARC
RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
30MHz
12.288MHz
LRCLK
BCLK
DATA
MCLK
ASDATA1 ALRCLK ABCLK DSDATA1
ADC NO. 1
SLAVE
LRCLK
BCLK
DATA
MCLK
DBCLK/AUXBCLK (64f )
S
DAC
ASDATA2/DAUXDATA
LRCLK
BCLK
DATA
MCLK
DLRCLK/AUXLRCLK
DSDATA2/AAUXDATA1
DSDATA3/AAUXDATA2
MCLK
ADC NO. 2
SLAVE
AD1836A
MASTER
Figure 10. AUX Mode Connection to SHARC (Master Mode)
SHARC IS ALWAYS
SHARC
RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
30MHz
12.288MHz
LRCLK
BCLK
DATA
MCLK
ASDATA1 ALRCLK ABCLK DSDATA1
ADC NO. 1
MASTER
LRCLK
BCLK
DATA
MCLK
DBCLK/AUXBCLK (64f )
S
DAC
ASDATA2/DAUXDATA
LRCLK
BCLK
DATA
MCLK
DLRCLK/AUXLRCLK
DSDATA2/AAUXDATA1
DSDATA3/AAUXDATA2
MCLK
ADC NO. 2
SLAVE
AD1836A
SLAVE
Figure 11. AUX Mode Connection to SHARC (Slave Mode)
Rev. 0 | Page 17 of 24
AD1836A
Table 11. Pin Function Changes in AUX Mode
Pin Name (I2S/AUX Mode)
ASDATA1(O)
ASDATA2(O)/DAUXDATA(O)
DSDATA1(I)
DSDATA2(I)/AAUXDATA(I)
DSDATA3(I)/AAUXDATA2(I)
ALRCLK(O)
I2S Mode
AUX Mode
I2S Data Out, Internal ADC1
I2S Data Out, Internal ADC2
I2S Data In, Internal DAC1
I2S Data In, Internal DAC2
I2S Data In, Internal DAC3
LRCLK for Internal ADC1, ADC2
BCLK for Internal ADC1, ADC2
LRCLK In/Out Internal DACs
TDM Data Out, to SHARC
AUX—I2S Data Out (to External DAC)
TDM Data In, from SHARC
AUX—I2S Data In 1 (to External ADC)
AUX—I2S Data In 2 (to External ADC)
TDM Frame Sync Out, to SHARC
TDM BCKL Out, to SHARC
AUX LRCLK In/Out, Driven by External IRCLK from ADC (in slave mode).
In master mode, driven by internal MCLK/512.
ABCLK(O)
DLRCLK(I)/AUXLRCLK(I/O)
DBCLK(I)/AUXBCLK(I/O)
BCLK In/Out Internal DACs
AUX BCLK In/Out, Driven by External BCLK from ADC (in slave mode).
In master mode, driven by internal MCLK/8.
SYNC SIGNAL DERIVED FROM AUXLRCLK USED TO
ADC
RESET INTERNAL ADC COUNTER
SYNC
LRCLK
ALRCLK
ABCLK
AUXBCLK
AUXLRCLK
AUXDATA2
AUXDATA1
ABCLK
2
I S
SPORT
DECODE
ASDATA1
ASDATA1
DATA TO SHARC
4 ADCS
ASDATA1
MCLK
2
I S
ASDATA2/DAUXDATA
DATA TO EXT DAC
MUX
TIMING GEN
LRCLK BCLK
BCLK AND LRCLK FOR
EXT DAC COMES FROM
ADC BCLK, LRCLK.
AUXDATA
2
MUST BE IN I S MODE.
2
I S FORMATTER
FROM SHARC
FROM EXT A/D DSDATA2/AUXDATA1
FROM EXT A/D DSDATA3/AUXDATA2
DSDATA1
DSDATA1
DSDATA2
DSDATA3
2 AUX
AUXLRCLK AUXBCLK
CHANNELS
MUX
MUX
LRCLK
BCLK
DLRCLK/AUXLRCLK
DBCLK/AUXBCLK
6-CH
DAC
SPORT
6 MAIN
CHANNELS
DAC
MASTER/SLAVE MODE,
FROM ADC SPI PORT
INDICATES MUX POSITION FOR AUX-TDM MODE
Figure 12. Extended TDM Mode (Internal Flow Diagram)
Rev. 0 | Page 18 of 24
AD1836A
SPI CONTROL REGISTERS
Note that all control registers default to zero at power-up.
Table 12. Serial SPI Word Format
Register Address
15:12
Read/Write
11
Reserved
Data Field
9:0
10
4 Bits
1 = Read
0 = Write
0
10 Bits
Table 13. Register Addresses and Functions
Register Address
RD/WR
Reserved
Function
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bits 9:0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DAC Control 1
DAC Control 2
DAC1L Volume
DAC1R Volume
DAC2L Volume
DAC2R Volume
DAC3L Volume
DAC3R Volume
ADC1L—Peak Level (Read-Only)
ADC1R—Peak Level (Read-Only)
ADC2L—Peak Level (Read-Only)
ADC2R—Peak Level (Read-Only)
ADC Control 1
ADC Control 2
ADC Control 3
Reserved
Table 14. DAC Control Register 1
Packed Mode: Eight channels are“packed” in DSDATA1 serial input. Packed Mode 128: Refer to Figure 7. Packed Mode 256: Refer to Figure 8.
Address
RD/WR Reserved Function
De-emphasis Serial Mode
Data-Word
Width
Power-Down Interpolator
Mode
Reserved
15, 14, 13, 12
11
10
9, 8
7, 6, 5
4, 3
2
1
0
0000
0
0
00 = None
01 = 44.1 kHz
10 = 32.0 kHz 010 = DSP
11 = 48.0 kHz 011 = LJ
000 = I2S
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = Normal
1 = PWRDWN
0 = 8× (48 kHz)
1 = 4× (96 kHz)
0
001 = RJ
100 = Packed Mode 256
101 = Packed Mode 128
110 = Reserved
111 = Reserved
Rev. 0 | Page 19 of 24
AD1836A
Table 15. DAC Control Register 2
DAC Mute
DAC3R
5
Address
RD/WR
Reserved
DAC3L
4
DAC2R
3
DAC2L
2
DAC1R
1
DAC1L
0
15, 14, 13, 12
11
10, 9, 8, 7, 6
0001
0
00000
0 = On
1 = Mute
0 = On
1 = Mute
0 = On
1 = Mute
0 = On
1 = Mute
0 = On
1 = Mute
0 = On
1 = Mute
Table 16. DAC Volume Registers
Function
Address
RD/WR
Reserved
Volume
9:0
15, 14, 13, 12
0010: DAC1L
0011: DAC1R
0100: DAC2L
0101: DAC2R
0110: DAC3L
0111: DAC3R
11
10
0
0
0 to 1023 in 1024 Linear Steps
Table 17. ADC Control Register 1
Function
Address
RD/WR
Reserved
Filter
Power-Down
7
Sample Rate
6
Left Gain
Right Gain
15, 14, 13, 12
11
10, 9
8
5, 4, 3
2, 1, 0
1100
0
00
0 = DC
1 = High Pass
0 = Normal
1 = PWRDWN
0 = 48 kHz
1 = 96 kHz
000 = 0 dB
001 = 3 dB
010 = 6 dB
011 = 9 dB
100 = 12 dB
101 = Reserved
110 = Reserved
111 = Reserved
000 = 0 dB
001 = 3 dB
010 = 6 dB
011 = 9 dB
100 = 12 dB
101 = Reserved
110 = Reserved
111 = Reserved
Table 18. ADC Control Register 2
Packed Mode: Eight channels are“packed” in ASDATA1 serial output. Packed Mode 128: Refer to Figure 5. Packed Mode 256: Refer to Figure 6.
Packed Mode AUX: Refer to Figure 9 to Figure 11. Note that Packed AUX mode affects the entire chip, including the DAC serial mode.
Master/Slave
RD/WR Reserved AUX Mode
ADC Mute
ADC2R
3
Address
SOUT Mode
Word Width
ADC2L
2
ADC1R
1
ADC1L
0
15, 14, 13, 12
11
10
9
8, 7, 6
000 = I2S
001 = RJ
010 = DSP
5, 4
1101
0
0
0 = Slave
1 = Master
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = On
0 = On
0 = On
0 = On
1 = Mute 1 = Mute 1 = Mute 1 = Mute
011 = LJ
100 = Packed Mode 256
101 = Packed Mode 128
110 = Packed Mode AUX
Rev. 0 | Page 20 of 24
AD1836A
Table 19. ADC Control Register 3
When changing clock mode, other SPI bits that are written during the same SPI transaction may be lost. Therefore, it is recommended
that these be set separately.
Function
Right
Left
Right
Right
Left Differential Differential
MUX/PGA
Enable
Left MUX MUX/PGA
I/P Select Enable
MUX I/P
Select
Address RD/WR Reserved Clock Mode
I/P Select
I/P Select
15, 14,
13, 12
11
10, 9, 8
7, 6
5
4
3
2
1
0
1110
0
000
00 = 256 × fS
01 = 512 × fS
10 = 768 × fS
0 = Differential
PGA Mode
1 = PGA/MUX
Mode (Single-
Ended Input)
0 = Differential 0 = Direct
PGA Mode
1 = PGA/MUX
Mode (Single-
Ended Input)
0 = I/P 0
1 = MUX/PGA 1 = I/P 1
0 = Direct
1 = MUX/PGA
0 = I/P 0
1 = I/P 1
Table 20. ADC Peak Level Data Registers
Peak Level Data (10 Bits)
6 Data Bits
Address
RD/WR
Reserved
4 Fixed Bits
3:0
15, 14, 13, 12
1000 = ADC1L
1001 = ADC1R
1010 = ADC2L
1011 = ADC2R
11
10
9:4
1
0
000000 = 0.0 dBFS
000001 = –1.0 dBFS
000010 = –2.0 dBFS
000011 = –3.0 dBFS
0000
The 4 LSBs are always zero.
111100 = –60 dBFS Min
Rev. 0 | Page 21 of 24
AD1836A
AD1836A
CAP1L
C1
1nF
GAIN SELECT
POWER-DOWN
–
+
250Ω
LEFT
V
V
REF
INPUT NO. 1
ADC2L
LEFT
INPUT NO. 2
250Ω
–
+
REF
PGA
CAP2L
C2
1nF
INPUT SELECT
NOTE
ADC2 SINGLE-ENDED MUX PGA INPUT MODE––LEFT CHANNEL ONLY SHOWN.
CONTROL REGISTER 3 CONTENTS: 6 LSBs: SELECT INPUT NO. 1: 11 1010
SELECT INPUT NO. 2: 11 1111
Figure 13. Single-Ended MUX/PGA Mode
AD1836A
CAP1L
C1
1nF
LEFT + VE
–
+
250Ω
250Ω
INPUT
V
ADC2L
REF
+
–
LEFT – VE
INPUT
GAIN SELECT
POWER-DOWN
PGA
CAP2L
C2
1nF
NOTE
ADC2 DIFFERENTIAL PGA INPUT MODE—LEFT CHANNEL ONLY SHOWN.
CONTROL REGISTER 3 CONTENTS: 6 LSBs: 00 1010
Figure 14. Differential PGA Mode
Rev. 0 | Page 22 of 24
AD1836A
OUTLINE DIMENSIONS
13.45
13.20 SQ
12.95
1.03
0.88
0.73
2.45
MAX
39
27
40
26
SEATING
PLANE
10.20
7.80
REF
TOP VIEW
10.00 SQ
9.80
(PINS DOWN)
VIEW A
PIN 1
52
14
1
13
0.23
0.11
0.65 BSC
0.40
0.22
2.20
7°
2.00
1.80
0°
0.13 MIN
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS M-022-AC
Figure 15. 52-Lead Plastic Quad Flat Package [MQFP]
(S-52A)
Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ORDERING GUIDE
AD1836A Products
AD1836AAS
AD1836AASRL
AD1836ACS
Temperature Package
–40°C to +85°C Ambient
–40°C to +85°C Ambient
–40°C to +85°C Ambient
–40°C to +85°C Ambient
Package Description
52-Lead MQFP
52-Lead MQFP
52-Lead MQFP
52-Lead MQFP
Package Option
S-52A
S-52A on 13" Reels
S-52A
AD1836ACSRL
EVAL-AD1836AEB
S-52A on 13" Reels
Evaluation Board
Rev. 0 | Page 23 of 24
AD1836A
NOTES
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03800–0–8/03(0)
Rev. 0 | Page 24 of 24
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