EVAL-AD1833EB [ADI]
Multichannel 24-Bit, 192 kHz, DAC; 多通道24位192 kHz时， DAC
| 型号： | EVAL-AD1833EB |
| 厂家： | 
ADI |
| 描述： | Multichannel 24-Bit, 192 kHz, DAC |
| 文件： | 总20页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multichannel,
24-Bit, 192 kHz, ⌺-⌬ DAC
a
AD1833
FUNCTIONAL BLOCK DIAGRAM
FEATURES
5 V Stereo Audio System with 3.3 V Tolerant Digital
Interface
ZERO FLAGS
AVDD
DVDD1 DVDD2
Supports 96 kHz Sample Rates on Six Channels and
192 kHz on 2 Channels
OUTLP1
OUTLN1
CDATA
CLATCH
CCLK
INTERPOLATOR
DAC
DAC
DAC
DAC
SPI
Supports 16-/20-/24-Bit Word Lengths
Multibit Sigma-Delta Modulators with
“Perfect Differential Linearity Restoration” for
Reduced Idle Tones and Noise Floor
Data Directed Scrambling DACs—Least Sensitive to
Jitter
Differential Output for Optimum Performance
DACs Signal-to-Noise and Dynamic Range: 110 dB
–94 dB THD + N—6-Channel Mode
–95 dB THD + N—2-Channel Mode
On-Chip Volume Control Per Channel with 1024-Step
Linear Scale
PORT
OUTLP2
OUTLN2
INTERPOLATOR
MCLK
OUTLP3
OUTLN3
INTERPOLATOR
INTERPOLATOR
INTERPOLATOR
INTERPOLATOR
RESET
FILTER
ENGINE
OUTRP3
OUTRN3
L/RCLK
BCLK
SDIN1
SDIN2
SDIN3
SOUT
OUTRP2
OUTRN2
DATA
PORT
DAC
DAC
OUTRP1
OUTRN1
AD1833
Software Controllable Clickless Mute
Digital De-Emphasis Processing
FILTR FILTD
DGND
AGND
Supports 256
؋
fS, 512؋
fS, and 768؋
fS Master Clock Modes
Power-Down Mode Plus Soft Power-Down Mode
Flexible Serial Data Port with Right-Justified, Left-
Justified, I2S-Compatible and DSP Serial Port Modes
Supports Packed Data Mode (TDM) for DACs
48-Lead LQFP Plastic Package
The AD1833 is fully compatible with all known DVD formats,
catering for up to 24-bit word lengths at sample rates of 48 kHz
and 96 kHz on all six channels while supporting a 192 kHz
sample rate on two channels. It also provides the “Redbook”
standard 50 µs/15 µs digital de-emphasis filters at sample rates
of 32 kHz, 44.1 kHz, and 48 kHz.
APPLICATIONS
DVD Video and Audio Players
Home Theatre Systems
Automotive Audio Systems
Set-Top Boxes
The AD1833 has a very flexible serial data input port that allows
for glueless interconnection to a variety of ADCs, DSP chips,
AES/EBU receivers, and sample rate converters. The AD1833
can be configured in left-justified, I2S, right-justified, or DSP
serial port compatible modes. The AD1833 accepts serial audio
data in MSB first, two’s complement format. While the AD1833
can be operated from a single 5 V power supply, it also features
a separate supply pin for its digital interface which allows the
device to be interfaced to devices using 3.3 V power supplies.
Digital Audio Effects Processors
GENERAL DESCRIPTION
The AD1833 is a complete, high-performance, single-chip, multi-
channel, digital audio playback system. It features six audio
playback channels each comprising a high-performance digital
interpolation filter, a multibit sigma-delta modulator featuring
Analog Devices patented technology and a continuous-time
voltage-out analog DAC section. Other features include an on-chip
clickless attenuator and mute capability, per channel, programmed
through an SPI-compatible serial control port.
It is fabricated on a single monolithic integrated circuit and is
housed in a 48-lead LQFP package for operation over the tem-
perature range –40°C to +85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
AD1833–SPECIFICATIONS
TEST CONDITIONS UNLESS OTHERWISE NOTED
Supply Voltages (AVDD, DVDD
Ambient Temperature
Input Clock
)
5.0 V
25°C
12.288 MHz, (256 × fS Mode)
Input Signal
Nominally 1 kHz, 0 dBFS (Full Scale)
Input Sample Rate
Measurement Bandwidth
Word Width
48 kHz
20 Hz to 20 kHz
24 Bits
Load Capacitance
Load Impedance
500 pF
10 kΩ
NOTES
Performance of all channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications).
Specifications subject to change without notice.
Parameter
Min
Typ
Max
Unit
Test Conditions
ANALOG PERFORMANCE
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range (20 Hz to 20 kHz, –60 dBFS Input)
With A-Weighted Filter
106.5
110
110.5
–95
–94
–95
–94
110
108
dB
dB
dB
dB
dB
dB
dB
dB
fS = 96 kHz
Two Channels Active
Six Channels Active
96 kHz, Two Channels Active
96 kHz, Six Channels Active
Total Harmonic Distortion + Noise
–89
SNR
Interchannel Isolation
DC Accuracy
Gain Error
Interchannel Gain Mismatch
Gain Drift
Interchannel Crosstalk (EIAJ Method)
Interchannel Phase Deviation
Volume Control Step Size (1023 Linear Steps)
Volume Control Range (Max Attenuation)
Mute Attenuation
3.0
0.2
80
–120
0.1
0.098
63.5
–120
0.1
%
%
ppm/°C
dB
Degrees
%
dB
dB
De-Emphasis Gain Error
dB
Full-Scale Output Voltage at Each Pin (Single-Ended)
Output Resistance Measured Differentially
Common-Mode Output Volts
1.0 (2.8)
150
2.2
V rms (V p-p)
Ω
V
DAC INTERPOLATION FILTER—48 kHz
Pass Band
Pass Band Ripple
Stop Band
Stop Band Attenuation
Group Delay
20
kHz
dB
kHz
dB
0.01
510
24
70
µs
DAC INTERPOLATION FILTER—96 kHz
Pass Band
Pass Band Ripple
Stop Band
Stop Band Attenuation
Group Delay
37.7
89.954
kHz
dB
kHz
dB
0.03
160
55.034
70
µs
DAC INTERPOLATION FILTER—192 kHz
Pass Band
Pass Band Ripple
kHz
dB
1
Stop Band
Stop Band Attenuation
Group Delay
104.85
70
kHz
dB
µs
140
–2–
REV. 0
AD1833
Parameter
Min
Typ
Max
Unit
Test Conditions
DIGITAL I/O
Input Voltage HI
Input Voltage LO
Output Voltage HI
Output Voltage LO
3.0
V
V
V
V
0.8
0.4
DVDD2 – 0.4
POWER SUPPLIES
Supply Voltage (AVDD and DVDD1
)
4.5
3.3
5.0
5.5
DVDD1
42
V
V
mA
mA
mA
Supply Voltage (DVDD2
)
Supply Current IANALOG
Supply Current IDIGITAL
38.5
42
2
45.5
Active
Power-Down
Power Supply Rejection Ratio
1 kHz 300 mV p-p Signal at Analog Supply Pins
20 kHz 300 mV p-p Signal at Analog Supply Pins
–60
–50
dB
dB
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
LQFP, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 91°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
AVDD, DVDDx to AGND, DGND . . . . . . . . –0.3 V to +6.5 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD2 + 0.3 V
Analog I/O Voltage to AGND . . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
ORDERING GUIDE
Package Description
Model
Temperature Range
Package Option
AD1833AST
EVAL-AD1833EB
–40°C to +85°C
Thin Plastic Quad Flatpack
Evaluation Board
ST-48
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
1
2
OUTLP1
OUTLN1
AVDD
36
35
34
33
32
31
30
29
28
27
26
25
OUTRP1
OUTRN1
AVDD
PIN 1
IDENTIFIER
3
4
AVDD
AVDD
5
AGND
AGND
AGND
AGND
DGND
DVDD2
AD1833
TOP VIEW
(Not to Scale)
6
AGND
7
AGND
8
DGND
9
DVDD1
ZEROA
ZERO3R
ZERO3L
10
11
12
RESET
ZERO1L
ZERO1R
13 14 15 16 17 18 19 20 21 22 23 24
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD1833 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–3–
REV. 0
AD1833
DIGITAL TIMING (Guaranteed over –40؇C to +85؇C, AVDD = DVDD = 5.0 V ؎ 10%)
Min
Unit
tDML
tDMH
tDBH
tDBL
tDLS
tDLH
tDDS
tDDH
tPDRP
tCCH
tCCL
tCSU
tCHD
tCLH
MCLK LO Pulsewidth (All Modes)
MCLK HI Pulsewidth (All Modes)
BCLK HI Pulsewidth
BCLK LO Pulsewidth
LRCLK Setup
LRCLK Hold (DSP Serial Port Mode Only)
SDATA Setup
SDATA Hold
PD/RST LO Pulsewidth
CCLK HI Pulsewidth
CCLK LO Pulsewidth
CDATA Setup Time
CDATA Hold Time
CLATCH HI Pulsewidth
15
15
15
15
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
5
15
10
10
10
5
10
10
Specifications subject to change without notice.
tDMH
MCLK INPUT
RESET INPUT
tDML
tPDRP
Figure 1. MCLK and RESET Timing
tDBH
BCLK
tDBL
tDLS
L/RCLK
tDDS
SDATA
LEFT-JUSTIFIED
MSB
tDDH
MSB-1
MODE
tDDS
MSB
tDDH
SDATA
I S-JUSTIFIED
MODE
2
tDDS
tDDS
SDATA
RIGHT-JUSTIFIED
MODE
LSB
tDDH
MSB
tDDH
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Serial Data Port Timing
–4–
REV. 0
AD1833
tCHD
CDATA
CCLK
D15
D14
D0
tCCH
tCSU
tCCL
CLATCH
tCLH
Figure 3. SPI Timing
PIN FUNCTION DESCRIPTIONS
Pin
Mnemonic
IN/OUT
Description
1
2
OUTLP1
OUTLN1
AVDD
O
O
DAC 1 Left Channel Positive Output.
DAC 1 Left Channel Negative Output.
Analog Supply.
3, 4, 33, 34, 44
5, 6, 7, 30, 31, 32, 41
AGND
Analog Ground.
8, 29
9
DGND
Digital Ground.
Digital Supply to Core Logic.
Flag to Indicate Zero Input on All Channels.
Flag to Indicate Zero Input on Channel 3 Right.
Flag to Indicate Zero Input on Channel 3 Left.
Flag to Indicate Zero Input on Channel 2 Right.
Latch Input for Control Data (SPI Port).
Serial Control Data Input (SPI Port).
DVDD1
ZEROA
ZERO3R
ZERO3L
ZERO2R
CLATCH
CDATA
CCLK
10
11
12
13
14
15
16
17
18
19
20
O
O
O
O
I
I
I
I/O
I/O
I
Clock Input for Control Data (SPI Port).
L/RCLK
BCLK
MCLK
Left/Right Clock for DAC Data Input (FSTDM Output in TDM Mode).
Bit Clock for DAC Data Input (BCLKTDM Output in TDM Mode).
Master Clock Input.
Data Input for Channel 1 Left/Right (Data Stream Input in TDM
and Packed Modes).
SDIN1
I
21
22
SDIN2
SDIN3
I/O
I/O
Data Input for Channel 2 Left/Right (L/RCLK Output to Auxiliary
DAC in TDM Mode).
Data Input for Channel 3 Left/Right (BCLK Output to Auxiliary
DAC in TDM Mode).
23
24
25
26
27
28
35
36
37
38
39
40
42
SOUT
O
O
O
O
I
Auxiliary I2S Output (Available in TDM Mode).
Flag to Indicate Zero Input on Channel 2 Left.
Flag to Indicate Zero Input on Channel 1 Right.
Flag to Indicate Zero Input on Channel 1 Left.
Power-Down and Reset Control.
Power Supply to External Interface Logic.
DAC 1 Right Channel Negative Output.
DAC 1 Right Channel Positive Output.
DAC 2 Right Channel Negative Output.
DAC 2 Right Channel Positive Output.
DAC 3 Right Channel Negative Output.
DAC 3 Right Channel Positive Output.
ZERO2L
ZERO1R
ZERO1L
RESET
DVDD2
OUTRN1
OUTRP1
OUTRN2
OUTRP2
OUTRN3
OUTRP3
FILTR
O
O
O
O
O
O
Reference/Filter Capacitor Connection. Recommend 10 µF/100 µF
Decouple to Analog Ground.
43
FILTD
Filter Capacitor Connection. Recommend 10 µF/100 µF Decouple to
Analog Ground.
45
46
47
48
OUTLP3
OUTLN3
OUTLP2
OUTLN2
O
O
O
O
DAC 3 Left Channel Positive Output.
DAC 3 Left Channel Negative Output.
DAC 2 Left Channel Positive Output.
DAC 2 Left Channel Negative Output.
REV. 0
–5–
AD1833–Typical Performance Characteristics
0.01
0.008
0.006
0.004
0.002
0
0.1
0.08
0.06
0.04
0.02
0
–0.002
–0.004
–0.006
–0.008
–0.01
–0.02
–0.04
–0.06
–0.08
–0.1
0
0.2
0.4
0.6
0.8
1.0
Hz
1.2
1.4
1.6
1.8
2.0
4
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4
؋
10 Hz
؋
10 TPC 1. Pass Band Response, 8× Mode
TPC 4. Pass Band Response, 4× Mode
0.5
10
0
0.4
0.3
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
0.5
1.0
1.5
2.0
Hz
2.5
3.0
3.5
4.0
4
2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50
4
؋
10 Hz
؋
10 TPC 2. Transition Band Response, 8× Mode
TPC 5. 40 kHz Pass Band Response, 4× Mode
10
0
0
–20
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40
–60
–80
–100
–120
–140
–160
0
0.5
1.0
1.5
Hz
2.0
2.5
3.0
؋
10 4.0
4.2
4.4
4.6
4.8
5.0
Hz
5.2
5.4
5.6
5.8
6.0
4
5
؋
10 TPC 3. Complete Response, 8× Mode
TPC 6. Transition Band Response, 4× Mode
–6–
REV. 0
AD1833
10
0
0
–20
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40
–60
–80
–100
–120
–140
–160
0
0.5
1.0
1.5
Hz
2.0
2.5
3.0
5
0.80
0.85
0.90
0.95
1.00
Hz
1.05
1.10
1.15
1.20
5
؋
10 ؋
10 TPC 7. Complete Response, 4× Mode
TPC 9. Transition Band Response, 2× Mode
2.0
1.5
0
–20
1.0
–40
0.5
–60
0
–80
–0.5
–1.0
–1.5
–2.0
–100
–120
–140
–160
0
0.5
1.0
1.5
2.0
0
1
2
3
4
5
6
7
8
5
4
Hz
؋
10 Hz
؋
10 TPC 8. 80 kHz Pass Band Response, 2× Mode
TPC 10. Complete Response, 2× Mode
REV. 0
–7–
AD1833
The modulator samples the output of the interpolator stage(s) at
a rate of 6.144 MHz.
FUNCTIONAL DESCRIPTION
Device Architecture
The AD1833 is a 6-channel audio DAC featuring multibit
Sigma-Delta (Σ-∆) technology. The AD1833 features three
stereo converters (giving six channels) where each stereo channel
is controlled by a common bit-clock (BCLK) and synchroniza-
tion signal (L/RCLK).
OPERATING FEATURES
SPI Register Definitions
The SPI port allows flexible control of the devices’ program-
mable functions. It is organized around nine registers; six
individual channel VOLUME registers and three CONTROL
registers. Each WRITE operation to the AD1833 SPI control
port requires 16 bits of serial data in MSB-first format. The four
most significant bits are used to select one of nine registers (seven
register addresses are reserved), and the bottom 10 bits are then
written to that register. This allows a write to one of the nine
registers in a single 16-bit transaction. The SPI CCLK signal is
used to clock in the data. The incoming data should change on
the falling edge of this signal and remain valid during the rising
edge. At the end of the 16 CCLK periods, the CLATCH signal
should rise to latch the data internally into the AD1833. See
Figure 2.
Interpolator
The interpolator consists of up to three stages of sample rate
doubling and half-band filtering followed by a 16 sample zero
order hold. The sample rate doubling is achieved by zero stuff-
ing the input samples, and a digital half band filter is then used
to remove any images above the band of interest and to bring
the zero samples to their correct values.
By selecting different input sample rates, one, two, or all three
stages of doubling may be switched in. This allows for three
different sample rate inputs. All three doubling stages are used
with the 48 kHz input sample rate, with the 96 kHz input sample
rate only two doubling stages are used, and with the 192 kHz
input sample rate only one doubling stage is used. In each case
the input sample frequency is increased to 384 kHz. The Zero-
Order Hold (ZOH) holds the interpolator samples for upsampling
by the modulator. This is done at a rate 16 times the interpola-
tor output sample rate.
The serial interface format used on the Control Port utilizes a
16-bit serial word as shown in Table I. The 16-bit word is divided
into several fields: Bits 15–12 define the register address,
Bits 11 and 10 are reserved and must be programmed to 0,
and Bits 9–0 are the data field (which has specific definitions,
depending on the register selected).
Modulator
The modulator is a 6-bit, second-order implementation and
uses data scrambling techniques to achieve perfect linearity.
Table I. Control Port Map
Register Address
14 13
Reserved1
11 10
Data Field
152
12
9
8
7
6
5
4
3
2
1
0
NOTES
1Must be programmed to zero.
2Bit 15 = MSB
Bit 15 Bit 14 Bit 13
Bit 12
Register Function
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC Control I
DAC Control II
DAC Volume 1
DAC Volume 2
DAC Volume 3
DAC Volume 4
DAC Volume 5
DAC Volume 6
DAC Control III
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
–8–
REV. 0
AD1833
Table II. DAC Control I
Function
Data Word
Width
Power-Down
RESET
Interpolator
Mode
Address
15–12
Reserved*
De-Emphasis
9–8
Serial Mode
11
10
7–5
4–3
2
1–0
0000
0
0
00 = None
000 = I2S
001 = RJ
010 = DSP
011 = LJ
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = Reserved
0 = Normal
1 = PWRDWN 01 = 2× (192 kHz)
00 = 8× (48 kHz)
01 = 44.1 kHz
10 = 32.0 kHz
11 = 48.0 kHz
10 = 4× (96 kHz)
11 = Reserved
100 = Pack Mode 1 (256)
101 = Pack Mode 2 (128)
110 = AUX Mode
111 = Reserved
*Must be programmed to zero.
DAC CONTROL REGISTER I
DAC Word Width
De-Emphasis
The AD1833 will accept input data in three separate word-
lengths—16, 20, and 24 bits. The word-length may be selected
by writing to Control Bits 4 and 3 in DAC Control Register I,
see Table V.
The AD1833 has a built-in de-emphasis filter that can be used
to decode CDs that have been encoded with the standard
“Redbook” 50 µs/15 µs emphasis response curve. Three curves
are available; one each for 32 kHz, 44.1 kHz, and 48 kHz sam-
pling rates. The filters may be selected by writing to Control
Bits 9 and 8 in DAC Control Register I, see Table III.
Table V. Word Length Settings
Bit 4
Bit 3
Word Length
Table III. De-Emphasis Settings
0
0
1
1
0
1
0
1
24 Bits
20 Bits
16 Bits
Reserved
Bit 9
Bit 8
De-Emphasis
0
0
1
1
0
1
0
1
Disabled
44.1 kHz
32 kHz
Power-Down Control
The AD1833 can be powered down by writing to Control Bit 2
in DAC Control Register I, see Table VI. The power-down/
reset bit is not latched when the CLATCH is brought high to
latch the entire word, but only after the following low-to-high
CLATCH transition. Therefore, to put the part in power-down,
or to bring it back up from power-down, the command should
be written twice.
48 kHz
Data Serial Interface Mode
The AD1833’s serial data interface is designed to accept data in
a wide range of popular formats including I2S, right justified
(RJ), left justified (LJ) and flexible DSP modes. The L/RCLK
pin acts as the word clock (or Frame Sync) to indicate sample
interval boundaries. The BCLK defines the serial data rate
while the data is input on the SDIN1-3 pins. The serial mode
settings may be selected by writing to Control Bits 7 through 5
in DAC Control Register I, see Table IV.
Table VI. Power-Down Control
Bit 2
Power-Down Setting
0
1
Normal Operation
Power-Down Mode
Table IV. Data Serial Interface Mode Settings
Bit 7
Bit 6
Bit 5
Serial Mode
I2S
Interpolator Mode
The AD1833’s DAC interpolators can be operated in one of
three modes—8×, 4×, or 2× corresponding with 48 kHz, 96 kHz,
and 192 kHz modes respectively. The Interpolator Mode may
be selected by writing to Control Bits 1 and 0 in DAC Control
Register I, see Table VII.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Right Justify
DSP
Left Justify
Packed Mode 1 (256)
Packed Mode 2 (128)
AUX Mode
Reserved
Table VII. Interpolator Mode Settings
Bit 1
Bit 0
Interpolator Mode
0
0
1
1
0
1
0
1
8× (48 kHz)
2× (192 kHz)
4× (96 kHz)
Reserved
REV. 0
–9–
AD1833
Table VIII. DAC Control II
Function
Mute Control
Address
15–12
Reserved*
Reserved*
11
10
9–6
5
4
3
2
1
0
0001
0
0
0
Channel 6
Channel 5
Channel 4
Channel 3
Channel 2
Channel 1
0 = Mute Off
1 = Mute On
0 = Mute Off 0 = Mute Off 0 = Mute Off
1 = Mute On 1 = Mute On 1 = Mute On
0 = Mute Off 0 = Mute Off
1 = Mute On 1 = Mute On
*Must be programmed to zero.
DAC CONTROL REGISTER III
Stereo Replicate
DAC CONTROL REGISTER II
DAC Control Register II contains individual channel mute
controls for each of the 6 DACs. Default operation (bit = 0) is
muting off. Bits 9 through 6 of Control Register II are reserved
and should be programmed to zero, see Table VIII.
The AD1833 allows the stereo information on Channel 1
(SDIN1—Left 1 and Right 1) to be copied to Channels 2 and 3
(Left/Right 2 and Left/Right 3). These signals can be used in an
external summing amplifier to increase potential signal SNR.
Stereo Replicate mode can be enabled by writing to Control
Bit 5, see Table XI. Note that replication is not reflected in
the zero flag status.
Table IX. Muting Control
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Muting
X
X
X
X
X
1
X
X
X
X
1
X
X
X
1
X
X
X
X
1
X
X
X
X
1
X
X
X
X
1
Mute Channel 1
Mute Channel 2
Mute Channel 3
Mute Channel 4
Mute Channel 5
Mute Channel 6
Table XI. Stereo Replicate
X
X
X
X
X
Bit 5
Stereo Mode
0
1
Normal
Channel 1 Data Replicated on Channels 2 and 3
X
Table X. DAC Control III
Stereo Replicate
Function
Address
15–12
Reserved*
Reserved
*
(192 kHz)
MCLK Select
Zero Detect
2
Reserved
1–0
11
10
9–6
5
4–3
1000
0
0
0
0 = Normal
1 = Replicate
00 = 256 × fS (MCLK × 2)
01 = 512 × fS (MCLK
Straight Through)
0 = Active High
1 = Active Low
10 = 768 × fS (MCLK × 2/3)
*Must be programmed to zero.
–10–
REV. 0
AD1833
is programmable by writing to Control Bit 2, see Table XIII.
The six individual channel flags are best used as three stereo
zero flags by combining pairs of them through suitable logic
gates. Then, when both the left and right input are zero for 1024
clock cycles, i.e., a stereo zero input for 1024 sample periods,
the combined result of the two individual flags will go active
indicating a stereo zero.
MCLK Select
The AD1833 allows the matching of available external MCLK
frequencies to the required sample rate. The oversampling rate
can be selected from 256 × fS, 512 × fS or 768 × fS by writing to
Bit 4 and Bit 3. Internally the AD1833 requires an MCLK of
512 × fS; therefore, in the case of 256 × fS mode, a clock doubler
is used, whereas in 768 × fS mode, a divide-by-3 block (/3) is
first implemented, followed by a clock doubler. See Table XII.
Table XIII. Zero Detect
Table XII. MCLK Settings
Bit 2
Channel Zero Status
Bit 4
Bit 3
Oversample Ratio
0
1
Active High
Active Low
0
0
1
1
0
1
0
1
256 × fS (MCLK × 2 Internally)
512 × fS
768 × fS (MCLK × 2/3 Internally)
Reserved
DAC Volume Control Registers
The AD1833 has six volume control registers, one each for the
six DAC channels. Volume control is exercised by writing to the
relevant register associated with each DAC. This setting is used
to attenuate the DAC output. Full-scale setting (all 1s) is equiva-
lent to zero attenuation. See Table XV.
Channel Zero Status
The AD1833 provides individual logic output status indicators
when zero data is sent to a channel for 1024 or more consecutive
sample periods. There is also a global zero flag that indicates all
channels contain zero data. The polarity of the active zero signal
Table XIV. MCLK vs. Sample Rate Selection
MCLK (MHz)
512 fS
Sampling Rate fS (kHz)
Interpolator Mode
256 fS
768 fS
32
64
128
8× (Normal)
4× (Double)
2× (4 Times)
8.192
16.384
22.5792
24.576
24.576
44.1
88.2
176.4
8× (Normal)
4× (Double)
2× (4 Times)
11.2896
12.288
33.8688
36.864
48
96
192
8× (Normal)
4× (Double)
2× (4 Times)
Table XV. Volume Control Registers
Address
15–12
Reserved*
Volume Control
9–0
11
10
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
Channel 1 Volume Control (OUTL1)
Channel 2 Volume Control (OUTR1)
Channel 3 Volume Control (OUTL2)
Channel 4 Volume Control (OUTR2)
Channel 5 Volume Control (OUTL3)
Channel 6 Volume Control (OUTR3)
*Must be programmed to zero.
REV. 0
–11–
AD1833
I2S Timing
data. There is a delay of one bit clock from the time the L/RCLK
signal changes state to the first bit of data on the SDINx lines.
The data is written MSB first and is valid on the rising edge of
bit clock.
I2S timing uses an L/RCLK to define when the data being trans-
mitted is for the left channel and when it is for the right channel.
The L/RCLK is low for the left channel and high for the right
channel. A bit clock running at 64 × fS is used to clock in the
L/RCLK
RIGHT CHANNEL
LEFT CHANNEL
INPUT
BCLK
INPUT
SDATA
INPUT
MSB MSB
–1 –2
LSB LSB
+2 +1
MSB MSB
–1 –2
LSB LSB
+2 +1
MSB
LSB
MSB
LSB
MSB
Figure 4. I 2S Timing Diagram
Left Justified Timing
low for the right channel. A bit clock running at 64 × fS is used
to clock in the data. The first bit of data appears on the SDINx
lines at the same time the L/RCLK toggles. The data is written
MSB first and is valid on the rising edge of bit clock.
Left Justified (LJ) timing uses an L/RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/RCLK is high for the left channel and
L/RCLK
LEFT CHANNEL
INPUT
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB MSB
–1 –2
LSB LSB
+2 +1
MSB MSB
–1 –2
LSB LSB
+2 +1
MSB
MSB
LSB
MSB
LSB
MSB
–1
Figure 5. Left-Justified Timing Diagram
Right Justified Timing
to clock in the data. The first bit of data appears on the SDINx
8-bit clock periods (for 24-bit data) after L/RCLK toggles. In RJ
mode the LSB of data is always clocked by the last bit clock
before L/RCLK transitions. The data is written MSB first and
is valid on the rising edge of bit clock.
Right Justified (RJ) timing uses an L/RCLK to define when the
data being transmitted is for the left channel and when it is for
the right channel. The L/RCLK is high for the left channel and
low for the right channel. A bit clock running at 64 × fS is used
L/RCLK
LEFT CHANNEL
INPUT
RIGHT CHANNEL
BCLK
INPUT
SDATA
INPUT
MSB MSB
–1 –2
LSB LSB
+2 +1
MSB MSB
–1 –2
LSB LSB
+2 +1
LSB
MSB
LSB
MSB
LSB
Figure 6. Right-Justified Timing Diagram
–12–
REV. 0
AD1833
AUX-Mode Timing—Interfacing to a SHARC®
data destined for the auxiliary DAC is sent to it in standard
I2S format in the next frame using the SDIN2, SDIN3, and
SOUT pins as the L/RCLK, BCLK, and SDIN pins respec-
tively for communicating with the auxiliary DAC.
In AUX mode, the AD1833 is the master and generates a frame
sync signal (FSTDM) on its L/RCLK pin, and a bit clock
(BCLKTDM) on its BCLK pin, both of which are used to
control the data transmission from the SHARC. The bit clock
runs at a frequency of 256 × fS. In this mode all data is writ-
ten on the rising edge of the bit clock and read on the falling
edge of the bit clock. The AD1833 starts the frame by raising
a frame sync on the rising edge of bit clock. The SHARC recog-
nizes this on the following falling edge of bit clock, and is
ready to start outputting data on the next rising edge of bit
clock. Each channel is given a 32-bit clock slot, the data is left
justified and uses 16, 20, or 24 of the 32 bits. An enlarged dia-
gram (see Figure 6) is provided detailing this. The data is sent
from the SHARC to the AD1833 on the SDIN1 pin and is
provided in the following order, MSB first—Internal DACL0,
Internal DACL1, Internal DACL2, AUX DACL0, Internal
DACR0, Internal DACR1, Internal DACR2 and AUX DACR0.
The data is written on the rising edge of bit clock and read by
the AD1833 on the falling edge of bit clock. The left and right
DSP Mode Timing
DSP Mode Timing uses the rising edge of the frame sync
signal on the L/RCLK pin to denote the start of the transmis-
sion of a data word. Note that for both left and right channels a
rising edge is used; therefore in this mode there is no way to
determine which data is intended for the left channel and which is
intended for the right. The DSP writes data on the rising edge
of BCLK and the AD1833 reads it on the falling edge. The DSP
raises the frame sync signal on the rising edge of BCLK and
then proceeds to transmit data, MSB first, on the next rising
edge of BCLK. The data length can be 16, 20, or 24 bits. The
frame sync signal can be brought low any time at or after the
MSB is transmitted, but must be brought low at least one BCLK
period before the start of the next channel transmission.
FSTDM
BCLKTDM
INTERNAL
DAC L0
INTERNAL
DAC L1
INTERNAL
DAC L2
AUXILIARY
DAC L0
INTERNAL
DAC R0
INTERNAL
DAC R1
INTERNAL
DAC R2
AUXILIARY
DAC R0
BCLKTDM
MSB
MSB MSB
–2 –3
MSB
LSB
+8
LSB
+7
LSB
+6
LSB
+5
LSB
+4
LSB
+3
LSB
+2
LSB
+1
MSB
LSB
24-BIT DATA
–1
–4
MSB
MSB MSB
–2 –3
MSB
LSB
+4
LSB
+3
LSB
+2
LSB
+1
20-BIT DATA
16-BIT DATA
MSB
MSB
LSB
–1
–4
MSB
MSB MSB
MSB
LSB
–1
–2
–3
–4
Figure 7. Aux-Mode Timing
L/RCLK
BCLK
MSB
–1
MSB
–2
MSB
–3
MSB
–4
MSB
–5
MSB
–6
MSB
–1
MSB
–2
MSB
–3
MSB
–4
MSB
–5
MSB
–6
SDATA
MSB
MSB
MSB
32 BCLKs
32 BCLKs
Figure 8. DSP Mode Timing
SHARC is a registered trademark of Analog Devices, Inc.
REV. 0
–13–
AD1833
Packed Mode 128
Packed Mode 256
In Packed Mode 128, all six data channels are “packed” into
one sample interval on one data pin. The BCLK runs at 128 ×
fS; therefore there are 128 BCLK periods in each sample inter-
val. Each sample interval is broken into eight time slots, six slots
of 20 BCLKs and two of four BCLKs. The data length is restricted
in this mode to a maximum of 20 bits. The three left channels
are written first, MSB first, and the data is written on the falling
edge of BCLK. After the three left channels are written, there is
a space of four BCLKs and then the three right channels are
written. The L/RCLK defines the left and right data transmis-
sion; it is high for the three left channels and low for the three
right channels.
In Packed Mode 256 all six data channels are “packed” into one
sample interval on one data pin. The BCLK runs at 256 × fS;
therefore there are 256 BCLK periods in each sample interval.
Each sample interval is broken into eight time slots of 32 BCLKs
each. The data length can be 16, 20, or 24 bits. The three left
channels are written first, MSB first, and the data is written on
the falling edge of BCLK with a one BCLK period delay from
the start of the slot. After the three left channels are written,
there is a space of 32 BCLKs and then the three right channels
are written. The L/RCLK defines the left and right data trans-
mission; it is low for the three left channels and high for the
three right channels.
L/RCLK
BCLK
SLOT 1
LEFT 0
BLANK SLOT
4 SCLKs
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 0
BLANK SLOT
4 SCLKs
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
DATA
BCLK
MSB
MSB MSB
–2 –3
MSB
LSB
+4
LSB
+3
LSB
+2
LSB
+1
MSB
MSB
20-BIT DATA
16-BIT DATA
LSB
–1
–4
MSB
MSB MSB
–2 –3
MSB
LSB
–1
–4
Figure 9. Packed Mode 128
L/RCLK
BCLK
DATA
SLOT 1
LEFT 0
SLOT 2
LEFT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 0
SLOT 5
RIGHT 1
SLOT 6
RIGHT 2
BCLK
MSB
MSB MSB
MSB
LSB
+8
LSB
+7
LSB
+6
LSB
+5
LSB
+4
LSB
+3
LSB
+2
LSB
+1
MSB
MSB
MSB
LSB
24-BIT DATA
20-BIT DATA
16-BIT DATA
–1
–2
–3
–4
MSB
MSB MSB
–2 –3
MSB
LSB
+4
LSB
+3
LSB
+2
LSB
+1
LSB
–1
–4
MSB
MSB MSB
–2 –3
MSB
LSB
–1
–4
Figure 10. Packed Mode 256
–14–
REV. 0
AD1833
0
150pF
NPO
5.62k⍀
2.80k⍀
–20
V
OUT–
5.62k⍀
–40
–60
560pF
NPO
6
604⍀
7
OP275
VFILT
OUT
560pF
NPO
2.2nF
NPO
5
49.9k⍀
–80
2.80k⍀
V
OUT+
5.62k⍀
–100
150pF
NPO
5.62k⍀
–120
–140
0
20
40
60
80
100
120
kHz
Figure 11. Suggested Output Filter Schematic
Figure 14. Dynamic Range for 37 kHz @ –60 dBFS,
110 dB, Triangular Dithered Input
0
0
–20
–20
–40
–60
–80
–40
–60
–80
–100
–100
–120
–140
–120
–140
0
0
2
4
6
8
10
12
14
16
18
20
20
40
60
80
100
120
kHz
kHz
Figure 12. Dynamic Range for 1 kHz @ –60 dBFS,
110 dB, Triangular Dithered Input
Figure 15. Input 0 dBFS @ 37 kHz, BW 20 Hz to 120 kHz,
SR 96 kHz, THD + N –95 dBFS
0
0
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
–140
–140
–160
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
kHz
kHz
Figure 16. Noise Floor for Zero Input, SR 48 kHz,
SNR 110 dBFS A-Weighted
Figure 13. Input 0 dBFS @ 1 kHz, BW 20 Hz to 20 kHz, SR
48 kHz, THD + N –95 dBFS
REV. 0
–15–
AD1833
–20
–30
–40
–50
–60
–70
–80
–60
–70
–90
–80
–100
–90
–100
–110
–120
–110
–120
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
dBFS
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
dBFS
0
Figure 18. THD + N Ratio vs. Amplitude, @ 1 kHz,
SR 48 kHz
Figure 17. THD + N Ratio vs. Amplitude, Input 1 kHz,
SR 48 kHz, 24-Bit
–16–
REV. 0
AD1833
AVDD
5V
DVDD
–INTF
10F
5V
+
0.1F
10F
+
10F
+
10F
0.1F
0.1F
+
0.1F
10F
10F
10F
+
+
DVDD
0.1F
+
0.1F
0.1F
AVDD
0.1F
10F
14
15
16
1
2
47
48
45
46
CLATCH
CDATA
CCLK
CLATCH
CDATA
CCLK
OUTLP1
OUTLN1
L1+
L1–
L2+
L2–
L3+
L3–
OUTLP2
OUTLN2
10nF
10nF
26
11
12
19
9
SDATA
FSYNC
SCK
RXP
17
18
20
21
22
23
OUTLP3
OUTLN3
L/RCLK
BCLK
SDIN1
SDIN2
SDIN3
SOUT
MCLK
75RO
MCK
10
20
36
35
38
37
PAL
RXN
FILT
AD1833
R1+
R1–
R2+
OUTRP1
OUTRN1
OUTRP2
OUTRN2
23
24
18
17
M0
M1
M2
M3
R2–
R3+
19
40
39
DIR-CS8414
OUTRP3
OUTRN3
1
1k⍀
C
U
R3–
14
15
28
25
42
43
CBL
VERF
ERF
VREFX
FILTDAC
47nF
+
+
6
10F
0.1F
10F
0.1F
CO/EO
CA/E1
5
21
8
AGND
DGND
4
CB/E2
3
CC/F0
2
CD/F1
27
16
CE/F2
SEL
13
CS12/FCK
5V
L5
0.1F
10k⍀
5
SHLD1
SHLD1
6
OUT
1
U5
TORX173
2
4
SHLD1
SHLD1
Figure 19. Example Digital Interface
REV. 0
–17–
AD1833
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Thin Plastic Quad Flatpack
(ST-48)
0.063 (1.60)
MAX
0.354 (9.00) BSC SQ
0.030 (0.75)
0.018 (0.45)
37
48
36
1
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.003 (0.08)
12
25
0؇
MIN
13
24
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
0.057 (1.45)
0.053 (1.35)
7؇
0؇
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
–18–
REV. 0
–19–
–20–
相关型号：
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