EVAL-AD7606BFMCZ_技术文档

8-Channel DAS with 16-Bit, 800 kSPS

Bipolar Input, Simultaneous Sampling ADC

AD7606B

Data Sheet

FEATURES

APPLICATIONS

16-bit ADC with 800 kSPS on all channels

Input buffer with 5 MΩ analog input impedance

Pin to pin compatible with the AD7606

Power line monitoring

Protective relays

Multiphase motor control

Instrumentation and control systems

−40°C to +125°C operating temperature range

Single 5 V analog supply and 1.71 V to 3.6 V V_DRIVEsupply

21 V input clamp protection with 8 kV ESD

Extra modes available in software mode

Data acquisition systems

Per channel selectable analog input ranges

Single-ended, bipolar: 10 V, 5 V, and 2.5 V

Per channel system phase, offset, and gain calibration

Analog input open circuit detection feature

<20 LSB open circuit code error (R_PD= 10 kΩ)

Self diagnostics and monitoring features

CRC error checking on read/write data and registers

FUNCTIONAL BLOCK DIAGRAM

AV

CC

REGCAP

V

DRIVE

CC

ALDO

AD7606B

DLDO

5MΩ

V1

CLAMP

PGA

SAR

CLK OSC

V1GND

LPF

CONVST

RESET

5MΩ

CONTROL

INPUTS

V2

CLAMP

RANGE

V2GND

OS0 TO OS2

5MΩ

PROGRAMMABLE

DIGITAL FILTER

SW/HW MODE

CONTROL

V3

BUSY

CLAMP

FRSTDATA

V3GND

SERIAL

D

A TO D

D

OUT

5MΩ

SDI

V4

CLAMP

ADC, PGA, AND

CHANNEL

SCLK

CS

PARALLEL/

SERIAL

INTERFACE

V4GND

CONTROL

AND

PARALLEL

DB0 TO DB15

CONFIGURATION

5MΩ

V5

CLAMP

RD

WR

V5GND

SYSTEM GAIN,

OFFSET AND

PHASE

PAR/SER SEL

REFCAPA

5MΩ

CALIBRATION

V6

CLAMP

V6GND

5MΩ

DIAGNOSTICS

AND

ANALOG INPUT

OPEN DETECT

CONFIGURATION

V7

CLAMP

REFCAPB

V7GND

REFIN/REFOUT

5MΩ

V8

CLAMP

2.5V

REF

V8GND

LPF

REF SELECT

AGND

REFGND

Figure 1.

Rev. 0

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AD7606B

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

System Phase Calibration.......................................................... 29

System Gain Calibration............................................................ 29

System Offset Calibration ......................................................... 29

Analog Input Open Circuit Detection .................................... 30

Digital Interface.............................................................................. 32

Hardware Mode.......................................................................... 32

Software Mode............................................................................ 32

Parallel Interface......................................................................... 33

Serial Interface............................................................................ 35

Diagnostics ...................................................................................... 39

Reset Detection........................................................................... 39

Overvoltage and Undervoltage Events .................................... 39

Digital Error................................................................................ 39

Diagnostics Multiplexer ............................................................ 42

Typical Connection Diagram ....................................................... 44

Applications Information.............................................................. 46

Layout Guidelines....................................................................... 46

Register Summary .......................................................................... 48

Register Details ............................................................................... 50

Outline Dimensions....................................................................... 69

Ordering Guide .......................................................................... 69

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

Timing Specifications .................................................................. 6

Absolute Maximum Ratings.......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics ........................................... 14

Terminology .................................................................................... 20

Theory of Operation ...................................................................... 22

Analog Front End....................................................................... 22

SAR ADC..................................................................................... 23

Reference ..................................................................................... 23

Operation Modes........................................................................ 24

Digital Filter .................................................................................... 27

Padding Oversampling .............................................................. 28

External Oversampling Clock................................................... 28

System Calibration Features.......................................................... 29

REVISION HISTORY

6/2019—Revision 0: Initial Version

Rev. 0 | Page 2 of 69

Data Sheet

AD7606B

GENERAL DESCRIPTION

The AD7606B is a 16-bit, simultaneous sampling, analog-to-

digital data acquisition system (DAS) with eight channels,

each channel containing analog input clamp protection, a

programmable gain amplifier (PGA), a low-pass filter, and a

16-bit successive approximation register (SAR), analog-to-digital

converter (ADC). The AD7606B also contains a flexible digital

filter, low drift, 2.5 V precision reference and reference buffer to

drive the ADC and flexible parallel and serial interfaces.



Additional 2.5 V analog input range.

A n a l o g i npu t r a n g e ( 1 0 V, 5 V, a n d 2 . 5 V ) , s e l e c t a b l e

per channel.

Additional oversampling (OS) options, up to OS × 256.

System gain, system offset, and system phase calibration

per channel.

Analog input open circuit detector.

Diagnostic multiplexer.

Monitoring functions (serial peripheral interface (SPI)

invalid read/write, cyclic redundancy check (CRC),

overvoltage and undervoltage events, busy stuck monitor,

and reset detection).



The AD7606B operates from a single 5 V supply and accommo-

dates 10 V, 5 V, and 2.5 V true bipolar input ranges when

sampling at throughput rates of 800 kSPS for all channels. The

input clamp protection tolerates voltages up to 21 V. The

AD7606B has a 5 MΩ analog input impedance, resulting in less

than 20 LSB bipolar zero code when the input signal is discon-

nected and pulled to ground through a 10 kΩ external resistor.

The single supply operation, on-chip filtering, and high input

impedance eliminates the need for external driver op amps, which

require bipolar supplies. For applications with lower throughput

rates, the AD7606B flexible digital filter can be used to improve

noise performance.

Note that throughout this data sheet, multifunction pins, such

RD

as the

/SCLK pin, are referred to either by the entire pin

name or by a single function of the pin, for example, the SCLK pin,

when only that function is relevant.

Table 1. Pin to Pin Compatible Devices

Resolution

(Bits)

Single-Ended

Bipolar Inputs

True Differential

Bipolar Inputs

In hardware mode, the AD7606B is fully compatible with the

AD7606. In software mode, the following advanced features are

available:

18

16

AD7608

AD7606

AD7606B

AD7607

AD7609

14

Rev. 0 | Page 3 of 69

AD7606B

Data Sheet

SPECIFICATIONS

Voltage reference (V_REF) = 2.5 V external and internal, analog supply voltage (AV_CC) = 4.75 V to 5.25 V, logic supply voltage (V_DRIVE) =

1.71 V to 3.6 V, sample frequency (f_SAMPLE) = 800 kSPS, with no oversampling, T_A= −40°C to +125°C, single-ended input, and all input

voltage ranges, unless otherwise noted.

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

Input frequency (f_IN) = 1 kHz sine wave, unless

otherwise noted

No oversampling (OS), 10 V range

No OS, 5 V range

Signal-to-Noise Ratio (SNR)¹

87.5

86.5

83.5

92

90.5

87.5

89.5

88.5

86

93.5

92

dB

No OS, 2.5 V range

Oversampling ratio (OSR) = 16×, 10 V range

OSR = 16×, 5 V range

OSR = 16×, 2.5 V range

All input ranges

89

Total Harmonic Distortion (THD)

Signal-to-Noise-and-Distortion

f_SAMPLE= 200 kSPS

f_SAMPLE= 800 kSPS

No OS, 10 V range

No OS, 5 V range

−105 −94

−100 −90

88.5

87.7

85.5

92

91.3

88.7

−104

dB

86.5

85.5

83

89

No OS, 2.5 V range

OSR = 16×, 10 V range

OSR = 16×, 5 V range

OSR = 16×, 2.5 V range

86.5

Spurious-Free Dynamic Range

(SFDR)

Channel to Channel Isolation

Full Scale Step Settling Time

f_INon unselected channels up to 160 kHz

0.01% of full scale

10 V range

5 V range

2.5V range

−110

dB

70

110

130

μs

ANALOG INPUT FILTER

Full Power Bandwidth

−3 dB, 10 V range

−3 dB, 5 V range

−3 dB, 2.5 V range

−0.1 dB, 10 V range

−0.1 dB, 5 V range

−0.1 dB, 2.5 V range

10 V range

22.5

13.5

11.5

3

2

kHz

µs

Phase Delay

8

5 V range

9

µs

2.5 V range

11

µs

Phase Delay Matching

10 V range

5 V range

2.5 V range

240

365

445

ns

DC ACCURACY

Resolution

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

No missing codes

16

Bits

0.5

0.99

2

2.5

47

30

LSB²

LSB

f_SAMPLE= 200 kSPS

f_SAMPLE= 800 kSPS

Internal reference

External reference

1.16

3

2

Total Unadjusted Error (TUE)

Positive and Negative Full-

Scale (FS) Error³

LSB

Internal reference

2

45

LSB

Rev. 0 | Page 4 of 69

Data Sheet

AD7606B

Parameter

Test Conditions/Comments

R_FILTER⁴= 20 kΩ, system gain calibration disabled

R_FILTER⁴= 0 kΩ to 65 kΩ, system gain calibration enabled

Min

Typ

126

4

Max

Unit

LSB

Positive and Negative FS Error Drift External reference

Internal reference

Positive and Negative FS Error

Matching

1

4

5

15

20

ppm/°C

LSB

3

Bipolar Zero Code Error

T_A= −40°C to +85°C

1

20

14

2

LSB²

LSB

ppm/°C

LSB²

LSB

Bipolar Zero Code Error Drift

Bipolar Zero Code Error Matching

T_A= −40°C to +85°C

0.2

1.5

1.4

12

1ꢀ

22

23

14

30

20

35

25

40

30

Open Circuit Code Error

Pull-down resistor (R_PD)⁵= 10 kΩ, 10 V range

R_PD= 10 kΩ, 10 V range, T_A= −40°C to +85°C

R_PD= 10 kΩ, 5 V range

R_PD= 10 kΩ, 5 V range, T_A= −40°C to +85°C

R_PD= 10 kΩ, 2.5 V range

LSB

R_PD= 10 kΩ, 2.5 V range, T_A= −40°C to +85°C

ANALOG INPUT

Input Voltage Ranges

Vx − VxGND

10 V range

5 V range

2.5 V range

−10

−5

−2.5

+10

+5

+2.5

V

Input Voltage Ranges

VxGND − AGND

10 V range

5 V range

2.5 V range

−0.ꢀ

−0.1

+1.9

+2.ꢀ

+3.1

V

Analog Input Current

Input Capacitance (C_IN)⁶

Input Impedance (R_IN)^ꢀ

Input Impedance Drift

REFERENCE INPUT/OUTPUT

Reference Input Voltage

DC Leakage Current

See the Typical Performance Characteristics section

(V_IN− 2)/R_IN

μA

pF

MΩ

ppm/°C

5

1

25

REF SELECT = 0, external reference

2.495

2.5

2.505

0.12

V

μA

pF

V

ppm/°C

V

Input Capacitance⁶

ꢀ.5

2.5

3

Reference Output Voltage

Reference Temperature Coefficient

Reference Voltage to the ADC

LOGIC INPUTS

REF SELSECT = 1, internal reference, T_A= 25°C

REFCAPA (Pin 44) and REFCAPB (Pin 45)

2.49ꢀ

2.503

15

4.41

4.39

Input High Voltage (V_INH

)

0.ꢀ × V_DRIVE

V

Input Low Voltage (V_INL

Input Current (I_IN)

Input Capacitance⁶

LOGIC OUTPUTS

)

0.3 × V_DRIVE

1

V

μA

pF

5

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

Floating State Leakage Current

Output Capacitance⁶

Output Coding

Current source (I_SOURCE) = 100 μA

Current sink (I_SINK) = 100 μA

V_DRIVE− 0.2

V

μA

pF

N/A⁸

0.2

20

1

5

Twos complement

See Table 3

CONVERSION RATE

Conversion Time

Acquisition Time

0.ꢀ5

0.5

μs

Throughput Rate

Per channel

800

kSPS

Rev. 0 | Page 5 of 69

AD7606B

Data Sheet

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER REQUIREMENTS

AV_CC

V_DRIVE

REGCAP

4.75

1.71

1.875

5

5.25

3.6

1.93

V

AV_CCCurrent (I_AVCC

)

Normal Mode (Static)

Normal Mode (Operational)

7.5

43

8

3.5

0.5

9.5

47.5

10

4.5

5

mA

µA

f_SAMPLE= 800 kSPS

f_SAMPLE= 10 kSPS

Standby

Shutdown Mode

V_DRIVECurrent (I_DRIVE

)

Normal Mode (Static)

Normal Mode (Operational)

1.8

1.1

30

1.6

0.8

3.5

1.5

75

3

µA

mA

µA

f_SAMPLE= 800 kSPS

f_SAMPLE= 10 kSPS

Standby

Shutdown Mode

2

Power Dissipation

Normal Mode (Static)

Normal Mode (Operational)

40

230

42

18

2.5

50

255

50

24

25

mW

µW

f_SAMPLE= 800 kSPS

f_SAMPLE= 10 kSPS

Standby

Shutdown Mode

¹No OS means no oversampling is applied.

²LSB means least significant bit. With a 2.5 V input range, 1 LSB = 76.293 µV. With a 5 V input range, 1 LSB = 152.58 µV. With a 10 V input range, 1 LSB = 305.175 µV.

³These specifications include the full temperature range variation and contribution from the internal reference and reference buffer.

⁴R_FILTERis a resistor placed in a series to the analog input front-end. See Figure 57.

⁵See Figure 59.

⁶Not production tested. Sample tested during initial release to ensure compliance.

⁷Input impedance variation is factory trimmed and accounted for in the System Gain Calibration section.

⁸N/A means not applicable.

TIMING SPECIFICATIONS

Universal Timing Specifications

AV_CC= 4.75 V to 5.25 V, V_DRIVE= 1.71 V to 3.6 V, V_REF= 2.5 V external reference and internal reference, and T_A= −40°C to +125°C, unless

otherwise noted. Interface timing tested using a load capacitance of 20 pF, dependent on V_DRIVEand load capacitance for serial interface.

Table 3.

Parameter

Min

Typ

Max

Unit

Description

t_CYCLE

1.25

µs

Minimum time between consecutive CONVST rising edges (excluding

oversampling modes)¹

t_{LP_CNV}

10

ns

CONVST low pulse width

CONVST high pulse width

CONVST high to BUSY high delay time

V_DRIVE> 2.7 V

t_{HP_CNV}

t_{D_CNV_BSY}

20

25

ns

V_DRIVE< 2.7 V

t_{S_BSY}

t_{D_BSY}

0

Minimum time from BUSY falling edge to RD falling edge setup time

(in parallel interface) or to MSB being available on D_OUTx line (in serial interface)

25

ns

Maximum time between last RD falling edge (in parallel interface) or

last LSB being clocked out (serial interface) and the following BUSY falling

edge; read during conversion

t_CONV

0.65

2.2

0.85

2.3

4.8

9.9

20

μs

Conversion time; no oversampling

Oversampling by 2

4.65

9.6

Oversampling by 4

Oversampling by 8

19.4

Oversampling by 16

Rev. 0 | Page 6 of 69

Data Sheet

AD7606B

Parameter

Min

Typ

Max

40.2

80.8

161.9

324

Unit

μs

Description

39.2

Oversampling by 32

Oversampling by 64

Oversampling by 128

Oversampling by 256

78.7

μs

157.6

315.6

μs

t_RESET

Partial Reset

Full Reset

t_{DEVICE_SETUP}

Partial Reset

Full Reset

t_WAKE-UP

55

2000

ns

µs

ns

µs

Partial RESET high pulse width

3000

Full RESET high pulse width

Time between RESET falling edge and first CONVST rising edge

50

253

Wake-up time after standby/shutdown mode

Standby

Shutdown

t_POWER-UP

1

10

µs

ms

Time between stable V_CC/V_DRIVEand assert of RESET

¹Applies to serial mode when all four D_OUTx lines are selected.

AV

DRIVE

CC

V

t

POWER-UP

t

RESET

t

CYCLE

DEVICE_SETUP

t

HP_CNV

t

LP_CNV

CONVST

t

CONV

t

D_CNV_BSY

BUSY

CS

t

D_BSY

t

S_BSY

READ DURING

CONVERSION

READ AFTER

CONVERSION

Figure 2. Universal Timing Diagram

Parallel Mode Timing Specifications

Table 4.

Parameter

Min

Typ

Max

Unit

Description

t_{S_}

0

ns

CS falling edge to RD falling edge setup time

RD rising edge to CS rising edge hold time

_RD

CS

t_{H_RD_}

0

ns

CS

t_{HP_RD}

t_{LP_RD}

10

ns

RD high pulse width

RD low pulse width

CS high pulse width

t_{HP_}

CS

t_{D_}

35

ns

Delay from CS until DBx three-state disabled

CS to DBx hold time

_DB

CS

t_{H_}

0

_DB

t_{D_RD_DB}

Data access time after falling edge of RD

V_DRIVE> 2.7 V

V_DRIVE< 2.7 V

Data hold time after falling edge of RD

CS rising edge to DBx high impedance

27

37

ns

t_{H_RD_DB}

12

t_{DHZ_}

40

_DB

CS

t_{CYC_RD}

RD falling edge to next RD falling edge

30

40

ns

V_DRIVE> 2.7 V

V_DRIVE< 2.7 V

t_{D_}

26

Delay from CS falling edge until FRSTDATA three-state disabled

_FD

CS

Rev. 0 | Page 7 of 69

AD7606B

Data Sheet

Parameter

t_{D_RD_FDH}

t_{D_RD_FDL}

t_{DHZ_FD}

Min

Typ

Max

30

Unit

ns

Description

Delay from RD falling edge until FRSTDATA high

Delay from RD falling edge until FRSTDATA low

Delay from CS rising edge until FRSTDATA three-state enabled

CS to WR setup time

30

ns

28

ns

t_{S_}

0

ns

_WR

CS

t_{HP_WR}

t_{LP_WR}

213

ns

WR high pulse width

WR low pulse width

V_DRIVE> 2.7 V

V_DRIVE< 2.7 V

WR hold time

88

213

0

ns

t_{H_WR_}

CS

t_{S_DB_WR}

t_{H_WR_DB}

t_{CYC_WR}

5

ns

Configuration data to WR setup time

5

Configuration data to WR hold time

230

Configuration data settle time, WR rising edge to next WR rising edge

CS

t_{S_CS_RD}

t_{HP_RD}

t_{H_RD_CS}

t_{LP_RD}

RD

t_{D_RD_DB}

t_{CYC_RD}

t_{H_RD_DB}

t_{H_CS_DB}

t_{DHZ_CS_DB}

t_{D_CS_DB}

DB0 TO DB15

t_{D_CS_FD}

VIN8

x

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

t_{D_RD_FDL}

t_{D_RD_FDH}

t_{DHZ_FD}

FRSTDATA

CS

Figure 3. Parallel Mode Read Timing Diagram, Separate and

RD

Pulses

t_{CYC_RD}

t_{HP_CS}

CS AND RD

t_{LP_RD}

t_{H_CS_DB}

t_{DHZ_CS_DB}

t_{D_RD_DB}

DB0 TO DB15

FRSTDATA

CS

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

VIN8

t_{D_CS_FD}

t_{D_RD_FDL}

t_{DHZ_FD}

CS

RD

Figure 4. Parallel Mode Read Timing Diagram, Linked and

t_{HP_WR}

t_{H_WR_CS}

t_{S_CS_WR}

t_{CYC_WR}

WR

t_{LP_WR}

t_{S_DB_WR}

t_{H_WR_DB}

DB0 TO DB15

Figure 5. Parallel Mode Write Operation Timing Diagram

Rev. 0 | Page 8 of 69

Data Sheet

AD7606B

Serial Mode Timing Specifications

Table 5.

Parameter

Min

Typ

Max

Unit

Description

f_SCLK

SCLK frequency; f_SCLK= 1/t_SCLK

V_DRIVE> 2.7 V

V_DRIVE< 2.7 V

Minimum SCLK period

CS to SCLK falling edge setup time

60

40

MHz

μs

t_SCLK

t_{S_}

1/f_SCLK

2

ns

_SCK

CS

t_{H_SCK_}

2

ns

SCLK to CS rising edge hold time

CS

t_{LP_SCK}

t_{HP_SCK}

t_{D_}

0.4 × t_SCLK

ns

SCLK low pulse width

SCLK high pulse width

Delay from CS until D_OUTx three-state disabled

_DO

CS

9

18

ns

V_DRIVE> 2.7 V

V_DRIVE< 2.7 V

t_{D_SCK_DO}

Data out access time after SCLK rising edge

V_DRIVE> 2.7 V

V_DRIVE< 2.7 V

Data out hold time after SCLK rising edge

Data in setup time before SCLK falling edge

Data in hold time after SCLK falling edge

CS rising edge to D_OUTx high impedance

15

25

ns

t_{H_SCK_DO}

t_{S_SDI_SCK}

t_{H_SCK_SDI}

t_{DHZ_}

8

0

_DO

CS

7

22

ns

V_DRIVE> 2.7 V

V_DRIVE< 2.7 V

t_WR

t_{D_}

25

Time between writing and reading the same register or between two writes;

if f_SCLK>50 MHz

26

ns

Delay from CS until D_OUTx three-state disabled/delay from CS until MSB valid

_FD

CS

t_{D_SCK_FDL}

t_{DHZ_FD}

18

28

ns

16^thSCLK falling edge to FRSTDATA low

CS rising edge until FRSTDATA three-state enabled

CS

t_{HP_SCK}

t_{H_SCK_CS}

t_{S_CS_SCK}

t_SCLK

SCLK

1

2

3

14

15

16

t

LP_SCK

t_{D_CS_DO}

t_{DHZ_CS_DO}

t_{D_SCK_DO}

t_{H_SCK_DO}

D

x

DB

0

OUT

15

14

13

2

1

t_{D_SCK_FDL}

t_{D_CS_FD}

t_{DHZ_FD}

FRSTDATA

CS

Figure 6. Serial Timing Diagram, ADC Read Mode (Channel 1)

t_SCLK

t_{S_CS_SCK}

t_{HP_SCK}

t_{H_SCK_CS}

1

2

3

8

9

7

16

SCLK

t_{LP_SCK}

t_{H_SCK_SDI}

t_{S_SDI_SCK}

t_WR

ADD5

ADD0

DIN

SDI

WEN

R/W

0

t_{D_CS_DO}

t_{D_SCK_DO}

D

x

D

7

D

0

OUT

Figure 7. Serial Interface Timing Diagram, Register Map Read/Write Operations

Rev. 0 | Page 9 of 69

AD7606B

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 6.

Parameter

Rating

AV_CCto AGND

V_DRIVEto AGND

−0.3 V to +7 V

−0.3 V to AV_CC+ 0.3 V

21 V

−0.3 V to V_DRIVE+ 0.3 V

−0.3 V to AV_CC+ 0.3 V

10 mA

−40°C to +125°C

−65°C to +150°C

150°C

Analog Input Voltage to AGND¹

Digital Input Voltage to AGND

Digital Output Voltage to AGND

REFIN to AGND

Input Current to Any Pin Except Supplies¹

Operating Temperature Range

Storage Temperature Range

Junction Temperature

Pb/Sn Temperature, Soldering

Reflow (10 sec to 30 sec)

Pb-Free Temperature, Soldering Reflow

Electrostatic Discharge (ESD)

All Pins Except Analog Inputs

Analog Input Pins Only

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit

board (PCB) design and operating environment. Close

attention to PCB thermal design is required.

θ_JAis the natural convection junction to ambient thermal

resistance measured in a one cubic foot sealed enclosure. θ_JCis

the junction to case thermal resistance.

240 (+0)°C

260 (+0)°C

Table 7. Thermal Resistance

Package Type

1

θ_JA

θ_JC

Unit

ST-64-2

40

7

°C/W

3.5 kV

8 kV

¹Simulated data based on JEDEC 2s2p thermal test PCB in a JEDEC natural

convention environment.

¹Transient currents of up to 100 mA do not cause silicon controlled

rectifier (SCR) latch-up.

ESD CAUTION

Rev. 0 | Page 10 of 69

Data Sheet

AD7606B

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

AV

CC

2

3

AGND

OS0

AGND

REFGND

REFCAPB

REFCAPA

REFGND

REFIN/REFOUT

AGND

4

OS1

5

OS2

6

PAR/SER SEL

STBY

AD7606B

TOP VIEW

(Not to Scale)

7

8

RANGE

CONVST

WR

9

AGND

10

11

12

13

14

15

16

REGCAP

RESET

RD/SCLK

CS

AV

CC

REGCAP

AGND

BUSY

FRSTDATA

DB0

REF SELECT

DB15

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

ANALOG INPUT

DATA OUTPUT

DECOUPLING CAPACITOR PIN

POWER SUPPLY

DIGITAL OUTPUT

DIGITAL INPUT

REFERENCE INPUT/OUTPUT

GROUND PIN

Figure 8. Pin Configuration

Table 8. Pin Function Description

Pin No.

Type¹

Mnemonic

Description

1, 37, 38, 48

P

AV_CC

Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end

amplifiers and to the ADC core. Decouple these supply pins to AGND.

2, 26, 35, 40,

41, 47

P

AGND

Analog Ground. These pins are the ground reference points for all analog circuitry on the

AD7606B. All analog input signals and external reference signals must be referred to these pins. All

six of the AGND pins must connect to the AGND plane of a system.

3 to 5

DI

OS0 to OS2

Oversampling Mode Pins. These inputs select the oversampling ratio or enable software mode

(see Table 12 for oversampling pin decoding). See the Digital Filter section for more details about

the oversampling mode of operation.

6

7

PAR/SER SEL Parallel/Serial Interface Selection Input. If this pin is tied to a logic low, the parallel interface is

selected. If this pin is tied to a logic high, the serial interface is selected. See the Digital Interface

section for more information on each interface available.

STBY

Standby Mode Input. In hardware mode, this pin, in combination with the RANGE pin, places the

AD7606B in one of two power-down modes: standby mode or shutdown mode. In software mode,

this pin is ignored. Therefore, it is recommended to connect this pin to logic high. See the Power-

Down Modes section for more information on both hardware mode and software mode.

8

DI

RANGE

CONVST

WR

Analog Input Range Selection Input. In hardware mode, this pin determines the input range of the

analog input channels (see Table 9). If the STBY pin is at logic low, this pin determines the power-

down mode (see Table 14). In software mode, the RANGE pin is ignored. However, this pin must be

tied high or low.

Conversion Start Input. When the CONVST pin transitions from low to high, the analog input is

sampled on all eight SAR ADCs. In software mode, this pin can be configured as external

oversampling clock. Providing a low jitter external clock improves the SNR performance for large

oversampling ratios. See the External Oversampling Clock section for further details.

9

10

Digital Input. In hardware mode, this pin has no function. Therefore, it can be tied high, tied low,

or shorted to CONVST. In software mode, this pin is an active low write pin for writing registers

using the parallel interface. See the Parallel Interface section for more information.

Rev. 0 | Page 11 of 69

AD7606B

Data Sheet

Pin No.

Type¹

Mnemonic

Description

11

DI

RESET

Reset Input, Active High. Full and partial reset options are available on the AD7606B. The type of

reset is determined by the length of the reset pulse. It is recommended that the device receives a

full reset pulse after power-up. See the Reset Functionality section for further details.

12

DI

RD/SCLK

Parallel Data Read Control Input when the Parallel Interface is Selected (RD).

Serial Clock Input when the Serial Interface is Selected (SCLK). See the Digital Interface section for

more details.

13

14

15

DI

CS

Chip Select. This pin is the active low chip select input for ADC data read or register data read and

write, in both serial and parallel interface. See the Digital Interface section for more details.

Busy Output. This pin transitions to a logic high along with the CONVST rising edge. The BUSY

output remains high until the conversion process for all channels is complete.

First Data Output. The FRSTDATA output signal indicates when the first channel, V1, is being read

back on the parallel interface (see Figure 3) or the serial interface (see Figure 6). See the Digital

Interface section for more details.

DO

BUSY

FRSTDATA

16 to 22

23

DO/DI

P

DB0 to DB6

V_DRIVE

Parallel Output/Input Data Bits. When using parallel interface, these pins act as three-state parallel

digital input and output pins (see the Parallel Interface section). When using serial interface, tie

these pins to AGND.

Logic Power Supply Input. The voltage (1.71 V to 3.6 V) supplied at this pin determines the

operating voltage of the interface. This pin is nominally at the same supply as the supply of the

host interface, that is, data signal processing (DSP) and field programmable gate array (FPGA).

24

DO/DI

DB7/D_OUT

DB8/D_OUT

DB9/D_OUT

A

B

C

Parallel Output/Input Data Bit 7 (DB7)/Serial Interface Data Output Pin (D_OUTA). When using the

parallel interface, this pin acts as a three-state parallel digital input/output pin. When using the

serial interface, this pin functions as D_OUTA. See Table 21 and Table 22 for more details on each

data interface and operation mode.

Parallel Output/Input Data Bit 8 (DB8)/Serial Interface Data Output Pin (D_OUTB). When using the

parallel interface, this pin acts as a three-state parallel digital input and output pin. When using

the serial interface, this pin functions as D_OUTB. See Table 21 and Table 22 for more details on each

data interface and operation mode.

Parallel Output/Input Data Bit 9 (DB9)/Serial Interface Data Output Pin (D_OUTC). When using the

parallel interface, this pin acts as a three-state parallel digital input and output pin. When using

the serial interface, this pin functions as D_OUTC if in software mode and using four data output lines

option. See Table 21 and Table 22 for more details on each data interface and operation mode.

Parallel Output/Input Data Bit 10 (DB10)/Serial Interface Data Output Pin (D_OUTD). When using the

parallel interface, this pin acts as a three-state parallel digital input/output pin. When using the

serial interface, this pin functions as D_OUTD if in software mode and using the four data output lines

option. See Table 21 and Table 22 for more details on each data interface and operation mode.

25

27

28

29

DO/DI

DB10/D_OUT

DB11/SDI

D

Parallel Output/Input Data Bit DB11/Serial Data Input. When using the parallel interface, this pin

acts as a three-state parallel digital input and output pin. When using the serial interface in

software mode, this pin functions as serial data input. See Table 21 and Table 22 for more details

on each data interface and operation mode.

30 to 33

34

DO/DI

DI

DB12 to

DB15

Parallel Output/Input Data Bits, DB15 to DB12. When using the parallel interface, these pins act as

three-state parallel digital input and output pins (see the Parallel Interface section). When using

the serial interface, tie these pins to AGND.

Internal/External Reference Selection Logic Input. If this pin is set to logic high, the internal

reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled

and an external reference voltage must be applied to the REFIN/REFOUT pin.

Decoupling Capacitor Pins for Voltage Output from 1.9 V Internal Regulator, Analog Low

Dropout (ALDO) and Digital Low Dropout (DLDO). These output pins must be decoupled

separately to AGND using a 1 μF capacitor.

Reference Input (REFIN)/Reference Output (REFOUT). The internal 2.5 V reference is available on

the REFOUT pin for external use while the REF SELECT pin is set to logic high. Alternatively, by

setting the REF SELECT pin to logic low, the internal reference is disabled and an external

reference of 2.5 V must be applied to this input (REFIN). A 100 nF capacitor must be applied from

the REFIN pin to ground, close to the REFGND pins, for both internal and external reference

options. See the Reference section for more details.

REF SELECT

REGCAP

36, 39

42

P

REF

REFIN/

REFOUT

43, 46

44, 45

REF

REFGND

REFCAPA,

REFCAPB

Reference Ground Pins. These pins must be connected to AGND.

Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled

to AGND using a low effective series resistance (ESR), 10 μF ceramic capacitor. The voltage on

these pins is typically 4.4 V.

49

50

AI

V1

Channel 1 Positive Analog Input Pin.

Channel 1 Negative Analog Input Pin.

Rev. 0 | Page 12 of 69

AI GND V1GND

Data Sheet

AD7606B

Pin No.

51

52

53

54

55

56

57

58

59

60

61

62

63

64

Type¹

AI

Mnemonic

Description

V2

Channel 2 Positive Analog Input Pin.

Channel 2 Negative Analog Input Pin.

Channel 3 Positive Analog Input Pin.

Channel 3 Negative Analog Input Pin.

Channel 4 Positive Analog Input Pin.

Channel 4 Negative Analog Input Pin.

Channel 5 Positive Analog Input Pin.

Channel 5 Negative Analog Input Pin.

Channel 6 Positive Analog Input Pin.

Channel 6 Negative Analog Input Pin.

Channel 7 Positive Analog Input Pin.

Channel 7 Negative Analog Input Pin.

Channel 8 Positive Analog Input Pin.

Channel 8 Negative Analog Input Pin.

AI GND V2GND

AI V3

AI GND V3GND

AI V4

AI GND V4GND

AI V5

AI GND V5GND

AI V6

AI GND V6GND

AI V7

AI GND V7GND

AI V8

AI GND V8GND

¹P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, and GND is ground.

Rev. 0 | Page 13 of 69

AD7606B

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0

–20

AV = 5V, V

= 3.3V

AV = 5V, V

INTERNAL REFERENCE

±5V RANGE

f_SAMPLE= 800kSPS

f_IN= 1kHz

32768 POINT FFT

SNR = 88.3dB

THD = –103dB

= 3.3V

CC

DRIVE

CC

DRIVE

INTERNAL REFERENCE

–20

–40

±10V RANGE

f_SAMPLE= 800kSPS

f_IN= 1kHz

32768 POINT FFT

SNR = 89.2dB

–40

–60

THD = –108.3dB

–80

–100

–120

–140

–160

–180

–100

–120

–140

–160

–180

0.1

1

10

100

0.1

1

10

100

INPUT FREQUENCY (kHz)

Figure 9. Fast Fourier Transform (FFT), 10 V Range

Figure 12. FFT, 5 V Range

0

–20

0

–20

AV = 5V, V = 3.3V

DRIVE

INTERNAL REFERENCE

±10V RANGE

f_SAMPLE= 800kSPS

f_IN= 146Hz

8192 POINT FFT

SNR = 93.6dB

THD = –110dB

AV = 5V, V

INTERNAL REFERENCE

±2.5V RANGE

f_SAMPLE= 800kSPS

f_IN= 1kHz

32768 POINT FFT

SNR = 86dB

THD = –98.5dB

= 3.3V

CC

DRIVE

–40

–60

–80

–100

–120

–140

–160

–180

–200

–100

–120

–140

–160

–180

0.1

1

10

100

0

5

10

15

20

25

INPUT FREQUENCY (kHz)

Figure 10. FFT, 2.5 V Range

Figure 13. FFT Oversampling by 16, 10 V Range

2.0

1.5

2.0

1.5

AV = 5V, V

= 3.3V

AV = 5V, V

= 3.3V

CC

DRIVE

CC

DRIVE

INTERNAL REFERENCE

f_SAMPLE= 800kSPS

T = 25°C

INTERNAL REFERENCE

f_SAMPLE= 800kSPS

T = 25°C

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–0.5

–1.0

–1.5

–2.0

0

10000

20000

30000

40000

50000

60000

0

10000

20000

30000

40000

50000

60000

ADC CODE

Figure 11. Typical INL, 10 V Range

Figure 14. Typical DNL

Rev. 0 | Page 14 of 69

Data Sheet

AD7606B

100

98

96

94

92

90

88

86

84

82

80

100

98

96

94

92

90

88

86

NO OS

OS BY 2

OS BY 4

OS BY 8

OS BY 16

OS BY 32

OS BY 64

OS BY 128

OS BY 256

NO OS

OS BY 2

OS BY 4

OS BY 8

OS BY 16

OS BY 32

OS BY 64

OS BY 128

OS BY 256

AV = 5V, V

= 3.3V

AV = 5V, V

= 3.3V

CC

DRIVE

CC

84

DRIVE

f_SAMPLE= 800KSPS/OSR

f_SAMPLE= 800kSPS/OSR

INTERNAL REFERENCE

T = 25°C

INTERNAL REFERENCE

T = 25°C

82

80

±10V RANGE

0.01

0.1

1

10

100

0.01

0.1

1

10

100

INPUT FREQUENCY (kHz)

Figure 18. SNR vs. Input Frequency for Different OSR Values, 10 V Range,

External OS Clock

Figure 15. SNR vs. Input Frequency for Different OSR Values, 10 V Range,

Internal OS Clock

100

98

96

94

92

90

100

NO OS

OS BY 2

98

96

94

92

90

88

86

84

82

80

OS BY 4

OS BY 8

OS BY 16

OS BY 32

OS BY 64

OS BY 128

OS BY 256

88

NO OS

OS BY 2

86

OS BY 4

OS BY 8

AV = 5V, V

= 3.3V

AV = 5V, V

= 3.3V

CC

DRIVE

CC

DRIVE

84

82

80

OS BY 16

OS BY 32

OS BY 64

OS BY 128

OS BY 256

f_SAMPLE= 800kSPS/OSR

INTERNAL REFERENCE

T = 25°C

INTERNAL REFERENCE

T = 25°C

±5V RANGE

0.01

0.1

1

10

100

0.01

0.1

1

10

100

INPUT FREQUENCY (kHz)

Figure 16. SNR vs. Input Frequency for Different OSR Values, 5 V Range,

Internal OS Clock

Figure 19. SNR vs. Input Frequency for Different OSR Values, 5 V Range,

External OS Clock

100

NO OS

OS BY 2

98

96

94

92

90

88

86

84

82

80

OS BY 4

OS BY 8

OS BY 16

OS BY 32

OS BY 64

OS BY 128

OS BY 256

95

90

NO OS

OS BY 2

85

OS BY 4

AV = 5V, V

= 3.3V

AV = 5V, V

= 3.3V

CC

DRIVE

OS BY 8

CC

DRIVE

OS BY 16

OS BY 32

OS BY 64

OS BY 128

OS BY 256

f_SAMPLE= 800kSPS/OSR

INTERNAL REFERENCE

T = 25°C

INTERNAL REFERENCE

T = 25°C

±2.5V RANGE

80

0.01

0.1

1

10

100

0.01

0.1

1

10

100

INPUT FREQUENCY (kHz)

Figure 20. SNR vs. Input Frequency for Different OSR Values, 2.5 V Range,

External OS Clock

Figure 17. SNR vs. Input Frequency for Different OSR Values, 2.5 V Range,

Internal OS Clock

Rev. 0 | Page 15 of 69

AD7606B

Data Sheet

91

90

89

88

87

86

–60

–70

±10V RANGE

AV = 5V V

f_SAMPLE= 800kSPS

= 3.3V

CC

DRIVE

f_SAMPLE= 800kSPS

R

MATCHED ON Vx AND VxGND

SOURCE

–80

–90

–100

–110

–120

0Ω

1.2kΩ

5kΩ

10kΩ

23.7kΩ

48.7kΩ

105kΩ

85

84

±2.5V

±5V

±10V

–40

–20

0

20

40

60

80

100

120

10

0.01

0.1

1

10

100

TEMPERATURE (°C)

INPUT FREQUENCY (kHz)

Figure 21. SNR vs. Temperature

Figure 24. THD vs. Input Frequency for Various Source Impedances,

10 V Range

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

–60

AV = 5V, V

f_SAMPLE= 800kSPS

T = 25°C

= 3.3V

±5V RANGE

0Ω

CC

DRIVE

1.2kΩ

5kΩ

f_SAMPLE= 800kSPS

R

MATCHED ON Vx AND VxGND

SOURCE

10kΩ

23.7kΩ

48.7kΩ

105kΩ

–70

–80

–90

–100

–

110

–120

0.01

–40

–20

0

20

40

60

80

100

0.1

1

10

100

TEMPERATURE (°C)

INPUT FREQUENCY (kHz)

Figure 22. Reference Drift

Figure 25. THD vs. Input Frequency for Various Source Impedances,

5 V Range

25

20

15

10

5

–60

±2.5V RANGE

0Ω

1.2kΩ

5kΩ

10kΩ

23.7kΩ

48.7kΩ

105kΩ

f_SAMPLE= 800kSPS

R

MATCHED ON Vx AND VxGND

SOURCE

–70

–80

–90

–100

–

110

0

–120

0.01

–10

–5

0

5

0.1

1

10

100

REFERENCE DRIFT (ppm/°C)

INPUT FREQUENCY (kHz)

Figure 23. Reference Drift Histogram

Figure 26. THD vs. Input Frequency for Various Source Impedances,

2.5 V Range

Rev. 0 | Page 16 of 69

Data Sheet

AD7606B

30

45

40

35

30

25

20

15

10

5

NFS CH1

NFS CH3

NFS CH5

NFS CH7

PFS CH1

PFS CH3

PFS CH5

PFS CH7

NFS CH2

NFS CH4

NFS CH6

NFS CH8

PFS CH2

PFS CH4

PFS CH6

PFS CH8

20

10

0

–10

–20

–30

0

–40

–20

0

20

40

60

80

100

120

–10

–5

0

5

10

TEMPERATURE (°C)

NFS DRIFT (ppm/°C)

Figure 27. Positive Full-Scale(PFS)/Negative Full-Scale (NFS) Error vs.

Temperature, 10 V Range

Figure 30. PFS/NFS Drift Histogram, External Reference

25

45

NFS CH1

NFS CH3

NFS CH5

NFS CH7

PFS CH1

PFS CH3

PFS CH5

PFS CH7

NFS CH2

NFS CH4

NFS CH6

NFS CH8

PFS CH2

PFS CH4

PFS CH6

PFS CH8

20

15

40

35

30

25

20

15

10

5

10

5

0

–5

–10

–15

–20

–25

0

–40

–20

0

20

40

60

80

100

120

–10

–5

0

5

10

TEMPERATURE (°C)

NFS DRIFT (ppm/°C)

Figure 28. PFS/NFS Error vs. Temperature, 5 V Range

Figure 31. PFS/NFS Drift Histogram, Internal Reference

20

15

–40

–50

–60

–70

–80

–90

–100

±10V RANGE

±5V RANGE

±2.5V RANGE

10

5

0

–5

–10

–15

–20

–25

NFS CH1

NFS CH3

NFS CH5

NFS CH7

PFS CH1

PFS CH3

PFS CH5

PFS CH7

NFS CH2

NFS CH4

NFS CH6

NFS CH8

PFS CH2

PFS CH4

PFS CH6

PFS CH8

AV = 5V, V

= 3.3V

CC

DRIVE

INTERNAL REFERENCE

RECOMMENDED DECOUPLING USED

f_SAMPLE= 800kSPS

T = 25°C

–40

–20

0

20

40

60

80

100

120

0.1

1

10

100

TEMPERATURE (°C)

AV NOISE FREQUENCY (kHz)

CC

Figure 29. PFS/NFS Error vs. Temperature, 2.5 V Range

Figure 32. AC PSRR

Rev. 0 | Page 17 of 69

AD7606B

Data Sheet

1400

1200

1000

800

600

400

200

0

6.0

CH1

Vx AND VxGND

SHORTED TOGETHER

T = 25°C

4096 SAMPLES

MEAN = 32767.8

SIGMA = 1.2

1303

CH2

CH3

CH4

CH5

CH6

CH7

CH8

4.8

3.6

1163

2.4

782

1.2

0

–1.2

–2.4

–3.6

–4.8

–6.0

458

246

AV = 5V, V

INTERNALREFERENCE

f_SAMPLE= 800kSPS

= 3.3V

CC

DRIVE

91

32765 32766 32767 32768 32769 32770 32771 32772

ADC CODE

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 36. Histogram of Codes, 10 V Range

Figure 33. Bipolar Zero Code Error vs. Temperature, 10 V Range

2000

12.0

CH1

Vx AND VxGND

SHORTED TOGETHER

T = 25°C

4096 SAMPLES

MEAN = 32767.8

SIGMA = 0.92

CH2

1800

1600

1400

1200

1000

800

600

400

200

0

9.6

1727

CH3

CH4

CH5

CH6

CH7

CH8

7.2

4.8

1182

2.4

0

878

–2.4

–4.8

–7.2

–9.6

–12.0

AV = 5V, V

INTERNAL REFERENCE

f_SAMPLE= 800kSPS

= 3.3V

CC

DRIVE

177

119

6

32765

32766

32767

32768

32769

32770

32771

32772

–40

–20

0

20

40

60

80

100

120

ADC CODE

TEMPERATURE (°C)

Figure 37. Histogram of Codes, 5 V Range

Figure 34. Bipolar Zero Code Error vs. Temperature, 5 V Range

1800

24.0

CH1

1702

Vx AND VxGND

1667

CH2

SHORTED TOGETHER

T = 25°C

19.2

CH3

1600

1400

1200

1000

800

600

400

200

0

CH4

4096 SAMPLES

MEAN = 32767.5

SIGMA = 0.8

CH5

CH6

CH7

CH8

14.4

9.6

4.8

0

–4.8

–9.6

–14.4

–19.2

–24.0

415

281

AV = 5V, V

= 3.3V

CC

DRIVE

INTERNAL REFERENCE

f

= 800kSPS

23

8

SAMPLE

32765 32766 32767 32768 32769 32770 32771 32772

ADC CODE

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 38. Histogram of Codes, 2.5 V Range

Figure 35. Bipolar Zero Code Error vs. Temperature, 2.5 V Range

Rev. 0 | Page 18 of 69

Data Sheet

AD7606B

50

45

40

35

30

25

20

15

10

5

6

AV = 5V, V

f_SAMPLE= 800kSPS

T = 25°C

= 3.3V

CC

DRIVE

NORMAL MODE

AUTOSTANDBY MODE

4

2

0

–2

–4

–6

AV = 5V, V

INTERNAL REFERENCE

T = 25°C

= 3.3V

±10V

±5V

CC

DRIVE

±2.5V

0

200

400

600

800

1000

–10

–8

–6

–4

–2

0

2

4

6

8

10

THROUGHPUT RATE (kSPS)

INPUT VOLTAGE (V)

Figure 39. Analog Input Current vs. Input Voltage

Figure 41. AV_CCSupply Current vs. Throughput Rate

–50

–60

50

45

40

35

30

25

20

15

10

5

AV = 5V,V = 3.3V

DRIVE

INTERNAL REFERENCE

±10V RANGE

±5V RANGE

±2.5V RANGE

T = –40°C

T = +25°C

T = +125°C

CC

f_SAMPLE= 800kSPS

T = 25°C

–70

INTERFERER IN ALL

UNSELECTED CHANNELS

–80

–90

–100

–110

–120

–130

–140

AV = 5V, V

INTERNAL REFERENCE

T = 25°C

= 3.3V

CC

DRIVE

0

20

40

60

80

100

120

140

160

0

100

200

300

400

500

600

700

800

NOISE FREQUENCY (kHz)

THROUGHPUT RATE (kSPS)

Figure 42. Channel to Channel Isolation vs. Noise Frequency

Figure 40. AV_CCSupply Current vs. Throughput Rate

Rev. 0 | Page 19 of 69

AD7606B

Data Sheet

TERMINOLOGY

Integral Nonlinearity (INL)

The ratio depends on the number of quantization levels in

INL is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The

endpoints of the transfer function are zero scale at ½ LSB below

the first code transition and full scale at ½ LSB above the last code

transition.

the digitization process: the more levels, the smaller the

quantization noise.

The theoretical SINAD for an ideal N-bit converter with a sine

wave input is given by

SINAD = (6.02 N + 1.76) (dB)

Differential Nonlinearity (DNL)

DNL is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Thus, for a 16-bit converter, the SINAD is 98 dB.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the harmonics to the

fundamental. For the AD7606B, THD is defined as

Bipolar Zero Code Error

Bipolar zero code error is the deviation of the midscale

transition (all 1s to all 0s) from the ideal, which is 0 V − ½ LSB.

THD (dB) =

Bipolar Zero Code Error Match

Bipolar zero code error match is the absolute difference in

bipolar zero code error between any two input channels.

2

V₂²+ V₃²+ V₄+ V₅²+ V₆²+ V₇+ V₈²+ V₉²

20log

where:

V

1

Open Circuit Code Error

V₁is the rms amplitude of the fundamental.

V₂to V₉are the rms amplitudes of the second through ninth

harmonics.

Open circuit code error is the ADC output code when there is an

open circuit on the analog input, and a pull-down resistor (R_PD)

connected between the analog input pair of pins. See Figure 59

for more details.

Peak Harmonic or Spurious Noise

Peak harmonic or spurious noise is the ratio of the rms value of the

next largest component in the ADC output spectrum (up to f_S/2,

excluding dc) to the rms value of the fundamental. Normally, the

value of this specification is determined by the largest harmonic

in the spectrum, but for ADCs where the harmonics are buried

in the noise floor, the value is determined by a noise peak.

Positive Full-Scale (PFS) Error

PFS error is the deviation of the actual last code transition from

the ideal last code transition (10 V − 1½ LSB (9.99954), 5 V −

1½ LSB (4.99977), and 2.5 V − 1½ LSB (2.49988)) after the

bipolar zero code error is adjusted out. The positive full-scale

error includes the contribution from the internal reference and

reference buffer.

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but

not the linearity of the converter. The power supply rejection (PSR)

is the maximum change in full-scale transition point due to a

change in power supply voltage from the nominal value. The

PSRR is defined as the ratio of the 100 mV p-p sinewave applied

to the AV_CCsupplies of the ADC frequency, f_S, to the power of

the ADC output at that frequency, f_S.

Positive Full-Scale Error Match

PFS error match is the absolute difference in positive full-scale

error between any two input channels.

Negative Full-Scale (NFS) Error

NFS error is the deviation of the first code transition from the

ideal first code transition (−10 V + ½ LSB (−9.99984), −5 V + ½

LSB (−4.99992), and −2.5 V + ½ LSB (−2.49996)) after the

bipolar zero code error is adjusted out. The negative full-scale

error includes the contribution from the internal reference and

reference buffer.

PSRR (dB) = 20 log (0.1/Pf_S)

where:

Pf_Sis equal to the power at frequency, f_S, coupled on the AV_CC

supply.

Negative Full-Scale Error Match

NFS error match is the absolute difference in negative full-scale

Channel to Channel Isolation

error between any two input channels.

Channel to channel isolation is a measure of the level of

crosstalk between all input channels. It is measured by applying

a full-scale sine wave signal, up to 160 kHz, to all unselected

input channels and then determining the degree to which the

signal attenuates in the selected channel with a 1 kHz sine wave

signal applied (see Figure 42).

Total Unadjusted Error (TUE)

TUE is the maximum deviation of the output code from the

ideal. TUE includes INL errors, bipolar zero code and positive

and negative full-scale errors, and reference errors.

Signal-to-Noise-and-Distortion Ratio (SINAD)

SINAD ratio is the measured ratio of signal-to-noise-and-

distortion at the output of the ADC. The signal is the rms

amplitude of the fundamental. Noise is the sum of all

nonfundamental signals up to half the sampling frequency (f_S/2,

excluding dc).

Rev. 0 | Page 20 of 69

Data Sheet

AD7606B

Phase Delay

Phase Delay Drift

Phase delay drift is the change in phase delay per unit temperature

across the entire operating temperature of the device.

Phase delay is a measure of the absolute time delay between

when an input is sampled by the converter and when the result

associated with that sample is available to be read back from the

ADC, including delay induced by the analog front end of the

device.

Phase Delay Matching

Phase delay matching is the maximum phase delay seen between

any simultaneously sampled pair.

Rev. 0 | Page 21 of 69

AD7606B

Data Sheet

THEORY OF OPERATION

ANALOG FRONT END

The AD7606B is a 16-bit, simultaneous sampling, analog-to-

digital DAS with eight channels. Each channel contains analog

input clamp protection, a PGA, a low-pass filter, and a 16-bit

SAR ADC.

21 V, no current flows in the clamp circuit. For input voltages

that are above 21 V, the AD7606B clamp circuitry turns on.

15

T

= –40°C

= +25°C

= +125°C

A

10

5

Analog Input Ranges

The AD7606B can handle true bipolar, single-ended input

voltages. In hardware mode, the logic level on the RANGE pin

determines either 10 V or 5 V as the analog input range of all

analog input channels, as shown in Table 9.

0

A logic change on the RANGE pin has an immediate effect on

the analog input range. However, there is typically a settling

time of approximately 80 µs in addition to the normal acquisition

time requirement. Changing the RANGE pin during a conversion

is not recommended for fast throughput rate applications.

–5

–10

–15

–30

–20

–10

0

10

20

30

SOURCE VOLTAGE (V)

In software mode, it is possible to configure an individual

analog input range per channel using Address 0x03 through

Address 0x06. The logic level on the RANGE pin is ignored in

software mode.

Figure 44. Input Protection Clamp Profile

It is recommended to place a series resistor on the analog input

channels to limit the current to 10 mA for input voltages

greater than 21 V. In an application where there is a series

resistance (R) on an analog input channel, Vx, it is recommended

to match the resistance (R) with the resistance on VxGND to

eliminate any offset introduced to the system, as shown in

Figure 45. However, in software mode, there is a per channel

system offset calibration that removes the offset of the full

system (see the System Offset Calibration section).

Table 9. Analog Input Range Selection

Range (V) Hardware Mode¹Software Mode²

10

RANGE pin high

RANGE pin low

Not applicable

Address 0x03 through

Address 0x06

Address 0x03 through

Address 0x06

Address 0x03 through

Address 0x06

5

2.5

During normal operation, it is not recommended to leave the

AD7606B in a condition where the analog input is greater than

the input range for extended periods of time because this can

degrade the bipolar zero code error performance. In shutdown

or standby mode, there is no such concern.

¹The same analog input range, 10 V or 5 V, applies to all eight channels.

²The analog input range ( 10 V, 5 V, or 2.5 V) is selected on a per channel

basis using the memory map.

Analog Input Impedance

The analog input impedance of the AD7606B is typically 5 MΩ.

This is a fixed input impedance that does not vary with the

AD7606B sampling frequency. This high analog input

impedance eliminates the need for a driver amplifier in front of

the AD7606B, allowing direct connection to the source or

sensor. Therefore, bipolar supplies can be removed from the

signal chain.

AD7606B

5MΩ

R

Vx

CLAMP

C

VxGND

CLAMP

Figure 45. Input Resistance Matching on the Analog Input of the AD7606B

PGA

Analog Input Clamp Protection

A PGA is provided at each input channel. The gain is configured

depending on the analog input range selected (see Table 9) to

scale the single-ended analog input signal to the ADC fully

differential input range.

Figure 43 shows the analog input circuitry of the AD7606B.

Each analog input of the AD7606B contains clamp protection

circuitry. Despite single, 5 V supply operation, this analog input

clamp protection allows an input overvoltage of up to 21 V.

Input impedance on each input of the PGA is accurately trimmed

to maintain the overall gain error. This trimmed value is then

used when the gain calibration is enabled to compensate for the

gain error introduced by an external series resistor. See the

System Gain Calibration section for more information on the

PGA feature.

5MΩ

Vx

CLAMP

16-BIT

SAR ADC

5MΩ

VxGND

LPF

Figure 43. Analog Input Circuitry for Each Channel

Figure 44 shows the input clamp current vs. the source voltage

characteristic of the clamp circuit. For input voltages of up to

Rev. 0 | Page 22 of 69

Data Sheet

AD7606B

The AD7606B contains an on-chip oscillator that performs the

conversions. The conversion time for all ADC channels is t_CONꢀ

(see Table 3). In software mode, there is an option to apply an

external clock through the CONꢀST pin. Providing a low jitter

external clock improves SNR performance for large oversampling

ratios. See the Digital Filter section and Figure ±5 to Figure 20

for further information.

Analog Input Antialiasing Filter

An analog antialiasing filter is provided on the AD7606B.

Figure 46 and Figure 47 show the frequency response and phase

response, respectively, of the analog antialiasing filter. In the

±±0 ꢀ range, the −3 dB frequency is typically 22.5 kHz.

Connect all unused analog input channels to AGND. The

results for any unused channels are still included in the data

read because all channels are always converted.

ADC Transfer Function

The output coding of the AD7606B is twos complement. The

designed code transitions occur midway between successive

integer LSB values, that is, ±/2 LSB and 3/2 LSB. The LSB size is

FSR/65,536 for the AD7606B. The ideal transfer characteristics for

the AD7606B are shown in Figure 48. The LSB size is dependent on

the analog input range selected, as shown in Table ±0.

Vx

±10V RANGE

±5V RANGE

±2.5V RANGE

100

1k

10k

100k

INPUT FREQUENCY (Hz)

±10V CODE =

±5V CODE =

±2.5V CODE =

× 32,768

10V

Figure 46. Analog Antialiasing Filter Frequency Response

Vx

5V

16

±10V

±5V

±2.5V

Vx

2.5V

14

12

10

8

011...111

011...110

000...001

000...000

111...111

PFS – (NFS)

LSB =

N*

2

6

100...010

100...001

100...000

4

NFS + 1/2LSB 0v – 1/2LSB PFS – 3/2LSB

AV = 5V, V

f_SAMPLE= 800kSPS

T = 25°C

= 3.3V

ANALOG INPUT

CC

DRIVE

2

Figure 48. Ideal Transfer Characteristics

0

100

1k

10k

100k

Table 10. Input Voltage Ranges

Range (V) PFS (V) Midscale (V) NFS (V)

INPUT FREQUENCY (Hz)

LSB (μV)

305

±52

Figure 47. Analog Antialiasing Filter Phase Response

±±0

±5

±2.5

ꢀ±0

ꢀ5

ꢀ2.5

0

−±0

−5

−2.5

SAR ADC

The AD7606B allows the ADC to accurately acquire an input

signal of full-scale amplitude to ±6-bit resolution. All eight SAR

ADCs sample the respective inputs simultaneously on the rising

edge of the CONꢀST signal.

76

REFERENCE

The AD7606B contains an on-chip, 2.5 ꢀ, band gap reference.

The REFIN/REFOUT pin allows either

The BUSY signal indicates when conversions are in progress.

Therefore, when the rising edge of the CONꢀST signal is applied,

the BUSY pin goes logic high and transitions low at the end of

the entire conversion process. The end of the conversion process

across all eight channels is indicated by the falling edge of the

BUSY signal. When the BUSY signal edge falls, the acquisition

time for the next set of conversions begins. The rising edge of the

CONꢀST signal has no effect while the BUSY signal is high.



Access to the internal 2.5 ꢀ reference, if the

REF SELECT pin is tied to logic high.



Application of an external reference of 2.5 ꢀ, if the REF

SELECT pin is tied to logic low.

Table 11. Reference Configuration

REF SELECT Pin Reference Selected

New data can be read from the output register via the parallel or

serial interface after the BUSY output goes low. Alternatively,

data from the previous conversion can be read while the BUSY pin

is high, as explained in the Reading During Conversion section.

Logic High

Logic Low

Internal reference enabled

Internal reference disabled; an external 2.5 V

reference voltage must be applied to the

REFIN/REFOUT pin

Rev. 0 | Page 23 of 69

AD7606B

Data Sheet

V

DRIVE

The AD7606B contains a reference buffer configured to gain the

reference voltage up to approximately 4.4 V, as shown in Figure 49.

The 4.4 V buffered reference is the reference used by the SAR

ADC, as shown in Figure 49. After a reset, the AD7606B operates

in the reference mode selected by the REF SELECT pin. The

REFCAPA and REFCAPB pins must be shorted together

externally, and a ceramic capacitor of 10 μF must be applied to

the REFGND pin to ensure that the reference buffer is in closed-

loop operation. A 10 µF ceramic capacitor is required on the

REFIN/REFOUT pin.

AD7606B

REF SELECT

AD7606B

REF SELECT

REFIN/REFOUT

+

10µF

100nF

Figure 51. Internal Reference Driving Multiple AD7606B REFIN/REFOUT Pins

OPERATION MODES

The AD7606B can be operated in hardware or software mode

by controlling the OSx pins (Pin 3, Pin 4, and Pin 5), described

in Table 12.

When the AD7606B is configured in external reference mode,

the REFIN/REFOUT pin is a high input impedance pin.

REFIN/REFOUT

In hardware mode, the AD7606B is configured depending on

SAR

the logic level on the RANGE, OSx, or

pins.

STBY

REFCAPA

BUF

In software mode, that is, when all three OSx pins are connected

to logic high level, the AD7606B is configured by the

10µF

REFCAPB

corresponding registers accessed via the serial or parallel interface.

Additional features are available, as described in Table 13.

2.5V

REF

The reference and the data interface is selected using the

Figure 49. Reference Circuitry

REF SELECT and

/SER SEL pins, in both hardware and

PAR

software modes.

Using Multiple AD7606B Devices

For applications using multiple AD7606B devices, the following

configurations are recommended, depending on the application

requirements.

Table 12. Oversampling Pin Decoding

OSx Pins

AD7606B

000

No OS

External Reference Mode

001

2

010

011

100

101

110

111

4

8

16

32

One external reference can drive the REFIN/REFOUT pins of

all AD7606B devices (see Figure 50). In this configuration,

decouple each REFIN/REFOUT pin of the AD7606B with at

least a 100 nF decoupling capacitor.

64

AD7606B

Enters software mode

REF SELECT

REFIN/REFOUT

100nF

REF

1µF

Figure 50. Single External Reference Driving Multiple AD7606B

REFIN/REFOUT Pins

Internal Reference Mode

One AD7606B device, configured to operate in internal

reference mode, can drive the remaining AD7606B devices,

which are configured to operate in external reference mode (see

Figure 51). Decouple the REFIN/REFOUT pin of the AD7606B,

configured in internal reference mode, using a 10 µF ceramic

decoupling capacitor. The other AD7606B devices, configured in

external reference mode, must use at least a 100 nF decoupling

capacitor on their REFIN/REFOUT pins.

Rev. 0 | Page 24 of 69

Data Sheet

AD7606B

Table 13. Functionality Matrix

Parameter

Analog Input Range¹

System Gain, Phase, and Offset Calibration

OSR

Analog Input Open Circuit Detection

Serial Data Output Lines

Diagnostics

Hardware Mode

10 V or 5 V²

Not accessible

From no OS to OSR = 64

Not accessible

2

Software Mode

10 V, 5 V, or 2.5 V³

Available³

From no OS to OSR = 256

Available³

Selectable: 1, 2, or 4

Available

Standby, shutdown, and autostandby

Not accessible

Standby and shutdown

Power-Down Modes

¹See Table 9 for the analog input range selection.

²Same input range configured in all input channels.

³On a per channel basis.

Rev. 0 | Page 25 of 69

AD7606B

Data Sheet

Table 14. Power-Down Mode Selection, Hardware Mode

Reset Functionality

STBY Pin

Power Mode

Normal Mode

Standby

RANGE Pin

The AD7606B has two reset modes: full or partial. The reset

mode selected is dependent on the length of the reset high

pulse. A partial reset requires the RESET pin to be held high

between 55 ns and 2 μs. After 50 ns from the release of the

RESET pin (t_{DEVICE_SETUP}, partial reset), the device is fully functional

and a conversion can be initiated. A full reset requires the

RESET pin to be held high for a minimum of 3 µs. After 253 μs

(t_{DEVICE_SETUP}, full reset) from the release of the RESET pin, the

device is completely reconfigured and a conversion can be

initiated.

1

0

X¹

1

0

Shutdown

¹X = don’t care.

In software mode, the power-down mode is selected through

the OPERATION_MODE bits on the CONFIG register

(Address 0x02, Bits[1:0]) within the memory map. There is an

extra power-down mode available in software mode called

autostandby mode.

A partial reset reinitializes the following modules:

Table 15. Power-Down Mode Selection, Software Mode,

Through CONFIG Register (Address 0x02)

Operation Mode Address 0x02, Bit 1 Address 0x02, Bit 0

•

Digital filter.

SPI and parallel, resetting to ADC mode.

SAR ADCs.

CRC logic.

Normal

Standby

Autostandby

Shutdown

0

1

0

1

0

1

After the partial reset, the RESET_DETECT bit of the status

register asserts (Address 0x01, Bit 7).The current conversion

result is discarded after the completion of a partial reset. The

partial reset does not affect the register values programmed in

software mode or the latches that store the user configuration in

both hardware and software modes.

When the AD7606B is placed in shutdown mode, all circuitry is

powered down and the current consumption reduces to 5 µA,

maximum. The power-up time is approximately 10 ms. When

the AD7606B is powered up from shutdown mode, a full reset

must be applied to the AD7606B after the required power-up

time elapses.

A full reset returns the device to the default power-on state, the

RESET_DETECT bit of the status register asserts (Address 0x01,

Bit 7), and the current conversion result is discarded. The

following features, in addition to those listed previously, are

configured when the AD7606B is released from full reset:

When the AD7606B is placed in standby mode, all the PGAs

and all the SAR ADCs enter a low power mode, such that the

overall current consumption reduces to 4.5 mA, maximum. No

reset is required after exiting standby mode.

•

Hardware mode or software mode.

Interface type (serial or parallel).

When the AD7606B is placed in autostandby mode, available

only in software mode the device automatically enters standby

mode on the BUSY signal falling edge. The AD7606B exits

standby mode automatically on the CONVST signal rising edge.

Therefore, the CONVST signal low pulse time is longer than

Power-Down Modes

In hardware mode, two power-down modes are available on the

STBY

AD7606B: standby mode and shutdown mode. The

controls whether the AD7606B is in normal mode or in one of the

STBY

t

_{WAKE_UP}(standby mode) = 1 μs.

two power-down modes, as shown in Table 14. If the

CONVST

is low, the power-down mode is selected by the state of the

RANGE pin.

BUSY

STANDBY

NORMAL

t_{WAKE_UP}

STANDBY

POWER MODE

Figure 52. Autostandby Mode Operation

Rev. 0 | Page 26 of 69

Data Sheet

AD7606B

DIGITAL FILTER

The AD7606B contains an optional digital averaging filter that

can be enabled in slower throughput rate applications that require

higher SNR or dynamic range.

averaging of multiple samples leads to an improvement in SNR

performance, at the expense of reducing the maximum throughput

rate. When the oversampling function is turned on, the BUSY

signal high time (t_CONV) extends, as shown in Table 3. Table 16

shows the trade-off in SNR vs. bandwidth and throughput for

the 10 V, 5 V, and 2.5 V ranges.

In hardware mode, the oversampling ratio of the digital filter is

controlled using the oversampling pins, OSx, as shown in Table 12.

The OSx pins are latched on the falling edge of the BUSY signal.

t_CYCLE

In software mode, that is, if all OSx pins are tied to logic high,

the oversampling ratio is selected through the oversampling

register (Address 0x08). Two additional oversampling ratios

(OS × 128 and OS × 256) are available in software mode.

CONVST

OS CLOCK

BUSY

t_CONV

CS

RD

In oversampling mode, the ADC takes the first sample for each

channel on the rising edge of the CONVST signal. After

converting the first sample, the subsequent samples are taken by

the internally generated sampling signal, as shown in Figure 53.

Alternatively, this sampling signal can be applied externally as

described in the External Oversampling Clock section.

DATA:

DB0 TO DB15

Figure 53. Oversampling by 8 Example, Read After Conversion, Parallel

Interface, OS Clock Internally Generated Sampling Signal

Figure 53 shows that the conversion time (t_CONV) extends when

oversampling is turned on. The throughput rate (1/t_CYCLE) must be

reduced to accommodate the longer conversion time and to allow

the read operation to occur. To achieve the fastest throughput rate

possible when oversampling is turned on, the read can be

performed during the BUSY signal high time as explained in the

Reading During Conversion section.

For example, if oversampling by eight is configured, eight

samples are taken, averaged, and the result is provided on the

output. A CONVST signal rising edge triggers the first sample,

and the remaining seven samples are taken with an internally

generated sampling signal. Consequently, turning on the

Table 16. Oversampling Performance

10 V Range

5 V Range

2.5 V Range

3 dB

OS

Ratio

Input

Frequency (Hz)

3 dB

Maximum Throughput

(kSPS)

SNR (dB) BW (kHz)

SNR (dB)

BW (kHz)

No OS

2

4

8

16

32

64

128¹

256¹

1000

130

50

89.5

91

92.2

93

93.5

95.4

96.3

97.1

97.6

23.0

22.7

22.0

20.0

15.4

9.7

5.3

2.7

1.4

88.5

89.9

90.8

91.5

92

93.7

95

95.9

96.8

13.9

13.8

13.6

13.0

11.4

8.4

5.0

2.7

1.4

86

87.2

88

88.4

89

90.4

91.8

93.3

94.7

11.6

11.5

11.4

11.1

10.0

7.7

4.9

2.7

1.4

800

400

200

100

50

25

12.5

6.25

3.125

¹Only available in software mode.

Rev. 0 | Page 27 of 69

AD7606B

Data Sheet

PADDING OVERSAMPLING

EXTERNAL OVERSAMPLING CLOCK

As shown in Figure 53, an internally generated clock triggers

the samples to be averaged, and then the ADC remains idle

until the following CONVST signal rising edge. In software

mode, through the oversampling register (Address 0x08), the

internal clock (OS clock) frequency can be changed such that idle

time is minimized, that is sampling instants are equally spaced, as

shown in Figure 54.

In software mode, there is an option to apply an external clock

through the CONVST pin when oversampling mode is enabled.

Providing a low jitter external clock improves SNR performance

for large oversampling ratios. By applying an external clock, the

input is sampled at regular time intervals, which is optimum for

antialiasing performance.

To enable the external oversampling clock, Bit 5 in the CONFIG

register (Address 0x02, Bit 5) must be set. Then, the throughput

rate is

t_CYCLE

CONVST

OS CLOCK

1

BUSY

Throughput =

t_CONV

t_CNVST×OSR

Figure 54. Oversampling by 8 Example, Oversampling Padding Enabled

That is, the sampling signal is provided externally through the

CONVST pin, and every OSR number of clocks, an output is

averaged and provided, as shown in Figure 55. This feature is

available using either the parallel interface or the serial interface.

Table 17. OS_PAD Bit Decoding

OS_PAD (Address 0x08, Bits[7:5]) OS Clock Frequency (kHz)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

800

753

711

673.5

640

609.5

582

556.5

533

512

492.5

474

457

441.5

426.5

413

t

CNVST

CONVST

BUSY

CS

RD

DB0 TO DB15

Figure 55. External Oversampling Clock Applied on the CONVST Pin (OSR = 4); Parallel Interface

Rev. 0 | Page 28 of 69

Data Sheet

AD7606B

SYSTEM CALIBRATION FEATURES

The following system calibration features are available in

software mode by writing to corresponding registers in the

memory map:

AD7606B

5MΩ

ANALOG

INPUT

SIGNAL

R

FILTER

Vx

C

5MΩ

VxGND

R

FILTER

•

Phase calibration.

Gain calibration.

Offset calibration.

Analog Input open circuit detection.

Figure 57. System Gain Error

For example, if a 27 kΩ resistor is placed in series to the analog

input of Channel 5, the resistor generates −170 LSB positive

full-scale error on the system (at 10 V range), as shown in

Figure 58. In software mode, this error is eliminated by writing

27d to the CH5_GAIN register (Address 0x0D).

0

SYSTEM PHASE CALIBRATION

When using an external filter, as shown in Figure 57, any

mismatch on the discrete components, or in the sensor used,

can cause phase mismatch between channels. This phase mismatch

can be compensated for in software mode, on a per channel

basis, by delaying the sampling instant on individual channels.

–100

–200

–300

–400

The sampling instant on any particular channel can be delayed

with regard to the CONVST signal rising edge, with a resolution of

1.25 μs, and up to 318.75 μs, by writing to the corresponding

CHx_PHASE register (Address 0x19 through Address 0x20).

For example, if the CH4_PHASE register (Address 0x1C) is

written with 10d, Channel 4 is effectively sampled 12.5 μs

(t_{PHASE_REG}) after the CONVST signal rising edge, as shown in

Figure 56.

SYSTEM GAIN CALIBRATION OFF

SYSTEM GAIN CALIBRATION ON

–500

0

10

20

30

40

(kΩ)

50

60

R

FILTER

INPUT V1

INPUT V4

Figure 58. System Gain Calibration with and Without Calibration

SYSTEM OFFSET CALIBRATION

CONVST

INTERNAL

CONVST CH1

A potential offset on the sensor, or any offset caused by a

mismatch between the R_FILTERpair placed on a particular

channel (as described in the Analog Front End section), can be

compensated in software mode, on a per channel basis. The

CHx_OFFSET registers (Address 0x11 through Address 0x18)

allow the ability to add or subtract up to 128 LSB from the ADC

code automatically, with a resolution of 1 LSB, as shown in

Table 18.

t_{PHASE_REG}

t_CONV

INTERNAL

CONVST CH4

BUSY

V1 CODE

V4 CODE

Figure 56. System Phase Calibration Functionality

The BUSY signal high time equals t_CONVplus t_{PHASE_REG}, as shown in

Figure 56. In the previously explained example and Figure 56, if

only CH4_PHASE_REGISTER is programmed, t_CONVincreases

by 12.5 μs. Therefore, this scenario must be taken into account

when running at higher throughput rates.

For example, if the signal connected to Channel 3 has a 9 mV

offset, and the analog input range is set to the 10 V range

(where LSB size = 305 μV) to compensate for this offset,

program −30 LSB to the corresponding register. Writing 128d −

30d = 0x80 − 0x1E = 0x62 to the CH3_OFFSET register

(Address 0x13) removes such offset.

SYSTEM GAIN CALIBRATION

Using an external R_FILTER, as shown in Figure 57, generates a

system gain error. This gain error can be compensated for in

software mode, on a per channel basis, by writing the series

resistor value used on the corresponding register, Address 0x09

through Address 0x10. These registers can compensate up to

65 kΩ series resistors, with a resolution of 1024 Ω.

Table 18. CHx_OFFSET Register Bit Decoding

CHx_OFFSET Register

Offset Calibration (LSB)

0x00

0x45

0x80 (Default)

0x83

−128

−59

0

+3

0xFF

+127

Rev. 0 | Page 29 of 69

AD7606B

Data Sheet

changes the PGA common-mode voltage, checks the ADC

ANALOG INPUT OPEN CIRCUIT DETECTION

output, and returns to the initial common-mode voltage, as

shown in Figure 61. If the ADC code changes in any channel

with the PGA common-mode change, this implies that there is

no input signal connected to that analog input, and the

corresponding flag asserts within the OPEN_DETECTED

register (Address 0x24). Each channel can be individually

enabled or disabled through the OPEN_DETECT_

The AD7606B has an analog input open circuit detection

feature available in software mode. To use this feature, R_PDmust

be placed as shown in Figure 59. If the analog input is

disconnected, for example, if a switch opens in Figure 59, the

source impedance changes from R_Sto R_PD, as long as R_S< R_PD. It

is recommended to use R_PD= 50 kΩ so that the AD7606B can

detect changes in the source impedance by internally switching

the PGA common-mode voltage. Analog input open circuit

detection operates in manual mode or in automatic mode.

ENABLE register (Address 0x23).

START

CONVERSION

AD7606B

R

FILTER

5MΩ

Vx+

NO

0 < ADC CODE < 350 LSB

i = 0

C

SAR

ADC

FILTER

Vx–

R

S

PD

R

FILTER

5MΩ

YES

N = NUMBER OF

NO

Figure 59. Analog Front End with R_PD

CONSECUTIVE REPEATED

i = N?

(WITHIN 10 LSB)

i = i + 1

ADC OUTPUT CODE

Manual Mode

YES; SET

COMMON MODE HIGH

In manual mode, enabled by writing 0x01 to OPEN_DETECT_

QUEUE (Address 0x2C), each PGA common-mode voltage is

controlled by the corresponding CHx_OPEN_DETECT_EN bit

on the OPEN_DETECT_ENABLE register (Address 0x23).

Setting this bit high shifts up the PGA common-mode voltage.

If there is an open circuit on the analog input, the ADC output

changes proportionally to the R_PDresistor, as shown in Figure 60. If

there is not an open circuit, any change on the PGA common-

mode voltage has no effect on the ADC output.

NO

ΔADC CODE > 20 LSB

i = 0

YES; SET

COMMON MODE LOW

NO

ADC CODE BACK

TO ORIGINAL?

i = 0

120

10V

5V

2.5V

100

YES

ERROR FLAG

80

60

40

20

0

Figure 61. Automatic Analog Input Open Circuit Detect Flowchart

If no oversampling is used, the recommended minimum

number of conversions to be programmed for the AD7606B to

automatically detect an open circuit on the analog input is

OPEN _ DETECT _QUEUE =

10 × f_SAMPLE

R

+ 2 × R_FILTER×C

(

)

PD FILTER

However, when oversampling mode is enabled, the

recommended minimum number of conversions to use is

0

20

40

60

80

100

R

(kΩ)

PD

OPEN _ DETECT _QUEUE =

Figure 60. Open Circuit Code Error Increment, Dependent of R_PD

1 + f

× 2 R + 2 × R_FILTER×C

×OSR

FILTER

(

)

(

)

SAMPLE

PD

Automatic Mode

Automatic mode is enabled by writing any value greater than

0x01 to the OPEN_DETECT_QUEUE register (Address 0x2C), as

shown in Table 19. If the AD7606B detects that the ADC reported a

number (specified in the OPEN_DETECT_QUEUE register) of

consecutive unchanged conversions, the analog input open circuit

detection algorithm is performed internally and automatically.

The analog input open circuit detection algorithm automatically

Rev. 0 | Page 30 of 69

Data Sheet

AD7606B

Table 19. Analog Input Open Circuit Detect Mode Selection and Register Functionality

OPEN_DETECT_QUEUE

(Address 0x2C)

0x00 (Default)

0x01

Open Detect Mode

Disabled

Manual mode

OPEN_DETECT_ENABLE (Address 0x23)

Not applicable

Sets common-mode voltage high or low, on a

per channel basis

0x02 to 0xFF

Automatic; OPEN_DETECT_QUEUE is the number of

consecutive conversions before asserting any CHx_OPENED flag

Enables or disables automatic analog input

open circuit detection on a per channel basis

Rev. 0 | Page 31 of 69

AD7606B

Data Sheet

DIGITAL INTERFACE

The AD7606B provides two interface options: a parallel interface

and a high speed serial interface. The required interface mode is

SOFTWARE MODE

In software mode, which is active only when all three

oversampling pins are tied high, both ADC read mode and

register mode are available. ADC data can be read from the

AD7606B, and registers can also be read from and written to

PAR

selected via the

/SER SEL pin.

Table 20. Interface Mode Selection

PAR/SER SEL

Interface Mode

CS RD

the AD7606B via the parallel data bus with standard

WR

,

0

1

Parallel interface mode

Serial interface mode

CS

,

and

signals or via the serial interface with standard

SCLK, SDI, and D_OUTA lines.

Operation of the interface modes is discussed in the following

sections.

See the Parallel Register Mode (Writing Register Data) section

and the Parallel Register Mode (Reading Register Data) section

for more details on how register mode operates.

HARDWARE MODE

In hardware mode, only ADC mode is available. ADC data can

be read from the AD7606B via the parallel data bus with standard

Pin functions differ depending on the interface selected

(parallel or serial) and the operation mode (hardware or

software), as shown in Table 21 and Table 22.

CS

RD

CS

and

SCLK, and two D_OUTx signals.

signals or via the serial interface with standard ,

See the Reading Conversion Results (Parallel ADC Mode) section

and the Reading Conversion Results (Serial ADC Mode) section

for more details on how ADC read mode operates.

Table 21. Data Interface Pin Function per Mode of Operation (Parallel Interface)

Software Mode

Register Mode

Pin Name

Pin No.

16 to 22

24

Hardware Mode

DB0 to DB6

ADC Mode

DB0 to DB6

Register data

Register data (MSB)

ADD0

DB7/D_OUT

DB8/D_OUT

DB9/D_OUT

A

B

C

DB7

DB8

25

27

DB9

ADD1

DB10/D_OUT

DB11/SDI

D

28

DB10

ADD2

29

DB11

ADD3

DB12 to DB14

DB15

30 to 32

33

DB12 to DB14

DB15

ADD4 to ADD6

R/W

Table 22. Data Interface Pin Function per Mode of Operation (Serial Interface)

Software Mode

Register Mode

Pin Name

Pin No.

16 to 22

24

Hardware Mode

N/A¹

ADC Mode

DB0 to DB6

N/A

DB7/D_OUT

DB8/D_OUT

DB9/D_OUT

A

B

C

D_OUT

N/A

A

B

D_OUT

A

D_OUTA

25

D_OUTB²

D_OUTC³

D_OUTD³

Unused

SDI

27

DB10/D_OUT

DB11/SDI

D

28

29

DB12 to DB14

DB15

30 to 32

33

N/A

¹N/A means not applicable. Tie all N/A pins to AGND.

²Only used if 2SDO or 4SDO mode is selected on the CONFIG register, otherwise leave unconnected.

³Only used if 4SDO mode is selected on the CONFIG register, otherwise leave unconnected.

Rev. 0 | Page 32 of 69

Data Sheet

AD7606B

available on the output data bus. The FRSTDATA pin returns to a

RD

PARALLEL INTERFACE

To read ADC data or to read/write the register content over the

logic low following the next falling edge of

.

PAR

parallel interface, tie the

/SER SEL pin low.

Reading During Conversion

Data can be read from the AD7606B while the BUSY pin is high

and the conversions are in progress. This operation has little

effect on the performance of the converter, and it allows a faster

throughput rate to be achieved. Data can be read from the

AD7606B at any time other than on the falling edge of the

BUSY signal because this is when the output data registers are

updated with the new conversion data. Any data read while the

BUSY signal is high must be completed before the falling edge

of the BUSY signal.

AD7606B

INTERRUPT

BUSY 14

13

12

CS

RD/SCLK

DIGITAL

HOST

WR 10

DB[33:24]

DB[22:16]

DB[15:0]

Figure 62. AD7606B Interface Diagram—One AD7606B Using the Parallel

CS RD

Bus, with and

Shorted Together

Parallel ADC Mode with CRC Enabled

In software mode, the parallel interface supports reading the

ADC data with the CRC appended, when enabled through the

INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is

16 bits, and it is clocked out after reading all eight channel

conversions, as shown in Figure 65. The CRC calculation includes

all data on the DBx pins: data, status (when appended), and zeros.

See the Diagnostics section for more details on the CRC.

CS

The rising edge of the

the falling edge of the

high impedance state.

input signal three-states the bus, and

input signal takes the bus out of the

is the control signal that enables the

data lines and it is the function that allows multiple AD7606B

devices to share the same parallel data bus.

Reading Conversion Results (Parallel ADC Mode)

RD

The falling edge of the

conversion results register. Applying a sequence of

RD

pin reads data from the output

Parallel ADC Mode with Status Enabled

RD

pulses to

pin clocks the conversion results out from each channel

In software mode, the 8-bit status header is enabled (see Table 24)

by setting Bit 6 in the CONFIG register (Address 0x02, Bit 6),

and each channel then takes two frames of data:

the

to the parallel bus, [DB15:DB0], in ascending order, from V1 to

V8, as shown in Figure 63.



The first frame clocks the ADC data out normally through

DBx.

CS

RD

signal

The

signal can be permanently tied low, and the

can access the conversion results, as shown in Figure 3. A read

operation of new data can take place after the BUSY signal goes

low (see Figure 2). Alternatively, a read operation of data from

the previous conversion process can take place while the

BUSY pin is high.



The second frame clocks out the status header of the

channel on DB15 to DB8, DB15 being the MSB and DB8

the LSB, while the DB7 to DB0 pins clock out zeros.

This sequence is shown in Figure 64. Table 24 explains the

status header content and describes each bit.

When there is only one AD7606B in a system and it does not

share the parallel bus, data can be read using one control signal

from the digital host. The

together, as shown in Figure 4. In this case, the falling edge of

CS RD

signals bring the data bus out of three-state and

Table 23. CH.ID Bits Decoding in Status Header

CS

RD

and

signals can be tied

CH.ID2

CH.ID1

CH.ID0

Channel Number

Channel 1 (V1)

Channel 2 (V2)

Channel 3 (V3)

Channel 4 (V4)

Channel 5 (V5)

Channel 6 (V6)

Channel 7 (V7)

Channel 8 (V8)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

the

and

clocks out the data.

The FRSTDATA output signal indicates when the first channel,

CS

V1, is being read back, as shown in Figure 4. When the

is high, the FRSTDATA output pin is in three-state. The falling

CS

input

edge of

falling edge of the

takes the FRSTDATA pin out of three-state. The

RD

signal corresponding to the result of V1 sets

the FRSTDATA pin high, indicating that the result from V1 is

Table 24. Status Header, Parallel Interface

Bit Details

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Bit Name

RESET_DETECT DIGITAL_ERROR

OPEN_DETECTED

AIN_OV_DIAG_ERR

AIN_UV_DIAG_ERR

CH.ID 2 CH.ID 1 CH.ID 0

Channel ID (see Table 23)

Bit Description¹Reset detected Error flag on

Address 0x22

The analog input

of this channel is

open

Overvoltage

detected on this

channel

Undervoltage

detected on this

channel

¹See the Diagnostics section for more information.

Rev. 0 | Page 33 of 69

AD7606B

Data Sheet

CONVST

BUSY

CS

RD

DB0 TO DB15

V1

V2

V3

V4

V5

V6

V7

V8

FRSTDATA

Figure 63. Parallel Interface, ADC Read Mode

CONVST

BUSY

CS

RD

DB0 TO

DB15

DB0 TO

DB7

V1[15:8]

V1[7:0]

STATUS_CH1

V2[15:8]

V2[7:0]

STATUS_CH2

V7[15:8]

V7[7:0]

STATUS_CH7

V8[15:8]

V8[7:0]

STATUS_CH8

Figure 64. Parallel Interface, ADC Read Mode with Status Header Enabled

CONVST

BUSY

CS

RD

DB0 TO

DB15

CRC

V1

V2

V3

V4

V5

V6

V7

V8

Figure 65. Parallel Interface, ADC Read Mode with CRC Enabled

Parallel Register Mode (Reading Register Data)

In software mode, all the registers in Table 31 can be read over

the parallel interface. [DB15:DB0] leave a high impedance state

To revert to ADC read mode, write to Address 0x00, as shown

in the Parallel Register Mode (Writing Register Data) section.

No ADC data can be read while the device is in register mode.

CS

RD

when both the

signal and

signal are logic low for reading

CS WR

Parallel Register Mode (Writing Register Data)

register content, or when both the

signal and

signal are

In software mode, all the R/W registers in Table 31 can be written

to over the parallel interface. To write a sequence of registers,

exit ADC read mode (default mode) by reading any register on the

memory map. A register write command is performed by a single

logic low for writing register address and/or register content.

A register read is performed through two frames: first, a read

command is sent to the AD7606B and second, the AD7606B

clocks out the register content. The format for a register read

command is shown in Figure 66. On the first frame,

CS

WR

frame, via the parallel bus (DB[15:0]), signal, and

signal.

The format for a write command is shown in Figure 66. The

format of a write command, as shown in Figure 66, is structured as

follows:



Bit DB15 must be set to 1 to select a read command. The

read command places the AD7606B in register mode.

Bits DB[14:8] must contain the register address.

The subsequent eight bits, DB[7:0], are ignored.



Bit DB15 must be set to 0 to select a write command.

Bits DB[14:8] contain the register address.

The subsequent eight bits, DB[7:0], contain the data to be

written to the selected register.

The register address is latched on the AD7606B on the rising

WR

edge of the

signal. The register content can then be read

RD

WR

pin. To

from the latched register by bringing the

following frame, as follows:

line low on the

Data is latched onto the device on the rising edge of the

revert to ADC read mode, write to Address 0x00. No ADC data

can be read while the device is in register mode.



Bit DB15 is pulled to 0 by the AD7606B.

Bits DB[14:8] provide the register address being read.

The subsequent eight bits, DB[7:0], provide the register

content.

Rev. 0 | Page 34 of 69

Data Sheet

AD7606B

CS

RD

WR

R/W = 1

R/W = 0

DB15

DB8 TO

DB14

REG. ADDRESS

ADDRESS = 0x00

DB0 TO

DB7

DON’T CARE

REGISTER DATA

DON’T CARE

MODE

ADC READ MODE

REGISTER MODE

ADC READ MODE

Figure 66. Parallel Interface Register Read Operation, Followed by a Write Operation

CS

FRSTDATA

SCLK

D

A

B

C

D

V1

V2

V3

V4

V5

V6

V7

V8

OUT

Figure 67. Serial Interface ADC Reading, One D_OUTx Line

SERIAL INTERFACE

In hardware mode, only the 2 D_OUTx lines option is available.

However, all channels can be read from D_OUTA by providing

eight 16-bit SPI frames between two CONVST pulses.

To read ADC data or to read/write the registers content over the

PAR

serial interface, tie the

/SER SEL pin high.

CNVST

AD7606B

INTERRUPT

BUSY 14

CS 13

CS

SCLK

12

29

24

25

27

28

RD/SCLK

DB11/SDI

D

A

B

C

D

V1

V5

V2

V6

V3

V7

V4

V8

OUT

DIGITAL

HOST

DB7/D

DB8/D

DB9/D

DB10/D

A

B

C

D

OUT

Figure 69. Serial Interface ADC Reading, Two D_OUTx Lines

CS

Figure 68. AD7606B Interface Diagram—One AD7606B Using the Serial

Interface with Four D_OUTx Lines

SCLK

Reading Conversion Results (Serial ADC Mode)

D

A

B

V1

V3

V2

V4

OUT

The AD7606B has four serial data output pins: D_OUTA, D_OUTB,

D

OUT

D

_OUTC, and D_OUTD. In software mode, data can be read back

D

C

D

V5

V7

V6

V8

from the AD7606B using either one (see Figure 68), two (see

Figure 69), or four D_OUTx lines (see Figure 70), depending on the

configuration set in the CONFIG register.

OUT

Figure 70. Serial Interface ADC Reading, Four D_OUTx Lines

Table 25. D_OUTx Format Selection, Using the CONFIG

Register (Address 0x02)

CS

The

falling edge takes the data output lines, D_OUTA to D_OUTD,

out of three-state and clocks out the MSB of the conversion result.

D_OUTx Format

Address 0x02, Bit 4

Address 0x02, Bit 3

CS

In 3-wire mode ( tied low), instead of clocking out the MSB,

the falling edge of the BUSY signal clocks out the MSB. The rising

edge of the SCLK signal clocks all the subsequent data bits on the

serial data outputs, D_OUTA to D_OUTD, as shown in Figure 6. The

input can be held low for the entire serial read operation, or it can

be pulsed to frame each channel read of 16 SCLK cycles (see

1 D_OUT

2 D_OUT

4 D_OUT

1 D_OUT

x

0

1

0

1

0

1

CS

Rev. 0 | Page 35 of 69

AD7606B

Data Sheet

CS

line sets the FRSTDATA pin high when the result from V1 is

available on D_OUTA.

Figure 69). However, if

is pulsed during a channel

conversion result transmission, the channel that was interrupted

retransmits on the next frame, completely starting from the

MSB.

If SDI is tied low or high, nothing is clocked to the AD7606B.

Therefore, the device remains clocking out conversion results.

When using the AD7606B in 3-wire mode, keep the SDI at a

high level. While in ADC read mode, single-write operations

can be performed, as shown in Figure 71. For writing a

sequence of registers, switch to register mode, as described in

the Serial Register Mode (Writing Register Data) section.

Data can also be clocked out using only the D_OUTA pin, as

shown in Figure 67. For the AD7606B to access all eight

conversion results on one D_OUTx line, a total of 128 SCLK cycles

is required. In hardware mode, these 128 SCLK cycles must be

CS

framed on groups of 16 SCLK cycles by the

signal. The

disadvantage of using just one D_OUTx line is that the throughput

rate is reduced if reading occurs after conversion. Leave the

unused D_OUTx lines unconnected in serial mode.

Reading During Conversion

Data can be read from the AD7606B while the BUSY signal is

high and the conversions are in progress. This operation has

little effect on the performance of the converter, and it allows a

faster throughput rate to be achieved. Data can be read from the

AD7606B at any time other than on the falling edge of the

BUSY signal because this is when the output data registers are

updated with the new conversion data. Any data read while the

BUSY signal is high must be completed before falling edge of

the BUSY signal.

Figure 70 shows a read of eight simultaneous conversion results

using four D_OUTx lines on the AD7606B, available in software

mode. In this case, a 32 SCLK transfer accesses data from the

CS

AD7606B, and

is either held low to frame the entire 32 SCLK

cycles or is pulsed between two 16-bit frames. This mode is only

available in software mode, and it is configured using the

CONFIG register (Address 0x02).

Figure 6 shows the timing diagram for reading one channel of

Serial ADC Mode, with CRC Enabled

CS

data, framed by the

signal, from the AD7606B in serial

In software mode, the CRC can be enabled by writing to the

register map. In this case, the CRC is appended on each D_OUTx

line after the last channel is clocked out as shown in Figure 78.

See the Interface CRC Checksum section for more information

on how the CRC is calculated.

mode. The SCLK input signal provides the clock source for the

serial read operation. The

from the AD7606B.

CS

signal goes low to access the data

The FRSTDATA output signal indicates when the first channel,

CS

V1, is being read back. When the input is high, the FRSTDATA

Serial ADC Mode, with Status Enabled

output pin is in three-state. In serial mode, the falling edge of the

In software mode, the 8-bit status header can be turned on

when using the serial interface, so that it is appended after each

16-bit data conversion, extending the frame size to 24 bits per

channel, as shown in Figure 71.

CS

signal takes the FRSTDATA pin out of three-state and sets

the FRSTDATA pin high if the BUSY line is already deasserted,

indicating that the result from V1 is available on the D_OUTA

output data line. The FRSTDATA output returns to a logic low

th

CS

following the 16 SCLK falling edge. If the

pin is tied

permanently low (3-wire mode), the falling edge of the BUSY

CS

1

2

3

4

5

6

7

8

9

16

24

SCLK

D

x

ADC DATA

STATUS HEADER

OUT

CS

Figure 71. Serial Interface, ADC Mode, Status On

SCLK

SDI

READ COMMAND

R/W COMMAND

WRITE COMMAND

ADDRESS

0x00

REGISTER

N

REGISTER

N + 1

REGISTER

N + 2

REGISTER

N

REGISTER

N + 2

D

A

ADC DATA

ADC MODE

OUT

N + 1

D

B TO

D

OUT

D

OUT

MODE

ADC MODE

REGISTER MODE

Figure 72. AD7606B Register Mode

Rev. 0 | Page 36 of 69

Data Sheet

AD7606B

Table 26. Status Header, Serial Interface

Bit Details

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Bit Name

Bit Description¹

RESET_DETECT DIGITAL_ERROR

OPEN_DETECTED

AIN_OV_DIAG_ERR

AIN_UV_DIAG_ERR

CH.ID 2 CH.ID 1 CH.ID 0

Channel ID (see Table 23)

Reset detected Error flag on

Address 0x22

At least one analog

input is open

on a channel

Overvoltage

detected on a

channel

Undervoltage

detected on a

channel

¹See the Diagnostics section for more information.

Serial Register Mode (Reading Register Data)

The format for a write command, as shown in Figure 74, is

structured as follows:

All the registers in Table 31 can be read over the serial interface.

The format for a read command is shown in Figure 73. It consists

of two 16-bit frames. On the first frame,

•

The first bit in SDI must be set to 0 to enable a write

command.

W

•

The second bit, the R/ bit, must be cleared to 0.

•

The first bit in SDI must be set to 0 to enable writing the

address.

The second bit must be set to 1 to select a read command.

Bits[3:8] in SDI contain the register address to be clocked out

on D_OUTA on the following frame.

Bits[ADD5:ADD0] contain the register address to be

written.

The subsequent eight bits (Bits[DIN7:DIN0]) contain the

data to be written to the selected register. Data is clocked in

from SDI on the falling edge of SCLK, while data is clocked

out on D_OUTA on the rising edge of SCLK.

•

The subsequent eight bits, Bits[9:16], in SDI are ignored.

If the AD7606B is in ADC mode, the SDO keeps clocking ADC

data on Bits[9:16], and then the AD7606B switches to register

mode.

When writing continuously to the device, the data that appears

on D_OUTA is from the register address that was written to on the

previous frame, as shown in Figure 74. The D_OUTB, D_OUTC, and

_OUTD pins are kept low during the transmission.

While in register mode, no ADC data is clocked out because the

_OUTx lines are used to clock out register content. When finished

writing all needed registers, a write to Address 0x00 returns the

AD7606B to ADC read mode, where the ADC data is again

clocked out on the D_OUTx lines, as shown in Figure 72.

If the AD7606B is in register mode, the SDO reads back the

content from the previous addressed register, no matter if the

previous frame was a read or a write command. To exit register

mode, a write to Address 0x00 is required, as shown in Figure 72.

D

Serial Register Mode (Writing Register Data)

In software mode, all the read/write registers in Table 31 can be

written to over the serial interface. To write a sequence of

registers, exit ADC read mode (default mode) by reading any

register on the memory map. A register write command is

performed by a single 16-bit SPI access. The format for a write

command is shown in Figure 74.

In software mode, when the CRC is turned on, eight additional

bits are clocked in and out on each frame. Therefore, 24-bit

frames are needed.

Rev. 0 | Page 37 of 69

AD7606B

Data Sheet

CS

SCLK

1

8

16

SDI

ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

WEN R/W

READ OR WRITE COMMAND

D

A

OUT

ADC DATA (8LSB) OR PREVIOUS

REGISTER READ/WRITTEN

ADC DATA (8LSB) OR XX

REGISTER [ADD5:ADD0] CONTENT

Figure 73. Serial Interface Read Command; First Frame Points the Address; Second Frame Provides the Register Content

CS

SCLK

1

8

9

16

1

SDI

WEN R/W ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 DIN7 DIN6 DIN5 DIN4 DIN3 DIN2 DIN1 DIN0

D

A

2

OUT

DATA OUT

1

2

DATA IN DINx IS WRITTEN INTO REGISTER ADDRESS [ADD5:ADD0]

DATA OUT IS THE REGISTER CONTENT OF PREVIOUS REGISTER WRITTEN

Figure 74. Serial Interface, Single-Write Command; SDI Clocks in the Address [ADD5:ADD0] and the Register Content [DINx] During the Same Frame, D_OUTA Provides

Register Content Requested on the Previous Frame

CS

1

8

9

16

24

SCLK

SDI

ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

WEN

R/W

MSB

LSB

8-BIT CRC

D

A

OUT

Figure 75. Reading Registers Through the SPI Interface with CRC Enabled

CS

1

8

9

16

24

SCLK

SDI

ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 MSB

LSB

8-BIT CRC

WEN

R/W

Figure 76. Writing Registers Through the SPI Interface with CRC Enabled

Serial Register Mode with CRC

With the CRC enabled, the SPI frames extend to 24 bits in

length, as shown in Figure 75.

Registers can be written to and read from the AD7606B with

CRC enabled, in software mode, by asserting the INT_CRC_

ERR_EN bit (Address 0x21, Bit 2).

When writing a register, the controller must clock the data

(register address plus register content) in the AD7606B followed by

an 8-bit CRC word, calculated from the previous 16 bits using

the previously described polynomial. The AD7606B reads the

register address and the register content, calculates the

corresponding 8-bit CRC word, and asserts the INT_CRC_ERR bit

(Address 0x22, Bit 2) if the calculated CRC word does not match

the CRC word received between the 17^thand 24^thbit through

SDI, as shown in Figure 76.

When reading a register, the AD7606B provides eight additional

bits on the D_OUTA pin with the CRC resultant of the data shifted

out previously on the same frame. The controller can then

check whether the data received is correct by applying the

following polynomial:

x⁸+ x²+ x + 1

Rev. 0 | Page 38 of 69

Data Sheet

AD7606B

DIAGNOSTICS

Diagnostic features are available in software mode to verify

correct operation of the AD7606B. The list of diagnostic

monitors includes reset detection, overvoltage detection,

undervoltage detection, analog input open circuit detection,

and digital error detection.

When the voltage on any analog input pin goes below the

undervoltage threshold shown in Table 27, the AIN_UV_

DIAG_ERROR register (Address 0x27) shows which channel or

channels have an undervoltage event. When a bit within the

AIN_UV_DIAG_ERROR register asserts, it stays at high state

after the undervoltage event disappears. To clear the error bit, the

error bit must be overwritten to 1 or the error checker must be

disabled.

If an error is detected, a flag asserts on the status header, if

enabled, as described in the Digital Interface section. This flag

points to the registers on which the error is located, as explained

in the following sections.

Table 27. Overvoltage and Undervoltage Thresholds

In addition, a diagnostic multiplexer can dedicate any channel

to verify a series of internal nodes, as explained in the

Diagnostics Multiplexer section.

Analog Input

Range (V)

Overvoltage

Threshold (V)

Undervoltage

Threshold (V)

2.5

5

10

+6.5

+8

+12

−3

−5.5

−11

RESET DETECTION

The RESET_DETECT bit on the status register (Address 0x01,

Bit 7) asserts if either a partial reset or full reset pulse is applied

to the AD7606B. On power-up, a full reset is required. This

reset asserts the RESET_DETECT bit, indicating that the

power-on reset (POR) initialized correctly on the device.

DIGITAL ERROR

Both the status register and status header contain a

DIGITAL_ERROR bit. This bit asserts when any of the

following monitors trigger:

•

Memory map CRC, read only memory (ROM) CRC, and

digital interface CRC.

The POR monitors the REGCAP voltage and issues a full reset

if the voltage drops under a certain threshold.

•

SPI invalid read or write.

BUSY stuck high.

The RESET_DETECT bit can be used to detect an unexpected

device reset or a large glitch on the RESET pin, or a voltage

drop on the supplies.

To find out which monitor triggered the DIGITAL_ERROR bit,

the DIGITAL_DIAG_ERR address (Address 0x22) has a bit

dedicated for each monitor, as explained in the following sections.

The RESET_DETECT bit is only cleared by reading the status

register.

ROM CRC

OVERVOLTAGE AND UNDERVOLTAGE EVENTS

The ROM stores the factory trimming settings for the

AD7606B. After power-up, the ROM content is loaded to

registers during device initialization. After the load, a CRC is

calculated on the loaded data and verified if the result matches

the CRC stored in the ROM. If an error is found, the ROM_

CRC_ERR (Address 0x22, Bit 0) asserts. When ROM_CRC_

ERR asserts after power-up, it is recommended to issue a full

reset to reload all factory settings.

The AD7606B includes on-chip overvoltage and undervoltage

circuitry on each analog input pin. These comparators can be

enabled or disabled using the AIN_OV_UV_DIAG_

ENABLE register (Address 0x25).

After this register is enabled, when the voltage on any analog

input pin goes above the overvoltage threshold shown in Table 27,

the AIN_OV_DIAG_ERROR register (Address 0x26) shows

which channel or channels have an overvoltage event. When a

bit within the AIN_OV_DIAG_ERROR register asserts, it stays

at a high state even after the overvoltage event disappears. To

clear the error bit, the error bit must be overwritten to 1 or the

error checker must be disabled.

This ROM CRC monitoring feature is enabled by default, but

can be disabled by clearing the ROM_CRC_ERR_EN bit

(Address 0x21, Bit 0).

Memory Map CRC

The memory map CRC is disabled by default. After the

AD7606B is configured in software mode through writing the

required registers, the memory map CRC can be enabled

through the MM_CRC_ERR_EN bit (Address 0x21, Bit 1).

When enabled, the CRC calculation is performed on the entire

memory map and stored. Every 4 μs, the CRC on the memory

map is recalculated and compared to the stored CRC value. If

the calculated and the stored CRC values do not match, the

memory map is corrupted and the MM_CRC_ERR bit asserts.

Every time the memory map is written, the CRC is recalculated

and the new value stored.

AD7606B

OVERVOLTAGE

THRESHOLD

CHx_OV_ERR

SETS IF Vx > OV

V

x

CHx_UV_ERR

SETS IF Vx < UV

UNDERVOLTAGE

THRESHOLD

Figure 77. Overvoltage and Undervoltage Circuitry on Each Analog Input

Rev. 0 | Page 39 of 69

AD7606B

Data Sheet

If the MM_CRC_ERR bit asserts, it is recommended to write to

the memory map to recalculate the CRC. If the error persists, it

is recommended to issue a full reset to restore the default

contents of the memory map.

The serial interface supports the CRC when enabled via the

INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is a 16-

bit word that is appended to the end of each D_OUTx in use, after

reading all the channels. An example using four D_OUTx lines is

shown in Figure 78.

Interface CRC Checksum

CNVST

The AD7606B has a CRC checksum mode to improve interface

robustness by detecting errors in data transmission. The CRC

feature is available in both ADC modes (serial and parallel) and

register mode (serial only).

CS

SCLK

D

A

B

C

D

V1

V3

V5

V7

V2

V4

V6

V8

CRC(V1,V2)

CRC(V3,V4)

CRC(V5,V6)

CRC(V7,V8)

OUT

The AD7606B uses the following 8-bit CRC polynomial to

calculate the CRC checksum value:

x

¹⁶+ x¹⁴+ x¹³+ x¹²+ x¹⁰+ x⁸+x⁶+ x⁴+ x³+ x + 1

To replicate the polynomial division in hardware, the data shifts

left by 16 bits to create a number ending in 16 Logic 0s. The

polynomial is aligned so that the MSB is adjacent to the

leftmost Logic 1 of the data. An exclusive OR (XOR) function is

applied to the data to produce a new, shorter number. The

polynomial is again aligned so that the MSB is adjacent to the

leftmost Logic 1 of the new result, and the procedure repeats.

This process repeats until the original data is reduced to a value

less than the polynomial, the 16-bit checksum.

Figure 78. Serial Interface ADC Reading with CRC On, Four D_OUTx Lines

If using two D_OUTx lines (D_OUTA and D_OUTB), each 16-bit CRC

word is calculated using data from four channels, that is 64 bits,

as shown in Figure 79. If using only one D_OUTx line, all eight

channels are clocked out through D_OUTA, followed by the 16-bit

CRC word calculated using data from the eight channels, that is,

128 bits.

An example of the CRC calculation for the 16-bit data is shown

in Table 28. The CRC corresponding to the data 0x064E, using

the previously described polynomial, is 0x2137.

CNVST

CS

SCLK

D

A

B

C

D

V1

V5

V2

V6

V3

V7

V4

V8

CRC(V1,V4)

CRC(V5,V8)

OUT

Figure 79. Serial Interface ADC Reading with CRC On, Two D_OUTx Lines

Rev. 0 | Page 40 of 69

Data Sheet

AD7606B

When the AD7606B is in register mode, that is, when registers

are being read or written, the CRC polynomial used is x⁸+ x²+

x + 1. When reading a register, and CRC is enabled, each SPI

frame is 24 bits long and the CRC 8-bit word is clocked out

from the 17^thto 24^thSCLK cycle. Similarly, when writing a

register, a CRC word can be appended on the SDI line, as shown

in Figure 80 and the AD7606B checks and triggers an error,

INT_CRC_ERR (Address 0x22, Bit 2), if the CRC given and the

internally calculated do not match.

The parallel interface also supports CRC in ADC mode only,

and it is clocked out through DB15 to DB0 after Channel 8, as

shown in Figure 65. The 16-bit CRC word calculated using data

from the eight channels, that is, 128 bits.

CS

1

2

3

4

15

16

17

24

SCLK

A TO D

D

OUT

DB15 DB14 DB13 DB12

WEN R/W ADD5 ADD4

DB1 DB0 CRC7

DIN1 DIN0 CRC7

CRC0

OUT

SDI

CRC0

Figure 80. Register Write with CRC On

Rev. 0 | Page 41 of 69

AD7606B

Data Sheet

Table 28. Example CRC Calculation for 16-Bit Data¹

Data²

0

1

0

1

0

1

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

x

0

Process

Data

0

1

0

1

0

Polynomial

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

CRC

¹This table represents the division of the data. Blank cells are for formatting purposes.

²X = don’t care.

Interface Check

BUSY Stuck High

BUSY stuck high monitoring is enabled by setting the

BUSY_STUCK_HIGH_ERR_EN bit (Address 0x21, Bit 5).

After this bit is enabled, the conversion time (t_CONVin Table 3) is

monitored internally with an independent clock. If t_CONVexceeds

4 μs, the AD7606B automatically issues a partial reset and asserts

the BUSY_STUCK_HIGH_ERR bit (Address 0x22, Bit 5). To

clear this error flag, the BUSY_STUCK_HIGH_ERR bit must be

overwritten with a 1.

The integrity of the digital interface can be checked by setting

the INTERFACE_CHECK_EN bit (Address 0x21, Bit 7).

Selecting the interface check forces the conversion result

registers to a known value, as shown in Table 29.

Verifying that the controller receives the data shown in Table 29

ensures that the interface between the AD7606B and the

controller operates properly. If the interface CRC is enabled

because the data transmitted is known, this mode verifies that

the controller performs the CRC calculation properly.

When oversampling mode is enabled, the individual conversion

time for each internal conversion is monitored.

Table 29. Interface Check Conversion Results

Channel Number

DIAGNOSTICS MULTIPLEXER

Conversion Result Forced (Hex.)

All eight input channels contain a diagnostics multiplexer in

front of the PGA that allows monitoring of the internal nodes

described in Table 30 to ensure the correct operation of the

AD7606B. Table 30 shows the bit decoding for the diagnostic mux

register on Channel 1, as an example. When an internal node is

selected, the input voltage at input pins are deselected from the

PGA, as shown in Figure 81.

V1

V2

V3

V4

V5

V6

V7

V8

0xACCA

0x5CC5

0xA33A

0x5335

0xCAAC

0xC55C

0x3AA3

0x3553

Each diagnostic multiplexer configuration is accessed, in

software mode through the corresponding register (Address 0x28

to Address 0x2B). To use the multiplexer on one channel, the

10 V range must be selected on that channel.

SPI Invalid Read/Write

When attempting to read back an invalid register address, the

SPI_READ_ERR bit (Address 0x22, Bit 4) is set. The invalid

readback address detection can be enabled by setting the

SPI_READ_ERR_EN bit (Address 0x21, Bit 4). If an SPI read

error is triggered, it is cleared by overwriting that bit or disabling

the checker.

Table 30. Diagnostic Mux Register Bit Decoding of Channel 1

Address 0x18

Bit 2

Bit 1

Bit 0

Signal on Channel 1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

V1

Temperature sensor

V_REF

4 × ALDO

4 × DLDO

V_DRIVE

When attempting to write to an invalid register address or a

read only register, the SPI_WRITE_ERR bit (Address 0x22, Bit 3) is

set. The invalid write address detection can be enabled by

setting the SPI_WRITE _ERR bit (Address 0x21, Bit 3). If an SPI

write error is triggered, it is cleared by overwriting that bit or

disabling the checker.

AGND

AV_CC

Rev. 0 | Page 42 of 69

Data Sheet

AD7606B

Therefore, if the ADC output goes beyond the expected 2.5 V,

either the reference buffer or the PGA is malfunctioning.

TEMPERATURE

SENSOR

AD7606B

V

REF

4×ALDO

4×DLDO

MUX

AD7606B

V

DRIVE

AGND

5MΩ

AV

R

CC

FB

INT REF

4.4V

V1

V1GND

EXT REF

5MΩ

2.5V

MUX

R

FB

5MΩ

Vx

R

FB

ADC

VxGND

Figure 81. Diagnostic Multiplexer (Channel 1 Shown as an Example)

R

FB

Temperature Sensor

Figure 82. Reference Voltage Signal Path Through the Diagnostic Multiplexer

The temperature sensor can be selected through the diagnostic

multiplexer and converted with the ADC, as shown in Figure 81.

The temperature sensor voltage is measured and is proportional to

the die temperature, as per the following equation:

Internal LDOs

The analog and digital LDO (REGCAP pins) can be selected

through the diagnostic multiplexer and converted with the

ADC, as shown in Figure 81. The ADC output is four times the

voltage on the REGCAPA and REGCAPD pins, respectively.

This measurement verifies that each LDO is at the correct

operating voltage so that the internal circuitry is biased correctly.

ADC_OUTV − 0.69068 V

(

)

( )

Temperature °C =

+ 25 °C

(

)

(

)

0.019328 V / °C

(

)

with an accuracy of 2°C.

Reference Voltage

Supply Voltages

The reference voltage can be selected through the diagnostic

AV_CC, V_DRIVE, and AGND can be selected through the diagnostic

multiplexer and converted with the ADC, as shown in Figure 81.

This setup ensures the voltage and grounds are correctly applied to

the device to ensure correct operation.

multiplexer and converted with the ADC, as shown in Figure 82.

The internal or external reference is selected as input to the

diagnostic multiplexer based on REF SELECT pin. Ideally, the

ADC output follows the voltage reference level ratio metrically.

Rev. 0 | Page 43 of 69

AD7606B

Data Sheet

TYPICAL CONNECTION DIAGRAM

There are four AV_CCsupply pins on the device. It is recommended

that each of the four pins are decoupled using a 100 nF capacitor at

each supply pin and a 10 µF capacitor at the supply source. The

AD7606B can operate with the internal reference or an externally

applied reference. When using a single AD7606B device on the

board, decouple the REFIN/REFOUT pin with a 100 nF capacitor.

Refer to the Reference section when using an application with

multiple AD7606B devices. The REFCAPA and REFCAPB pins

are shorted together and decoupled with a 10 µF ceramic capacitor.

PAR

/SER pin is tied to AGND.

parallel interface because the

The analog input range for all eight channels is 10 V, provided

the RANGE pin is tied to a high level and the oversampling

ratio is controlled through the OS pins by the controller.

In Figure 84, the AD7606B is configured in software mode,

because all three OS2, OS1, and OS0 pins are at logic level high.

The oversampling ratio, as well as each channel range, are

configured through accessing the memory map. In this example,

PAR

the

/SER pin is at logic level high. Therefore, the serial

The V_DRIVEsupply is connected to the same supply as the

processor. The V_DRIVEvoltage controls the voltage value of the

output logic signals. For more information on layout, decoupling,

and grounding, see the Layout Guidelines section.

interface is used for both reading the ADC data and reading

and writing the memory map. The REF SELECT pin is tied to

AGND. Therefore, the internal reference is disabled and an

external reference is connected externally to the REFIN/REFOUT

pin and decoupled through a 100 nF capacitor.

After supplies are applied to the AD7606B, apply a reset to the

AD7606B to ensure that it is configured for the correct mode of

operation.

Figure 83 and Figure 84 are examples of typical connection

diagrams. Other combinations of reference, data interface, and

operation mode are also possible, depending on the logic levels

applied to each configuration pin.

In Figure 83, the AD7606B is configured in hardware mode and is

operating with the internal reference because the REF SELECT pin

is set to logic high. In this example, the device also uses the

ANALOG SUPPLY

DIGITAL SUPPLY

VOLTAGE +1.71V TO +3.6V

1

VOLTAGE 5V

+

100nF

1µF

100nF

2

REFIN/REFOUT

REGCAP

AV

V

CC

DRIVE

REFCAPA

PARALLEL

INTERFACE

DB0 TO DB15

+

REFCAPB

REFGND

10µF

CONVST

CS

V1

V1GND

V2

RD

BUSY

V2GND

V3

RESET

OS2

AD7606B

V3GND

V4

OS1

OVERSAMPLING

EIGHT ANALOG

INPUTS V1 TO V8

V4GND

V5

OS0

V5GND

V6

REF SELECT

PAR/SER SEL

RANGE

STBY

V

DRIVE

V6GND

V7

V

DRIVE

V7GND

V8

V8GND

AGND

1

2

DECOUPLING SHOWN ON THE AV PIN APPLIES TO EACH AV PIN (PIN 1, PIN 37, PIN 38, PIN 48).

CC

DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV

PIN 37 AND PIN 38.

CC

DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).

Figure 83. AD7606B Typical Connection Diagram, Hardware Mode

Rev. 0 | Page 44 of 69

Data Sheet

AD7606B

ANALOG SUPPLY

DIGITAL SUPPLY

VOLTAGE +1.71V TO +3.6V

1

VOLTAGE 5V

REF

+

100nF

1µF

100nF

2

REFIN/REFOUT

REFCAPA

REGCAP

AV

V

DRIVE

CC

DB0 TO DB15

+

REFCAPB

REFGND

10µF

CONVST

CS

V1

V1GND

V2

SDI

D

x

OUT

V2GND

V3

SCLK

RESET

AD7606B

V3GND

V4

OS2

OS1

OVERSAMPLING =

111b

EIGHT ANALOG

INPUTS V1 TO V8

V4GND

V5

OS0

V5GND

V6

REF SELECT

V6GND

V7

PAR/SER SEL

RANGE

V

DRIVE

V7GND

V8

STBY

V8GND

AGND

1

2

DECOUPLING SHOWN ON THE AV PIN APPLIES TO EACH AV PIN (PIN 1, PIN 37, PIN 38, PIN 48).

CC

DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV PIN 37 AND PIN 38.

CC

DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39).

Figure 84. Typical Connection Diagram, Software Mode

Rev. 0 | Page 45 of 69

AD7606B

Data Sheet

APPLICATIONS INFORMATION

Figure 85 shows the recommended decoupling on the top layer

of the AD7606B board. Figure 86 shows bottom layer decoupling,

which is used for the four AV_CCpins and the V_DRIVEpin decoupling.

Where the ceramic 100 nF caps for the AV_CCpins are placed

close to their respective device pins, a single 100 nF capacitor

can be shared between Pin 37 and Pin 38.

LAYOUT GUIDELINES

The following layout guidelines are recommended to be

followed when designing the PCB that houses the AD7606B:

•

The analog and digital sections are separated and confined

to different areas of the board.

•

Use at least one ground plane. This plane can be common

or split between the digital and analog sections. In the case

of a split plane, join the digital and analog ground planes in

only one place, preferably as close as possible to the

AD7606B.

•

If the AD7606B is in a system where multiple devices

require analog-to-digital ground connections, make the

connection at only one point: a star ground point that is

established as close as possible to the AD7606B.

Make stable connections to the ground plane. Avoid

sharing one connection for multiple ground pins. Use

individual vias or multiple vias to the ground plane for

each ground pin.

•

Avoid running digital lines under the device because doing

so couples noise on the die. Allow the analog ground plane

to run under the AD7606B to avoid noise coupling.

Shield fast switching signals like CONVST, or clocks with

digital ground to avoid radiating noise to other sections of

the board and ensure that they never run near analog

signal paths.

Figure 85. Top Layer Decoupling REFIN/REFOUT,

REFCAPA, REFCAPB, and REGCAP Pins

•

Avoid crossover of digital and analog signals.

Traces on layers in close proximity on the board run at

right angles to each other to reduce the effect of

feedthrough through the board.

•

Power supply lines to the AV_CCand V_DRIVEpins on the

AD7606B use as large a trace as possible to provide low

impedance paths and reduce the effect of glitches on the

power supply lines. Where possible, use supply planes and

make stable connections between the AD7606B supply

pins and the power tracks on the board. Use a single via or

multiple vias for each supply pin.

•

Place the decoupling capacitors close to (ideally, directly

against) the supply pins and their corresponding ground

pins. Place the decoupling capacitors for the REFIN/

REFOUT pin and the REFCAPA pin and REFCAPB pin as

close as possible to their respective AD7606B pins. Where

possible, place the pins on the same side of the board as the

AD7606B device.

Figure 86. Bottom Layer Decoupling

Rev. 0 | Page 46 of 69

Data Sheet

AD7606B

To ensure stable device to device performance matching in a

system that contains multiple AD7606B devices, a symmetrical

layout between the AD7606B devices is important.

AVCC

Figure 87 shows a layout with two AD7606B devices. The AV_CC

supply plane runs to the right of both devices, and the V_DRIVE

supply track runs to the left of the two devices. The reference

chip is positioned between the two devices, and the reference

voltage track runs north to Pin 42 of U1 and south to Pin 42 of

U2. A solid ground plane is used.

U2

These symmetrical layout principles can also be applied to a

system that contains more than two AD7606B devices. The

AD7606B devices can be placed in a north/south direction, with

the reference voltage located midway between the devices and

the reference track running in the north/south direction,

similar to Figure 87.

U1

Figure 87. Layout for Multiple AD7606B Devices—Top Layer and

Supply Plane Layer

Rev. 0 | Page 47 of 69

AD7606B

Data Sheet

REGISTER SUMMARY

Table 31. Register Summary

Addr Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset RW

0x01 STATUS

RESET_

DETECT

DIGITAL_

ERROR

RESERVED

0x00

0x08

0x33

R

0x02 CONFIG

RESERVED

STATUS_

HEADER

EXT_OS_CLOCK

DOUT_FORMAT

RESERVED

OPERATION_MODE

R/W

0x03 RANGE_CH1_

CH2

CH2_RANGE

CH1_RANGE

0x04 RANGE_CH3_

CH4

CH4_RANGE

CH6_RANGE

CH8_RANGE

OS_PAD

CH3_RANGE

CH5_RANGE

CH7_RANGE

OS_RATIO

0x05 RANGE_CH5_

CH6

0x06 RANGE_CH7_

CH8

0x08 OVERSAMPLING

0x09 CH1_GAIN

0x0A CH2_GAIN

0x0B CH3_GAIN

0x0C CH4_GAIN

0x0D CH5_GAIN

0x0E CH6_GAIN

0x0F CH7_GAIN

0x10 CH8_GAIN

0x11 CH1_OFFSET

0x12 CH2_OFFSET

0x13 CH3_OFFSET

0x14 CH4_OFFSET

0x15 CH5_OFFSET

0x16 CH6_OFFSET

0x17 CH7_OFFSET

0x18 CH8_OFFSET

0x19 CH1_PHASE

0x1A CH2_PHASE

0x1B CH3_PHASE

0x1C CH4_PHASE

0x1D CH5_PHASE

0x1E CH6_PHASE

0x1F CH7_PHASE

0x20 CH8_PHASE

0x00

0x80

0x00

0x01

R/W

RESERVED

CH1_GAIN

RESERVED

CH2_GAIN

CH3_GAIN

CH4_GAIN

CH5_GAIN

CH6_GAIN

CH7_GAIN

CH8_GAIN

CH1_OFFSET

CH2_OFFSET

CH3_OFFSET

CH4_OFFSET

CH5_OFFSET

CH6_OFFSET

CH7_OFFSET

CH8_OFFSET

CH1_PHASE_OFFSET

CH2_PHASE_OFFSET

CH3_PHASE_OFFSET

CH4_PHASE_OFFSET

CH5_PHASE_OFFSET

CH6_PHASE_OFFSET

CH7_PHASE_OFFSET

CH8_PHASE_OFFSET

0x21 DIGITAL_

DIAG_ENABLE

INTERFACE_

CHECK_EN

CLK_FS_OS_

COUNTER_EN

BUSY_STUCK_

HIGH_ERR_EN

SPI_READ_

ERR_EN

SPI_WRITE_

ERR_EN

INT_CRC_

ERR_EN

MM_CRC_

ERR_EN

ROM_

CRC_

ERR_EN

0x22 DIGITAL_

DIAG_ERR

RESERVED

BUSY_STUCK_

HIGH_ERR

SPI_READ_

ERR

SPI_WRITE_

ERR

INT_CRC_ERR MM_CRC_

ERR

ROM_

CRC_

ERR

0x00

R/W

0x23 OPEN_

DETECT_

CH8_OPEN_

DETECT_EN

CH7_OPEN_

DETECT_EN

CH6_OPEN_

DETECT_EN

CH5_OPEN_ CH4_OPEN_ CH3_OPEN_ CH2_OPEN_ CH1_

DETECT_EN

OPEN_

DETECT_

EN

ENABLE

0x24 OPEN_

DETECTED

CH8_OPEN

CH8_OV_

CH7_OPEN

CH6_OPEN

CH5_OPEN

CH4_OPEN

CH3_OPEN

CH2_OPEN

CH1_

OPEN

0x00

R/W

0x25 AIN_OV_UV_

CH7_OV_UV_EN CH6_OV_UV_EN CH5_OV_

UV_EN

CH4_OV_

UV_EN

CH3_OV_

UV_EN

CH2_OV_

UV_EN

CH1_

OV_UV_

EN

DIAG_ENABLE UV_EN

0x26 AIN_OV_DIAG_ CH8_OV_ERR CH7_OV_ERR

ERROR

CH6_OV_ERR

CH6_UV_ERR

CH5_OV_ERR CH4_OV_ERR CH3_OV_ERR CH2_OV_ERR CH1_

OV_ERR

CH5_UV_ERR CH4_UV_ERR CH3_UV_ERR CH2_UV_ERR CH1_

UV_ERR

0x00

R/W

0x27 AIN_UV_DIAG_ CH8_UV_ERR CH7_UV_ERR

ERROR

0x28 DIAGNOSTIC_

MUX_CH1_2

RESERVED

CH2_DIAG_MUX_CTRL

CH4_DIAG_MUX_CTRL

CH1_DIAG_MUX_CTRL

0x29 DIAGNOSTIC_

MUX_CH3_4

RESERVED

CH3_DIAG_MUX_CTRL

Rev. 0 | Page 48 of 69

Data Sheet

AD7606B

Addr Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset RW

0x2A DIAGNOSTIC_

MUX_CH5_6

RESERVED

CH6_DIAG_MUX_CTRL

CH8_DIAG_MUX_CTRL

OPEN_DETECT_QUEUE

CH5_DIAG_MUX_CTRL

0x00

R/W

0x2B DIAGNOSTIC_

MUX_CH7_8

RESERVED

CH7_DIAG_MUX_CTRL

0x2C OPEN_

DETECT_

QUEUE

0x2D FS_CLK_

COUNTER

CLK_FS_COUNTER

CLK_OS_COUNTER

0x00

0x14

R

0x2E OS_CLK_

COUNTER

0x2F ID

DEVICE_ID

SILICON_REVISION

Rev. 0 | Page 49 of 69

AD7606B

Data Sheet

REGISTER DETAILS

Address: 0x01, Reset: 0x00, Name: STATUS

7

6

5

4

3

2

1

0

[7] RESET_DETECT (R)

[5:0] RESERVED

A reset has been detected, either

full or partial reset

[6] DIGITAL_ERROR (R)

Error present in DIGITAL_DIAG_ERROR

register

Table 32. Bit Descriptions for STATUS

Bits

7

Bit Name

Description

Reset

0x0

Access

RESET_DETECT

DIGITAL_ERROR

RESERVED

A reset has been detected, either full or partial reset.

Error present in DIGITAL_DIAG_ERROR register.

Reserved.

R

6

[5:0]

0x0

Address: 0x02, Reset: 0x08, Name: CONFIG

7

6

5

4

3

2

1

0

1

0

[7] RESERVED

[1:0] OPERATION_MODE (R/W)

Operation mode

00: normal mode.

01: standby mode.

10: autostandby mode.

11: shutdown mode.

[6] STATUS_HEADER (R/W)

Enable STATUS header to be appended

to ADC data in both serial and parallel

interface

[5] EXT_OS_CLOCK (R/W)

[2] RESERVED

In oversampling mode, enable external

oversampling clock. Oversampling

conversions are triggered through

a clock signal applied to CONVST

pin, instead of managed by the internal

oversampling clock

[4:3] DOUT_FORMAT (R/W)

Number of DOUT lines used in serial

mode when reading conversions

00: 1 D_OUTx.

01: 2 D_OUTx.

10: 4 D_OUTx.

11: 1 D_OUTx.

Table 33. Bit Descriptions for CONFIG

Bits Bit Name

Description

Reset Access

7

6

5

RESERVED

STATUS_HEADER

EXT_OS_CLOCK

Reserved.

0x0

R

R/W

Enable STATUS header to be appended to ADC data in both serial and parallel interface.

In oversampling mode, enable external oversampling clock. Oversampling conversions are 0x0

triggered through a clock signal applied to CONVST pin, instead of managed by the

internal oversampling clock.

[4:3] DOUT_FORMAT

Number of D_OUTx lines used in serial mode when reading conversions.

0x1

R/W

00: 1 D_OUTx.

01: 2 D_OUTx.

10: 4 D_OUTx.

11: 1 D_OUTx.

Reserved.

2

RESERVED

0x0

R

R/W

[1:0] OPERATION_MODE Operation mode.

00: normal mode.

01: standby mode.

10: autostandby mode.

11: shutdown mode.

Rev. 0 | Page 50 of 69

Data Sheet

AD7606B

Address: 0x03, Reset: 0x33, Name: RANGE_CH1_CH2

7

6

5

4

3

2

1

0

1

0

1

[7:4] CH2_RANGE (R/W)

Range options for Channel 2

0000: ±2.5V single-ended range.

0001: ±5V single-ended range.

0010: ±10V single-ended range.

...

[3:0] CH1_RANGE (R/W)

Range options for Channel 1

0000: ±2.5V single-ended range.

0001: ±5V single-ended range.

0010: ±10V single-ended range.

...

1101: reserved.

1110: reserved.

1111: reserved.

Table 34. Bit Descriptions for RANGE_CH1_CH2

Bits

Bit Name

Description

Reset

Access

[7:4]

CH2_RANGE

Range options for Channel 2.

0x3

R/W

0000: 2.5 V single-ended range.

0001: 5 V single-ended range.

0010: 10 V single-ended range.

0011: 10 V single-ended range.

0100: 10 V single-ended range.

0101: 10 V single-ended range.

0110: 10 V single-ended range.

0111: 10 V single-ended range.

1000: 10 V single-ended range.

1001: 10 V single-ended range.

1010: 10 V single-ended range.

1011: 10 V single-ended range.

1100: reserved.

1101: reserved.

1110: reserved.

1111: reserved.

[3:0]

CH1_RANGE

Range options for Channel 1.

0000: 2.5 V single-ended range.

0001: 5 V single-ended range.

0010: 10 V single-ended range.

0011: 10 V single-ended range.

0100: 10 V single-ended range.

0101: 10 V single-ended range.

0110: 10 V single-ended range.

0111: 10 V single-ended range.

1000: 10 V single-ended range.

1001: 10 V single-ended range.

1010: 10 V single-ended range.

1011: 10 V single-ended range.

1100: reserved.

0x3

R/W

1101: reserved.

1110: reserved.

1111: reserved.

Rev. 0 | Page 51 of 69

AD7606B

Data Sheet

Address: 0x04, Reset: 0x33, Name: RANGE_CH3_CH4

7

6

5

4

3

2

1

0

1

0

1

[7:4] CH4_RANGE (R/W)

Range options for Channel 4

0000: ±2.5V single-ended range.

0001: ±5V single-ended range.

0010: ±10V single-ended range.

...

[3:0] CH3_RANGE (R/W)

Range options for Channel 3

0000: ±2.5V single-ended range.

0001: ±5V single-ended range.

0010: ±10V single-ended range.

...

1101: reserved.

1110: reserved.

1111: reserved.

Table 35. Bit Descriptions for RANGE_CH3_CH4

Bits

Bit Name

Description

Reset

Access

[7:4]

CH4_RANGE

Range options for Channel 4.

0x3

R/W

0000: 2.5 V single-ended range.

0001: 5 V single-ended range.

0010: 10 V single-ended range.

0011: 10 V single-ended range.

0100: 10 V single-ended range.

0101: 10 V single-ended range.

0110: 10 V single-ended range.

0111: 10 V single-ended range.

1000: 10 V single-ended range.

1001: 10 V single-ended range.

1010: 10 V single-ended range.

1011: 10 V single-ended range.

1100: reserved.

1101: reserved.

1110: reserved.

1111: reserved.

[3:0]

CH3_RANGE

Range options for Channel 3.

0000: 2.5 V single-ended range.

0001: 5 V single-ended range.

0010: 10 V single-ended range.

0011: 10 V single-ended range.

0100: 10 V single-ended range.

0101: 10 V single-ended range.

0110: 10 V single-ended range.

0111: 10 V single-ended range.

1000: 10 V single-ended range.

1001: 10 V single-ended range.

1010: 10 V single-ended range.

1011: 10 V single-ended range.

1100: reserved.

0x3

R/W

1101: reserved.

1110: reserved.

1111: reserved.

Rev. 0 | Page 52 of 69

Data Sheet

AD7606B

Address: 0x05, Reset: 0x33, Name: RANGE_CH5_CH6

7

6

5

4

3

2

1

0

1

0

1

[7:4] CH6_RANGE (R/W)

Range options for Channel 6

0000: ±2.5V single-ended range.

0001: ±5V single-ended range.

0010: ±10V single-ended range.

...

[3:0] CH5_RANGE (R/W)

Range options for Channel 5

0000: ±2.5V single-ended range.

0001: ±5V single-ended range.

0010: ±10V single-ended range.

...

1101: reserved.

1110: reserved.

1111: reserved.

Table 36. Bit Descriptions for RANGE_CH5_CH6

Bits

Bit Name

Description

Reset

Access

[7:4]

CH6_RANGE

Range options for Channel 6.

0x3

R/W

0000: 2.5 V single-ended range.

0001: 5 V single-ended range.

0010: 10 V single-ended range.

0011: 10 V single-ended range.

0100: 10 V single-ended range.

0101: 10 V single-ended range.

0110: 10 V single-ended range.

0111: 10 V single-ended range.

1000: 10 V single-ended range.

1001: 10 V single-ended range.

1010: 10 V single-ended range.

1011: 10 V single-ended range.

1100: reserved.

1101: reserved.

1110: reserved.

1111: reserved.

[3:0]

CH5_RANGE

Range options for Channel 5.

0000: 2.5 V single-ended range.

0001: 5 V single-ended range.

0010: 10 V single-ended range.

0011: 10 V single-ended range.

0100: 10 V single-ended range.

0101: 10 V single-ended range.

0110: 10 V single-ended range.

0111: 10 V single-ended range.

1000: 10 V single-ended range.

1001: 10 V single-ended range.

1010: 10 V single-ended range.

1011: 10 V single-ended range.

1100: reserved.

0x3

R/W

1101: reserved.

1110: reserved.

1111: reserved.

Rev. 0 | Page 53 of 69

AD7606B

Data Sheet

Address: 0x06, Reset: 0x33, Name: RANGE_CH7_CH8

7

6

5

4

3

2

1

0

1

0

1

[7:4] CH8_RANGE (R/W)

Range options for Channel 8

0000: ±2.5V single-ended range.

0001: ±5V single-ended range.

0010: ±10V single-ended range.

...

[3:0] CH7_RANGE (R/W)

Range options for Channel 7

0000: ±2.5V single-ended range.

0001: ±5V single-ended range.

0010: ±10V single-ended range.

...

1101: reserved.

1110: reserved.

1111: reserved.

Table 37. Bit Descriptions for RANGE_CH7_CH8

Bits

Bit Name

Description

Reset

Access

[7:4]

CH8_RANGE

Range options for Channel 8.

0x3

R/W

0000: 2.5 V single-ended range.

0001: 5 V single-ended range.

0010: 10 V single-ended range.

0011: 10 V single-ended range.

0100: 10 V single-ended range.

0101: 10 V single-ended range.

0110: 10 V single-ended range.

0111: 10 V single-ended range.

1000: 10 V single-ended range.

1001: 10 V single-ended range.

1010: 10 V single-ended range.

1011: 10 V single-ended range.

1100: reserved.

1101: reserved.

1110: reserved.

1111: reserved.

[3:0]

CH7_RANGE

Range options for Channel 7.

0000: 2.5 V single-ended range.

0001: 5 V single-ended range.

0010: 10 V single-ended range.

0011: 10 V single-ended range.

0100: 10 V single-ended range.

0101: 10 V single-ended range.

0110: 10 V single-ended range.

0111: 10 V single-ended range.

1000: 10 V single-ended range.

1001: 10 V single-ended range.

1010: 10 V single-ended range.

1011: 10 V single-ended range.

1100: reserved.

0x3

R/W

1101: reserved.

1110: reserved.

1111: reserved.

Rev. 0 | Page 54 of 69

Data Sheet

AD7606B

Address: 0x08, Reset: 0x00, Name: OVERSAMPLING

7

6

5

4

3

2

1

0

[7:4] OS_PAD (R/W)

Oversampling padding, extend the

internal oversampling period allowing

evenly spaced sampling between

CONVST rising edges.

[3:0] OS_RATIO (R/W)

Oversampling ratio

0: no oversampling.

1: oversampling by 2.

10: oversampling by 4.

...

1101: oversampling off.

1110: oversampling off.

1111: oversampling off.

Table 38. Bit Descriptions for OVERSAMPLING

Bits Bit Name

Description

Reset Access

[7:4] OS_PAD

Oversampling padding, extend the internal oversampling period allowing evenly spaced sampling

between CONVST rising edges.

0x0

R/W

[3:0] OS_RATIO Oversampling ratio.

0: no oversampling.

0x0

R/W

1: oversampling by 2.

10: oversampling by 4.

11: oversampling by 8.

100: oversampling by 16.

101: oversampling by 32.

110: oversampling by 64.

111: oversampling by 128.

1000: oversampling by 256.

1001: oversampling off.

1010: oversampling off.

1011: oversampling off.

1100: oversampling off.

1101: oversampling off.

1110: oversampling off.

1111: oversampling off.

Address: 0x09, Reset: 0x00, Name: CH1_GAIN

7

6

5

4

3

2

1

0

[7:6] RESERVED

[5:0] CH1_GAIN (R/W)

R_FILTERcalibration register. Resolution:

1024 Ω. Range: 0 Ω to 65,536 Ω

Table 39. Bit Descriptions for CH1_GAIN

Bits

[7:6]

[5:0]

Bit Name

RESERVED

CH1_GAIN

Description

Reserved.

Reset

0x0

Access

R

R/W

R_FILTERcalibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω.

Address: 0x0A, Reset: 0x00, Name: CH2_GAIN

7

6

5

4

3

2

1

0

[7:6] RESERVED

[5:0] CH2_GAIN (R/W)

R_FILTERcalibration register. Resolution:

1024 Ω. Range: 0 Ω to 65,536 Ω

Table 40. Bit Descriptions for CH2_GAIN

Bits

[7:6]

[5:0]

Bit Name

RESERVED

CH2_GAIN

Description

Reserved.

Reset

0x0

Access

R

R/W

R_FILTERcalibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω.

Rev. 0 | Page 55 of 69

AD7606B

Data Sheet

Address: 0x0B, Reset: 0x00, Name: CH3_GAIN

7

6

5

4

3

2

1

0

[7:6] RESERVED

[5:0] CH3_GAIN (R/W)

R_FILTERcalibration register. Resolution:

1024 Ω. Range: 0 Ω to 65,536 Ω

Table 41. Bit Descriptions for CH3_GAIN

Bits

[7:6]

[5:0]

Bit Name

RESERVED

CH3_GAIN

Description

Reserved.

Reset

0x0

Access

R

R/W

R_FILTERcalibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω.

Address: 0x0C, Reset: 0x00, Name: CH4_GAIN

7

6

5

4

3

2

1

0

[7:6] RESERVED

[5:0] CH4_GAIN (R/W)

R_FILTERcalibration register. Resolution:

1024 Ω. Range: 0 Ω to 65,536 Ω

Table 42. Bit Descriptions for CH4_GAIN

Bits

[7:6]

[5:0]

Bit Name

RESERVED

CH4_GAIN

Description

Reserved.

Reset

0x0

Access

R

R/W

R_FILTERcalibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω.

Address: 0x0D, Reset: 0x00, Name: CH5_GAIN

7

6

5

4

3

2

1

0

[7:6] RESERVED

[5:0] CH5_GAIN (R/W)

R_FILTERcalibration register. Resolution:

1024 Ω. Range: 0 Ω to 65,536 Ω

Table 43. Bit Descriptions for CH5_GAIN

Bits

[7:6]

[5:0]

Bit Name

RESERVED

CH5_GAIN

Description

Reserved.

Reset

0x0

Access

R

R/W

R_FILTERcalibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω.

Address: 0x0E, Reset: 0x00, Name: CH6_GAIN

7

6

5

4

3

2

1

0

[7:6] RESERVED

[5:0] CH5_GAIN (R/W)

R_FILTERcalibration register. Resolution:

1024 Ω. Range: 0 Ω to 65,536 Ω

Table 44. Bit Descriptions for CH6_GAIN

Bits

[7:6]

[5:0]

Bit Name

RESERVED

CH6_GAIN

Description

Reserved.

Reset

0x0

Access

R

R/W

R_FILTERcalibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω.

Rev. 0 | Page 56 of 69

Data Sheet

AD7606B

Address: 0x0F, Reset: 0x00, Name: CH7_GAIN

7

6

5

4

3

2

1

0

[7:6] RESERVED

[5:0] CH7_GAIN (R/W)

R_FILTERcalibration register. Resolution:

1024 Ω. Range: 0 Ω to 65,536 Ω

Table 45. Bit Descriptions for CH7_GAIN

Bits

[7:6]

[5:0]

Bit Name

RESERVED

CH7_GAIN

Description

Reserved.

Reset

0x0

Access

R

R/W

R_FILTERcalibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω.

Address: 0x10, Reset: 0x00, Name: CH8_GAIN

7

6

5

4

3

2

1

0

[7:6] RESERVED

[5:0] CH8_GAIN (R/W)

R_FILTERcalibration register. Resolution:

1024 Ω. Range: 0 Ω to 65,536 Ω

Table 46. Bit Descriptions for CH8_GAIN

Bits

[7:6]

[5:0]

Bit Name

RESERVED

CH8_GAIN

Description

Reserved.

Reset

0x0

Access

R

R/W

R_FILTERcalibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω.

Address: 0x11, Reset: 0x80, Name: CH1_OFFSET

7

6

5

4

3

2

1

0

1

0

[7:0] CH1_OFFSET (R/W)

Offset register. Range from –128

LSB to +127 LSB.

Table 47. Bit Descriptions for CH1_OFFSET

Bits Bit Name Description

[7:0] CH1_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;

0xFF = +127 LSB offset.

Reset Access

0x80 R/W

Address: 0x12, Reset: 0x80, Name: CH2_OFFSET

7

6

5

4

3

2

1

0

1

0

[7:0] CH2_OFFSET (R/W)

Offset register. Range from –128

LSB to +127 LSB.

Table 48. Bit Descriptions for CH2_OFFSET

Bits Bit Name Description

[7:0] CH2_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;

0xFF = +127 LSB offset.

Reset Access

0x80 R/W

Rev. 0 | Page 57 of 69

AD7606B

Data Sheet

Address: 0x13, Reset: 0x80, Name: CH3_OFFSET

7

6

5

4

3

2

1

0

1

0

[7:0] CH3_OFFSET (R/W)

Offset register. Range from –128

LSB to +127 LSB.

Table 49. Bit Descriptions for CH3_OFFSET

Bits Bit Name Description

Reset Access

[7:0] CH3_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;

0xFF = +127 LSB offset.

0x80

R/W

Address: 0x14, Reset: 0x80, Name: CH4_OFFSET

7

6

5

4

3

2

1

0

1

0

[7:0] CH4_OFFSET (R/W)

Offset register. Range from –128

LSB to +127 LSB.

Table 50. Bit Descriptions for CH4_OFFSET

Bits Bit Name Description

[7:0] CH4_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;

0xFF = +127 LSB offset.

Reset Access

0x80 R/W

Address: 0x15, Reset: 0x80, Name: CH5_OFFSET

7

6

5

4

3

2

1

0

1

0

[7:0] CH5_OFFSET (R/W)

Offset register. Range from –128

LSB to +127 LSB.

Table 51. Bit Descriptions for CH5_OFFSET

Bits Bit Name Description

[7:0] CH5_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;

0xFF = +127 LSB offset.

Reset Access

0x80 R/W

Address: 0x16, Reset: 0x80, Name: CH6_OFFSET

7

6

5

4

3

2

1

0

1

0

[7:0] CH6_OFFSET (R/W)

Offset register. Range from –128

LSB to +127 LSB.

Table 52. Bit Descriptions for CH6_OFFSET

Bits Bit Name Description

[7:0] CH6_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;

0xFF = +127 LSB offset.

Reset Access

0x80 R/W

Rev. 0 | Page 58 of 69

Data Sheet

AD7606B

Address: 0x17, Reset: 0x80, Name: CH7_OFFSET

7

6

5

4

3

2

1

0

1

0

[7:0] CH7_OFFSET (R/W)

Offset register. Range from –128

LSB to +127 LSB.

Table 53. Bit Descriptions for CH7_OFFSET

Bits Bit Name Description

Reset Access

[7:0] CH7_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;

0xFF = +127 LSB offset.

0x80

R/W

Address: 0x18, Reset: 0x80, Name: CH8_OFFSET

7

6

5

4

3

2

1

0

1

0

[7:0] CH8_OFFSET (R/W)

Offset register. Range from –128

LSB to +127 LSB.

Table 54. Bit Descriptions for CH8_OFFSET

Bits Bit Name Description

Reset Access

[7:0] CH8_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;

0xFF = +127 LSB offset.

0x80

R/W

Address: 0x19, Reset: 0x00, Name: CH1_PHASE

7

6

5

4

3

2

1

0

[7:0] CH1_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75

µs in steps of 1.25 µs

Table 55. Bit Descriptions for CH1_PHASE

Bits

Bit Name

Description

Reset

Access

[7:0]

CH1_PHASE_OFFSET

Phase delay from 0 to 318.75 μs in steps of 1.25 μs.

0x0

R/W

Address: 0x1A, Reset: 0x00, Name: CH2_PHASE

7

6

5

4

3

2

1

0

[7:0] CH2_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75

µs in steps of 1.25 µs

Table 56. Bit Descriptions for CH2_PHASE

Bits

Bit Name

Description

Reset

Access

[7:0]

CH2_PHASE_OFFSET

Phase delay from 0 to 318.75 μs in steps of 1.25 μs.

0x0

R/W

Address: 0x1B, Reset: 0x00, Name: CH3_PHASE

7

6

5

4

3

2

1

0

[7:0] CH3_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75

µs in steps of 1.25 µs

Table 57. Bit Descriptions for CH3_PHASE

Bits

Bit Name

Description

Reset

Access

[7:0]

CH3_PHASE_OFFSET

Phase delay from 0 to 318.75 μs in steps of 1.25 μs.

0x0

R/W

Rev. 0 | Page 59 of 69

AD7606B

Data Sheet

Address: 0x1C, Reset: 0x00, Name: CH4_PHASE

7

6

5

4

3

2

1

0

[7:0] CH4_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75

µs in steps of 1.25 µs

Table 58. Bit Descriptions for CH4_PHASE

Bits

Bit Name

Description

Reset

Access

[7:0]

CH4_PHASE_OFFSET

Phase delay from 0 to 318.75 μs in steps of 1.25 μs.

0x0

R/W

Address: 0x1D, Reset: 0x00, Name: CH5_PHASE

7

6

5

4

3

2

1

0

[7:0] CH5_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75

µs in steps of 1.25 µs

Table 59. Bit Descriptions for CH5_PHASE

Bits

Bit Name

Description

Reset

Access

[7:0]

CH5_PHASE_OFFSET

Phase delay from 0 to 318.75 μs in steps of 1.25 μs.

0x0

R/W

Address: 0x1E, Reset: 0x00, Name: CH6_PHASE

7

6

5

4

3

2

1

0

[7:0] CH6_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75

µs in steps of 1.25 µs

Table 60. Bit Descriptions for CH6_PHASE

Bits

Bit Name

Description

Reset

Access

[7:0]

CH6_PHASE_OFFSET

Phase delay from 0 to 318.75 μs in steps of 1.25 μs.

0x0

R/W

Address: 0x1F, Reset: 0x00, Name: CH7_PHASE

7

6

5

4

3

2

1

0

[7:0] CH7_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75

µs in steps of 1.25 µs

Table 61. Bit Descriptions for CH7_PHASE

Bits

Bit Name

Description

Reset

Access

[7:0]

CH7_PHASE_OFFSET

Phase delay from 0 to 318.75 μs in steps of 1.25 μs.

0x0

R/W

Address: 0x20, Reset: 0x00, Name: CH8_PHASE

7

6

5

4

3

2

1

0

[7:0] CH8_PHASE_OFFSET (R/W)

Phase delay from 0 µs to 318.75

µs in steps of 1.25 µs

Table 62. Bit Descriptions for CH8_PHASE

Bits

Bit Name

Description

Reset

Access

[7:0]

CH8_PHASE_OFFSET

Phase delay from 0 to 318.75 μs in steps of 1.25 μs.

0x0

R/W

Rev. 0 | Page 60 of 69

Data Sheet

AD7606B

Address: 0x21, Reset: 0x01, Name: DIGITAL_DIAG_ENABLE

7

6

5

4

3

2

1

0

1

[7] INTERFACE_CHECK_EN (R/W)

Enable interface check. Provides

a fixed data on each channel when

reading ADC data

[0] ROM_CRC_ERR_EN (R/W)

Enable ROM CRC check

[1] MM_CRC_ERR_EN (R/W)

Enable memory map CRC check

[6] CLK_FS_OS_COUNTER_EN (R/W)

Enable FS and OS clock counter

[2] INT_CRC_ERR_EN (R/W)

Enable interface CRC check

[5] BUSY_STUCK_HIGH_ERR_EN (R/W)

Enable busy stuck high check

[3] SPI_WRITE_ERR_EN (R/W)

Enable checking if attempting to write

to an invalid address

[4] SPI_READ_ERR_EN (R/W)

Enable checking if attempting to read

from an invalid address

Table 63. Bit Descriptions for DIGITAL_DIAG_ENABLE

Bits Bit Name

Description

Reset Access

7

INTERFACE_CHECK_EN

Enable interface check. Provides a fixed data on each channel when reading ADC

data.

0x0

R/W

6

5

4

3

2

1

0

CLK_FS_OS_COUNTER_EN

BUSY_STUCK_HIGH_ERR_EN Enable busy stuck high check.

Enable FS and OS clock counter.

0x0

0x1

R/W

SPI_READ_ERR_EN

SPI_WRITE_ERR_EN

INT_CRC_ERR_EN

MM_CRC_ERR_EN

ROM_CRC_ERR_EN

Enable checking if attempting to read from an invalid address.

Enable checking if attempting to write to an invalid address.

Enable interface CRC check.

Enable memory map CRC check.

Enable ROM CRC check.

Address: 0x22, Reset: 0x00, Name: DIGITAL_DIAG_ERR

7

6

5

4

3

2

1

0

[7:6] RESERVED

[0] ROM_CRC_ERR (R/W1C)

ROM CRC error

[5] BUSY_STUCK_HIGH_ERR (R/W1C)

Busy stuck high error. Busy line has

been at high logic level for longer

than 4us

[1] MM_CRC_ERR (R/W1C)

Memory map CRC error

[2] INT_CRC_ERR (R/W1C)

[4] SPI_READ_ERR (R/W1C)

Interface CRC error

SPI invalid read address

[3] SPI_WRITE_ERR (R/W1C)

SPI invalid write address

Table 64. Bit Descriptions for DIGITAL_DIAG_ERR

Bits

Bit Name

Description

Reset Access

[7:6] RESERVED

Reserved.

0x0

R

5

4

3

2

1

0

BUSY_STUCK_HIGH_ERR

Busy stuck high error. Busy line has been at high logic level for longer than 4 μs.

R/W1C

SPI_READ_ERR

SPI_WRITE_ERR

INT_CRC_ERR

MM_CRC_ERR

ROM_CRC_ERR

SPI invalid read address.

SPI invalid write address.

Interface CRC error.

Memory map CRC error.

ROM CRC error.

Rev. 0 | Page 61 of 69

AD7606B

Data Sheet

Address: 0x23, Reset: 0x00, Name: OPEN_DETECT_ENABLE

7

6

5

4

3

2

1

0

[7] CH8_OPEN_DETECT_EN (R/W)