EVAL-ADCMP573BCPZ [ADI]
Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators; 超快3.3 V / 5 V单电源比较器的SiGe
| 型号： | EVAL-ADCMP573BCPZ |
| 厂家： | 
ADI |
| 描述： | Ultrafast 3.3 V/5 V Single-Supply SiGe Comparators |
| 文件： | 总16页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultrafast 3.3 V/5 V
Single-Supply SiGe Comparators
ADCMP572/ADCMP573
FUNCTIONAL BLOCK DIAGRAM
FEATURES
3.3 V/5.2 V single-supply operation
150 ps propagation delay
V
V
CCO
CCI
V
TERMINATION
15 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
80 ps minimum pulse width
TP
V
NONINVERTING
INPUT
P
Q OUTPUT
Q OUTPUT
ADCMP572
ADCMP573
CML/
RSPECL
35 ps typical output rise/fall
10 ps deterministic jitter (DJ)
V
INVERTING
INPUT
N
200 fs random jitter (RJ)
V
TERMINATION
TN
On-chip terminations at both input pins
Robust inputs with no output phase reversal
Resistor-programmable hysteresis
Differential latch control
LE INPUT
LE INPUT
HYS
Figure 1.
Extended industrial −40°C to +125°C temperature range
APPLICATIONS
Clock and data signal restoration and level shifting
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
GENERAL DESCRIPTION
The ADCMP572 and ADCMP573 are ultrafast comparators
fabricated on Analog Devices’ proprietary XFCB3 Silicon
Germanium (SiGe) bipolar process. The ADCMP572 features
CML output drivers and latch inputs, and the ADCMP573
features reduced swing PECL (RSPECL) output drivers and
latch inputs.
provided at both inputs with the optional capability to be left
open (on an individual pin basis) for applications requiring
high impedance inputs.
The CML output stage is designed to directly drive 400 mV into
50 Ω transmission lines terminated to between 3.3 V to 5.2 V.
The RSPECL output stage is designed to drive 400 mV into
50 Ω terminated to VCCO − 2 V and is compatible with several
commonly used PECL logic families. The comparator input
stage offers robust protection against large input overdrive, and
the outputs do not phase reverse when the valid input signal
range is exceeded. High speed latch and programmable
hysteresis features are also provided.
Both devices offer 150 ps propagation delay and 80 ps
minimum pulse width for 10 Gbps operation with 200 fs rms
random jitter (RJ). Overdrive and slew rate dispersion are
typically less than 15 ps.
A flexible power supply scheme allows both devices to operate
with a single 3.3 V positive supply and a −0.2 V to +1.2 V input
signal range or with split input/output supplies to support a
wider −0.2 V to +3.2 V input signal range and an independent
range of output levels. 50 Ω on-chip termination resistors are
The ADCMP572 and ADCMP573 are available in a 16-lead
LFCSP package and have been characterized over an extended
industrial temperature range of −40°C to +125°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result fromits use. Specifications subject to change without notice. No
licenseis granted byimplication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2009 Analog Devices, Inc. All rights reserved.
ADCMP572/ADCMP573
TABLE OF CONTENTS
Electrical Characteristics................................................................. 3
Using/Disabling the Latch Feature..............................................9
Optimizing High Speed Performance ..................................... 10
Comparator Propagation Delay Dispersion ........................... 10
Comparator Hysteresis .............................................................. 11
Minimum Input Slew Rate Requirements .............................. 11
Typical Application Circuits ......................................................... 12
Timing Information ....................................................................... 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Absolute Maximum Ratings............................................................ 5
Thermal Considerations.............................................................. 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Application Information.................................................................. 9
Power/Ground Layout and Bypassing....................................... 9
CML/RSPECL Output Stage....................................................... 9
REVISION HISTORY
4/09—Rev. 0 to Rev. A
Changes to Figure 26...........................................................................12
Updated Outline Dimensions............................................................14
Changes to Ordering Guide ...............................................................14
4/05—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADCMP572/ADCMP573
ELECTRICAL CHARACTERISTICS
VCCI = VCCO = 3.3 V, TA = −40°C to +125°C, typical at TA = +25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
DC INPUT CHARACTERISTICS
Input Voltage Range
VP, VN
VCCI = 3.3 V, VCCO = 3.3 V
VCCI = 5.2 V, VCCO = 3.3 V
−0.2
−0.2
−1.2
−5.0
+1.2
+3.1
+1.2
+5.0
V
V
V
Input Differential Voltage
Input Offset Voltage
Offset Voltage Tempco
Input Bias Current
Input Bias Current Tempco
Input Offset Current
Input Impedance
VOS
∆VOS/dT
IP, IN
2.0
10.0
−25.0
50.0
2.0
mV
μV/°C
μA
nA/°C
μA
Ω
Open termination
−50.0
0.0
50
Input Resistance, Differential
Input Resistance, Common-Mode
Active Gain
Open termination
Open termination
50
500
54
kΩ
kΩ
dB
dB
AV
CMRR
Common-Mode Rejection
VCCI = 3.3 V, VCCO = 3.3 V,
65
V
CM = 0.0 V to 1.0 V
VCCI = 5.2 V, VCCO = 3.3 V,
CM = 0.0 V to 3.0 V
65
dB
V
Power Supply Rejection—VCCI
Hysteresis
PSRVCCI
VCCI = 3.3 V 5ꢀ, VCCO = 3.3 V
RHYS = ∞
74
1
dB
mV
LATCH ENABLE CHARACTERISTICS
ADCMP572
Latch Enable Input Range
Latch Enable Input Differential
Latch Setup Time
2.8
0.2
VCCO + 0.2
0.5
V
V
ps
ps
0.4
15
5
tS
tH
VOD = 100 mV
VOD = 100 mV
Latch Hold Time
ADCMP573
Latch Enable Input Range
Latch Enable Input Differential
Latch Setup Time
1.8
0.2
VCCO − 0.6
0.5
V
V
0.4
90
100
50.0
150
100
tS
tH
VOD = 100 mV
VOD = 100 mV
ps
ps
Ω
ps
ps
Latch Hold Time
Latch Enable Input Impedance
Latch to Output Delay
Latch Minimum Pulse Width
DC OUTPUT CHARACTERISTICS
ADCMP572 (CML)
tPLOH, tPLOL
tPL
VOD = 100 mV
VOD = 100 mV
Output Impedance
ZOUT
VOH
VOL
−8 mA < IOUT < 8 mA
50 Ω terminate to VCCO
50 Ω terminate to VCCO
50 Ω terminate to VCCO
50.0
Ω
V
V
mV
Output Voltage High Level
Output Voltage Low Level
Output Voltage Differential
ADCMP573 (RSPECL)
VCCO − 0.10 VCCO − 0.05 VCCO
VCCO − 0.60 VCCO − 0.45 VCCO − 0.30
300
375
450
Output Voltage High −40°C
Output Voltage High +25°C
Output Voltage High +125°C
Output Voltage Low −40°C
Output Voltage Low +25°C
Output Voltage Low +125°C
Output Voltage Differential
VOH
VOH
VOH
VOL
VOL
VOL
50 Ω terminate to VCCO − 2.0
50 Ω terminate to VCCO − 2.0
50 Ω terminate to VCCO − 2.0
50 Ω terminate to VCCO − 2.0
50 Ω terminate to VCCO − 2.0
50 Ω terminate to VCCO − 2.0
50 Ω terminate to VCCO − 2.0
VCCO − 1.14 VCCO − 1.02 VCCO − 0.90
VCCO − 1.10 VCCO − 0.98 VCCO − 0.86
VCCO − 1.04 VCCO − 0.92 VCCO − 0.80
VCCO − 1.54 VCCO − 1.39 VCCO − 1.24
VCCO − 1.50 VCCO − 1.35 VCCO − 1.20
VCCO − 1.44 VCCO − 1.29 VCCO − 1.14
V
V
V
V
V
V
mV
300
375
450
Rev. A | Page 3 of 16
ADCMP572/ADCMP573
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
AC PERFORMANCE
Propagation Delay
tPD
VCCI = 3.3 V, VOD = 200 mV
VCCI = 3.3 V, VOD = 20 mV
VCCI = 5.2 V, VOD = 200 mV
150
165
145
0.5
ps
ps
ps
ps/°C
ps
Propagation Delay Tempco
Prop Delay Skew—Rising Transition
to Falling Transition
∆tPD/dT
VOD = 200 mV, 5 V/ns
10
Overdrive Dispersion
50 mV < VOD < 0.2 V, 5 V/ns
10 mV < VOD < 0.2 V, 5 V/ns
2 V/ns to 10 V/ns, 250 mV OD
100 ps to 5 ns, 250 mV OD
VCCI = 3.3 V, 1 V/ns, 250 mV OD
VCCI = 5.2 V, 1 V/ns, 250 mV OD
VOD = 0.2 V, 0.0 V < VCM < 2.9 V
0.0 V to 250 mV input
tR = tF = 17 ps, 20/80
>50% Output Swing
VOD = 200 mV, 5 V/ns,
PRBS31 − 1 NRZ, 4 Gbps
15
15
15
5
5
10
5
ps
ps
ps
ps
ps
Slew Rate Dispersion
Pulse Width Dispersion
10% – 90% Duty Cycle Dispersion
Common-Mode Dispersion
Equivalent Input Bandwidth1
ps/V
GHz
BWEQ
DJ
8.0
Toggle Rate
Deterministic Jitter
12.5
10
Gbps
ps
VOD = 200 mV, 5 V/ns,
20
ps
PRBS31 − 1 NRZ, 10 Gbps
RMS Random Jitter
Minimum Pulse Width
RJ
VOD = 200 mV, 5 V/ns, 1.25 GHz
∆tPD/∆PW < 5 ps, 200 mV OD
∆tPD/∆PW < 10 ps, 200 mV OD
20/80
0.2
100
80
35
35
ps
ps
ps
ps
ps
PWMIN
PWMIN
tR
Rise Time
Fall Time
tF
20/80
POWER SUPPLY
Input Supply Voltage Range
Output Supply Voltage Range
Positive Supply Differential
ADCMP572 (CML)
VCCI
VCCO
VCCI −VCCO
3.1
3.1
−0.2
5.4
5.4
+2.3
V
V
V
Positive Supply Current
IVCCI + IVCCO
VCCI = 3.3 V, VCCO = 3.3 V,
terminate 50 Ω to VCCO
44
52
mA
VCCI = 5.2 V, VCCO = 5.2 V,
terminate 50 Ω to VCCO
44
52
Device Power Dissipation
PD
VCCI = 3.3 V, VCCO = 3.3 V,
terminate 50 Ω to VCCO
VCCI = 5.2 V, VCCO = 5.2 V,
terminate 50 Ω to VCCO
140
230
165
265
mW
ADCMP573 (RSPECL)
Positive Supply Current
IVCCI + IVCCO
VCCI = 3.3 V, VCCO = 3.3 V,
50 Ω to VCCO − 2 V
62
80
mA
VCCI = 5.2 V, VCCO = 5.2 V,
50 Ω to VCCO – 2 V
64
80
Device Power Dissipation
PD
VCCI = 3.3 V, VCCO = 3.3 V,
50 Ω to VCCO − 2 V
VCCI = 5.2 V, VCCO = 5.2 V,
50 Ω to VCCO − 2 V
110
146
160
230
mW
1 Equivalent input bandwidth assumes a simple first-order response and is calculated with the following formula: BWEQ = 0.22/√(trCOMP2−trIN2), where trIN is the 20/80
transition time of a quasi-Gaussian signal applied to the comparator input, and trCOMP is the effective transition time digitized by the comparator.
Rev. A | Page 4 of 16
ADCMP572/ADCMP573
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
SUPPLY VOLTAGE
Input Supply Voltage
(VCCI to GND)
Output Supply Voltage
(VCCO to GND)
Positive Supply Differential
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.5 V to +6.0 V
−0.5 V to +6.0 V
−0.5 V to +3.5 V
(VCCI − VCCO
)
INPUT VOLTAGE
THERMAL CONSIDERATIONS
Input Voltage
−0.5 V to VCCI + 0.5 V
(VCCI + 0.5 V)
−0.5 V to VCCO + 0.5 V
Differential Input Voltage
Input Voltage, Latch Enable
HYSTERESIS CONTROL PIN
Applied Voltage (HYS to GND)
Maximum Input/Output Current
OUTPUT CURRENT
The ADCMP572/ADCMP573 LFCSP 16-lead package has a θJA
(junction-to-ambient thermal resistance) of 70°C/W in still air.
−0.5 V to +1.5 V
1 mA
ADCMP572 (CML)
20 mA
ADCMP573 (RSPECL)
−35 mA
TEMPERATURE
Operating Temperature, Ambient
Operating Temperature, Junction
Storage Temperature Range
−40°C to +125°C
+150°C
−65°C to +150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 16
ADCMP572/ADCMP573
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
16
15
14
13
PIN1
1
2
3
4
12
V
CCO
V
TP
ADCMP572
ADCMP573
TOP VIEW
(Not to Scale)
V
V
11
10
9
Q
Q
P
N
V
V
CCO
TN
5
6
7
8
Figure 2. ADCMP572/ADCMP573 Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
VTP
VP
Termination Resistor Return Pin for VP Input.
Noninverting Analog Input.
3
VN
Inverting Analog Input.
4
5, 16
6
VTN
VCCI
LE
Termination Resistor Return Pin for VN Input.
Positive Supply Voltage for Input Stage.
Latch Enable Input Pin, Inverting Side.
In compare mode (LE = low), the output tracks changes at the input of the comparator.
In latch mode (LE = high), the output reflects the input state just prior to the comparator’s being placed
into latch mode. LE must be driven in complement with LE.
7
8
LE
Latch Enable Input Pin, Noninverting Side.
In compare mode (LE = high), the output tracks changes at the input of the comparator.
In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being placed
into latch mode. LE must be driven in complement with LE.
VCCO/VTT
Termination Return Pin for the LE/LE Input Pins.
For the ADCMP572 (CML output stage), this pin is internally connected to and also should be externally
connected to the positive VCCO supply.
For the ADCMP573 (RSPECL output stage), this pin should normally be connected to the VCCO – 2 V
termination potential.
9, 12
13, 15
10
VCCO
GND
Q
Positive Supply Voltage for the CML/RSPECL Output Stage.
Ground.
Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE
descriptions (Pins 6 and 7) for more information.
11
14
Q
Noninverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater
than the analog voltage at the inverting input, VN, provided the comparator is in compare mode.
See the LE/LE descriptions (Pins 6 and 7) for more information.
HYS
N/C
Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a suitably
sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of RHYS
hysteresis control resistor.
The metallic back surface of the package is not electrically connected to any part of the circuit, and it
can be left floating for best electrical isolation between the package handle and the substrate of the
die. However, it can be soldered to the application board if improved thermal and/or mechanical
stability is desired. Exposed metal at package corners is connected to the heat sink paddle.
Isolated
Heat Sink
Rev. A | Page 6 of 16
ADCMP572/ADCMP573
TYPICAL PERFORMANCE CHARACTERISTICS
VCCI = VCCO = 3.3 V, TA = 25°C, unless otherwise noted.
20
39.0
38.5
38.0
37.5
37.0
36.5
36.0
15
10
5
0
–60
–40
–20
0
20
40
60
80
100
0
50
100
150
200
250
INPUT OVERDRIVE VOLTAGE (mV)
TEMPERATURE (°C)
Figure 3. Propagation Delay vs. Input Overdrive
Figure 6. Rise/Fall Time vs. Temperature
158.5
158.0
157.5
157.0
156.5
156.0
155.5
60
50
40
30
20
10
0
0
0.2
0.4
0.6
0.8
1.0
1.2
0
1
2
3
4
5
6
INPUT COMMON-MODE VOLTAGE (V)
R
(kΩ)
HYS
Figure 7. Hysteresis vs. RHYS Control Resistor
Figure 4. Propagation Delay vs. Input Common-Mode
80
160
158
156
154
152
150
148
146
70
60
50
40
30
20
10
0
–600
–500
–400
–300
–200
–100
0
–60
–40
–20
0
20
40
60
80
100
R
SINK CURRENT (μA)
HYS
TEMPERATURE (°C)
Figure 5. Propagation Delay vs. Temperature
Figure 8. Hysteresis vs. RHYS Sink Current
Rev. A | Page 7 of 16
ADCMP572/ADCMP573
–15.0
–15.5
–16.0
–16.5
–17.0
–17.5
–18.0
–18.5
380
379
378
377
376
375
374
373
–60
–40
–20
0
20
40
60
80
100
–0.5 –0.3 –0.1 0.1
0.3
0.5
0.7
0.9
1.1
1.3
1.5
V
INPUT VOLTAGE (V
=
N
–0.2V)
TEMPERATURE (°C)
P
Figure 12. Output Levels vs. Temperature
Figure 9. Input Bias Current vs. Input Differential
–16.2
–16.3
–16.4
–16.5
–16.6
–16.7
–16.8
–16.9
496.0mV
M1
504.0mV
60.00ps/DIV
–60
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 13. ADCMP572 Eye Diagram at 2.5 Gbps
Figure 10. Input Bias Current vs. Temperature
0.5
500.0mV
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
500.0mV
25.00ps/DIV
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 11. Input Offset Voltage vs. Temperature
Figure 14. ADCMP572 Eye Diagram at 6.5 Gbps
Rev. A | Page 8 of 16
ADCMP572/ADCMP573
APPLICATION INFORMATION
microstrip or strip line techniques are essential to ensure proper
transition times and to prevent output ringing and pulse width
dependent propagation delay dispersion. For the most timing
critical applications where transmission line reflections pose the
greatest risk to performance, the ADCMP572 provides the best
match to 50 Ω output transmission paths.
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP572/ADCMP573 comparators are very high speed
SiGe devices. Consequently, it is essential to use proper high
speed design techniques to achieve the specified performance.
Of critical importance is the use of low impedance supply
planes, particularly the output supply plane (VCCO) and the
ground plane (GND). Individual supply planes are recom-
mended as part of a multilayer board. Providing the lowest
inductance return path for switching currents ensures the best
possible performance in the target application.
V
CCO
50Ω
Q
Q
It is important to adequately bypass the input and output
supplies. A 1 μF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the VCCI and VCCO
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be avoided to maximize the
effectiveness of the bypass at high frequencies.
16mA
GND
Figure 15. Simplified Schematic Diagram of
the ADCMP572 CML Output Stage
If the input and output supplies are connected separately such
that VCCI ≠ VCCO, care should be taken to bypass each of these
supplies separately to the GND plane. A bypass capacitor
should not be connected between them. It is recommended that
the GND plane separate the VCCI and VCCO planes when the
circuit board layout is designed to minimize coupling between
the two supplies and to take advantage of the additional bypass
capacitance from each respective supply to the ground plane.
This enhances the performance when split input/output
supplies are used. If the input and output supplies are connected
V
CCO
Q
Q
together for single-supply operation such that VCCI = VCCO
,
coupling between the two supplies is unavoidable; however,
every effort should be made to keep the supply plane adjacent
to the GND plane to maximize the additional bypass
capacitance this arrangement provides.
GND
Figure 16. Simplified Schematic Diagram of
the ADCMP573 RSPECL Output Stage
CML/RSPECL OUTPUT STAGE
USING/DISABLING THE LATCH FEATURE
Specified propagation delay dispersion performance can be
achieved only by using proper transmission line terminations.
The outputs of the ADCMP572 are designed to directly drive
400 mV into 50 Ω cable, microstrip, or strip line transmission
lines properly terminated to the VCCO supply plane. The CML
output stage is shown in the simplified schematic diagram of
Figure 15. The outputs are each back terminated with 50 Ω for
best transmission line matching. The RSPECL outputs of the
ADCMP573 are illustrated in Figure 16 and should be
LE
The latch inputs (LE/ ) are active low for latch mode and are
internally terminated with 50 Ω resistors to Pin 8. This pin
corresponds to and is internally connected to the VCCO supply
for the CML-compatible ADCMP572. With the aid of these
resistors the ADCMP572 latch function can be disabled by
LE
connecting the
resistor and leaving the LE pin unconnected. To avoid excessive
power dissipation, the resistor should be 750 Ω when VCCO
pin to GND with an external pull-down
=
3.3 V, and 1.2 kΩ when VCCO = 5.2 V. In the PECL-compatible
ADCMP573, the VTT pin should be connected externally to the
PECL termination supply at VCCO – 2 V. The latch can then be
disabled by connecting the LE pin to VCCO with an external
terminated to VCCO − 2 V. As an alternative, Thevenin
equivalent termination networks can be used in either case if
the direct termination voltage is not readily available. If high
speed output signals must be routed more than a centimeter,
Rev. A | Page 9 of 16
ADCMP572/ADCMP573
LE
500 Ω resistor and leaving the
pin disconnected. In this case,
COMPARATOR PROPAGATION
DELAY DISPERSION
the resistor value does not depend on the VCCO supply voltage.
The ADCMP572/ADCMP573 comparators are designed to
reduce propagation delay dispersion over a wide input overdrive
range of 5 mV to 500 mV. Propagation delay dispersion is
variation in the propagation delay that results from a change in
the degree of overdrive or slew rate (how far or how fast the
input signal exceeds the switching threshold).
VCCO is the signal return for the output stage and VCCO pins
should of course be connected to a supply plane for maximum
performance.
OPTIMIZING HIGH SPEED PERFORMANCE
As with any high speed comparator, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power and ground
impedances, or other layout issues can severely limit
performance and often cause oscillation. Discontinuities along
input and output transmission lines can severely limit the
specified pulse width dispersion performance.
Propagation delay dispersion is a specification that becomes
important in high speed, time-critical applications such as data
communication, automatic test and measurement, instrumenta-
tion, and event driven applications such as pulse spectroscopy,
nuclear instrumentation, and medical imaging. Dispersion is
defined as the variation in propagation delay as the input over-
drive conditions vary (Figure 17 and Figure 18). For the
ADCMP572/ADCMP573, dispersion is typically <15 ps
because the overdrive varies from 10 mV to 500 mV, and the
input slew rate varies from 2 V/ns to 10 V/ns. This specification
applies for both positive and negative signals since the
ADCMP572/ADCMP573 has substantially equal delays for
either positive going or negative going inputs.
For applications working in a 50 Ω environment, input and
output matching has a significant impact on data dependent (or
deterministic) jitter (DJ) and on pulse width dispersion
performance. The ADCMP572/ADCMP573 comparators
provide internal 50 Ω termination resistors for both the VP and
VN inputs, and the ADCMP572 provides 50 Ω back terminated
outputs. The return side for each input termination is pinned
out separately with the VTP and VTN pins, respectively. If a 50 Ω
termination is desired at one or both of the VP/VN inputs, then
the VTP and VTN pins can be connected (or disconnected) to
(from) the desired termination potential as required. The
termination potential should be carefully bypassed using high
quality bypass capacitors as discussed earlier to prevent
undesired aberrations on the input signal due to parasitic
inductance in the circuit board layout. If a 50 Ω input
termination is not desired, either one or both of the VTP/VTN
termination pins can be left disconnected. In this case, the pins
should be left floating with no external pull-downs or bypassing
capacitors.
500mV OVERDRIVE
INPUT VOLTAGE
10mV OVERDRIVE
± V
V
N
OS
DISPERSION
Q/Q OUTPUT
Figure 17. Propagation Delay—Overdrive Dispersion
When leaving an input termination disconnected, the internal
resistor acts as a small stub on the input transmission path and
can cause problems for very high speed inputs. Reflections
should then be expected from the comparator inputs because
they no longer provide matched impedance to the input path
leading to the device. In this case, it is important to back match
the drive source impedance to the input transmission path to
minimize multiple reflections. For applications in which the
comparator is very close to the driving signal source, the source
impedance should be minimized. High source impedance in
combination with parasitic input capacitance of the comparator
might cause an undesirable degradation in bandwidth at the
input, therefore degrading the overall response. Although the
ADCMP572/ADCMP573 comparators have been designed to
minimize input capacitance, some parasitic capacitance is
inevitable. It is therefore recommended that the drive source
impedance be no more than 50 Ω for best high speed
performance.
INPUT VOLTAGE
1V/ns
V
± V
OS
N
10V/ns
DISPERSION
Q/Q OUTPUT
Figure 18. Propagation Delay—Slew Rate Dispersion
Rev. A | Page 10 of 16
ADCMP572/ADCMP573
applied as a function of external resistor value. The advantages
of applying hysteresis in this manner are improved accuracy,
stability, and reduced component count. An external bypass
capacitor is not recommended on the HYS pin because it would
likely degrade the jitter performance of the device. The
hysteresis pin could also be driven by a CMOS DAC. It is biased
to approximately 250 mV and has an internal series resistance
of 600 Ω.
COMPARATOR HYSTERESIS
The addition of hysteresis to a comparator is often desirable in a
noisy environment or when the differential input amplitudes are
relatively small or slow moving, but excessive hysteresis has a
cost in degraded accuracy and slew-induced timing shifts. The
transfer function for a comparator with hysteresis is shown in
Figure 19. If the input voltage approaches the threshold (0.0 V
in this example) from the negative direction, the comparator
switches from low to high when the input crosses +VH/2. The
new switching threshold becomes −VH/2. The comparator
remains in the high state until the threshold −VH/2 is crossed
from the positive direction. In this manner, noise centered on
0.0 V input does not cause the comparator to switch states
unless it exceeds the region bounded by VH/2.
60
50
40
30
20
10
0
OUTPUT
V
OH
0
1
2
3
4
5
6
R
(kΩ)
HYS
V
OL
Figure 20. Hysteresis vs. RHYS Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENTS
INPUT
0
–V
2
+V
2
H
H
As with all high speed comparators, a minimum slew rate
requirement must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This
oscillation is due in part to the high input bandwidth of the
comparator and the feedback parasitics inherent in the package.
A minimum slew rate of 50 V/μs should ensure clean output
transitions from the ADCMP572/ADCMP573 comparators.
Figure 19. Comparator Hysteresis Transfer Function
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to the
input. A limitation of this approach is that the amount of
hysteresis varies with the output logic levels, resulting in
hysteresis that can be load dependent and is not symmetrical
about the threshold. The external feedback network can also
introduce significant parasitics, which reduce high speed
performance and can even induce oscillation in some cases.
The slew rate may be too slow for other reasons. The extremely
high bandwidth of these devices means that broadband noise
can be a significant factor when input slew rates are low. There
will be at least 120 μv of thermal noise generated over the full
comparator bandwidth by two 50 Ω terminations at room
temperature. With a slew rate of only 50 V/μs the input will be
inside this noise band for over 2 ps, rendering the comparator’s
jitter performance of 200 fs moot. Raising the slew rate of the
input signal and/or reducing the bandwidth over which this
resistance is seen at the input can greatly reduce jitter.
The ADCMP572/ADCMP573 comparators offer a program-
mable hysteresis feature that can significantly improve the
accuracy and stability of the desired hysteresis. By connecting
an external pull-down resistor from the HYS pin to GND, a
variable amount of hysteresis can be applied. Leaving the HYS
pin disconnected disables the feature, and hysteresis is then less
than 1 mV as specified. The maximum hysteresis that can be
applied using this method is approximately 25 mV with the
pin grounded. Figure 20 illustrates the amount of hysteresis
Rev. A | Page 11 of 16
ADCMP572/ADCMP573
TYPICAL APPLICATION CIRCUITS
3.3V
V
CCI
V
= 3.3V
5V
CCO
50Ω
50Ω
V
TP
75Ω
V
V
P
Q
Q
V
IN
100Ω
100Ω
N ADCMP572
ADCMP572
V
TN
50Ω
50Ω
LATCH
INPUTS
LATCH
INPUTS
Figure 21. Zero-Crossing Detector with 3.3 V CML Outputs
Figure 25. Interfacing 3.3 V CML to a 50 Ω
Ground Terminated Instrument
V
V
= 5.2V
CCI
CCI
V
= 3.3V
V
CCO
CCO
V
CCO
V
TP
50Ω
50Ω
50Ω
50Ω
V
V
P
Q
Q
V
V
V
V
P
P
ADCMP572
N ADCMP572
N
N
V
V
CCO
TN
1.35kΩ
LATCH
INPUTS
Figure 22. LVDS to 50 Ω Back Terminated RSPECL Receiver
Figure 26. Disabling the ADCMP572 Latch Feature
V
= 3.3V
V
= 5.2V = V
CCI CCO
CCI
V
= 2.5V/3.3V
2.5V/3.3V
50Ω 50Ω
CCO
+
Q
Q
V
V
IN
P
ADCMP572
ADCMP573
V
V
–
TH
N
50Ω
50Ω
V
= 3.2V
TT
500Ω
LATCH
INPUTS
V
CCO
GND = –1V
Figure 23. Comparator with 1 V Input Range and
2.5 V or 3.3 V CML Outputs
Figure 27. Disabling the ADCMP573 Latch Feature
V
= 5.2V
V
CCI
CCI
V
= 3.3V/5.2V
3.3V/5.2V
50Ω 50Ω
V
V
CCO
CCO
CCO
50Ω
50Ω
Q
Q
V
IN
ADCMP572
ADCMP572
V
TH
HYS
0Ω TO 5kΩ
LATCH
INPUTS
Figure 28. Adding Hysteresis Using the HYS Control Pin
Figure 24. Comparator with 0 V to 3 V Input Range and
3.3 V or 5.2 V Positive CML Outputs
Rev. A | Page 12 of 16
ADCMP572/ADCMP573
TIMING INFORMATION
Figure 29 illustrates the ADCMP572/ADCMP573 compare and latch timing relationships. Table 4 provides definitions of the terms
shown in the figure.
LATCH ENABLE
50%
LATCH ENABLE
tS
tPL
tH
V
IN
DIFFERENTIAL
INPUT VOLTAGE
V
± V
OS
N
V
OD
tPDL
tPLOH
Q OUTPUT
50%
50%
tF
tPDH
Q OUTPUT
tPLOL
tR
Figure 29. System Timing Diagram
Table 4. Timing Descriptions
Symbol Timing
Description
tPDH
tPDL
tPLOH
tPLOL
tH
Input to output high delay
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50ꢀ point of an output low-to-high transition.
Propagation delay measured from the time the input signal crosses the reference ( the
input offset voltage) to the 50ꢀ point of an output high-to-low transition.
Propagation delay measured from the 50ꢀ point of the latch enable signal low-to-high
transition to the 50ꢀ point of an output low-to-high transition.
Propagation delay measured from the 50ꢀ point of the latch enable signal low-to-high
transition to the 50ꢀ point of an output high-to-low transition.
Input to output low delay
Latch enable to output high delay
Latch enable to output low delay
Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
tPL
Minimum latch enable pulse width
Minimum setup time
Minimum time that the latch enable signal must be high to acquire an input signal
change.
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
tS
tR
Output rise time
Amount of time required to transition from a low to a high output as measured at the
20ꢀ and 80ꢀ points.
tF
Output fall time
Amount of time required to transition from a high to a low output as measured at the
20ꢀ and 80ꢀ points.
VOD
Voltage overdrive
Difference between the input voltages VA and VB.
Rev. A | Page 13 of 16
ADCMP572/ADCMP573
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.45
1.30 SQ
1.15
13
16
1
0.45
(BOTTOM VIEW)
12
PIN 1
INDICATOR
2.75
BSC SQ
TOP
VIEW
EXPOSED
PAD
4
9
0.50
BSC
8
5
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
Evaluation Board
Package Option
CP-16-2
CP-16-2
CP-16-2
CP-16-2
CP-16-2
CP-16-2
CP-16-2
CP-16-2
CP-16-2
CP-16-2
CP-16-2
CP-16-2
Branding
G03
G0Y
G03
G03
ADCMP572BCP-WP
ADCMP572BCPZ-WP1
ADCMP572BCP-R2
ADCMP572BCP-RL7
ADCMP572BCPZ-R21
ADCMP572BCPZ-RL71
ADCMP573BCP-WP
ADCMP573BCPZ-WP1
ADCMP573BCP-R2
ADCMP573BCP-RL7
ADCMP573BCPZ-R21
ADCMP573BCPZ-RL71
EVAL-ADCMP572BCPZ1
EVAL-ADCMP573BCPZ1
G0Y
G0Y
G05
G0Z
G05
G05
G0Z
G0Z
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
ADCMP572/ADCMP573
NOTES
Rev. A | Page 15 of 16
ADCMP572/ADCMP573
NOTES
© 2005–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04409–0–4/09(A)
Rev. A | Page 16 of 16
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