OPZ177FPZ [ADI]
IC OP-AMP, 40 uV OFFSET-MAX, 0.6 MHz BAND WIDTH, PDIP8, PLASTIC, MS-001BA, DIP-8, Operational Amplifier;
| 型号： | OPZ177FPZ |
| 厂家： | 
ADI |
| 描述： | IC OP-AMP, 40 uV OFFSET-MAX, 0.6 MHz BAND WIDTH, PDIP8, PLASTIC, MS-001BA, DIP-8, Operational Amplifier 放大器 光电二极管 |
| 文件： | 总16页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultraprecision
Operational Amplifier
OP177
FEATURES
PIN CONFIGURATION
Ultralow offset voltage
TA = 25°C, 25 μV maximum
Outstanding offset voltage drift 0.1 μV/°C maximum
Excellent open-loop gain and gain linearity
12 V/μV typical
1
2
3
4
8
7
6
5
V
TRIM
–IN
V
TRIM
OS
OS
OP177
V+
+IN
V–
OUT
NC
TOP VIEW
(Not to Scale)
NC = NO CONNECT
CMRR: 130 dB minimum
Figure 1. 8-Lead PDIP (P-Suffix),
8-Lead SOIC (S-Suffix)
PSRR: 115 dB minimum
Low supply current 2.0 mA maximum
Fits industry-standard precision op amp sockets
operational amplifier. The combination of outstanding
specifications of the OP177 ensures accurate performance in
high closed-loop gain applications.
GENERAL DESCRIPTION
The OP177 features one of the highest precision performance of
any op amp currently available. Offset voltage of the OP177 is
only 25 μV maximum at room temperature. The ultralow VOS of
the OP177 combines with its exceptional offset voltage drift
(TCVOS) of 0.1 μV/°C maximum to eliminate the need for
external VOS adjustment and increases system accuracy over
temperature.
This low noise, bipolar input op amp is also a cost effective
alternative to chopper-stabilized amplifiers. The OP177
provides chopper-type performance without the usual problems
of high noise, low frequency chopper spikes, large physical size,
limited common-mode input voltage range, and bulky external
storage capacitors.
The OP177 open-loop gain of 12 V/μV is maintained over the
full 10 V output range. CMRR of 130 dB minimum, PSRR of
120 dB minimum, and maximum supply current of 2 mA are
just a few examples of the excellent performance of this
The OP177 is offered in the −40°C to +85°C extended industrial
temperature ranges. This product is available in 8-lead PDIP, as
well as the space saving 8-lead SOIC.
FUNCTIONAL BLOCK DIAGRAM
V+
(OPTIONAL NULL)
R
*
R
*
2A
2B
C
1
R
7
R
R
1A
1B
Q
2B
19
R
Q
Q
10
9
9
Q
Q
12
11
Q
Q
Q
8
7
Q
Q
Q
6
Q
Q
OUTPUT
3
5
4
R
R
C
Q
3
C
3
2
17
NONINVERTING
INPUT
Q
R
27
26
25
10
Q
16
15
R
Q
1
R
5
Q
Q
Q
Q
20
21
23
24
Q
Q
22
4
INVERTING
INPUT
Q
2
Q
18
R
Q
14
Q
13
6
8
V–
*R AND R ARE ELECTRONICALLY ADJUSTED ON CHIP AT FACTORY.
2A 2B
Figure 2. Simplified Schematic
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1995–2009 Analog Devices, Inc. All rights reserved.
OP177
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information.................................................................9
Gain Linearity................................................................................9
Pin Configuration............................................................................. 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Test Circuits................................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Thermocouple Amplifier with Cold-Junction
Compensation........................................................................................9
Precision High Gain Differential Amplifier ........................... 10
Isolating Large Capacitive Loads.............................................. 10
Bilateral Current Source............................................................ 10
Precision Absolute Value Amplifier......................................... 10
Precision Positive Peak Detector.............................................. 12
Precision Threshold Detector/Amplifier ................................ 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 14
REVISION HISTORY
3/09—Rev. E to Rev. F
Added Figure 23, Renumbered Sequentially ................................ 8
Updated Outline Dimensions....................................................... 13
Changes to Figure 12 through Figure 17........................................7
Changes to Figure 18 through Figure 22........................................8
Change to Figure 27 ....................................................................... 10
Changes to Figure 30 and Figure 31............................................. 11
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide.......................................................... 13
5/06—Rev. D to Rev. E
Changes to Figure 1.......................................................................... 1
Change to Specifications Table 1 .................................................... 3
Changes to Specifications Table 2................................................... 4
Changes to Table 3............................................................................ 5
Changes to Figure 23 and Figure 24............................................... 9
Changes to Figure 32...................................................................... 12
Updated the Ordering Guide ........................................................ 14
1/05—Rev. B to Rev. C
Edits to Features.................................................................................1
Edits to General Description ...........................................................1
Edits to Pin Connections..................................................................1
Edits to Electrical Characteristics .............................................. 2, 3
Global deletion of references to OP177E ............................ 3, 4, 10
Edits to Absolute Maximum Ratings..............................................5
Edits to Package Type .......................................................................5
Edits to Ordering Guide ...................................................................5
Edit to Outline Dimensions .......................................................... 11
4/06—Rev. C to Rev. D
Change to Pin Configuration Caption........................................... 1
Changes to Features.......................................................................... 1
Change to Table 2 ............................................................................. 4
Change to Figure 2 ........................................................................... 4
Changes to Figure 10 and Figure 11............................................... 6
11/95—Rev. 0: Initial Version
Rev. F | Page 2 of 16
OP177
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VS = 15 V, TA = 25°C, unless otherwise noted.
Table 1.
OP177F
Typ
OP177G
Typ Max Unit
Parameter
Symbol
Conditions
Min
Max Min
INPUT OFFSET VOLTAGE
LONG-TERM INPUT OFFSET1
Voltage Stability
VOS
10
25
20
60
μV
ΔVOS/time
0.3
0.3
+1.2
118
3
0.4
0.3
+1.2
118
3
μV/mo
nA
INPUT OFFSET CURRENT
INPUT BIAS CURRENT
IOS
IB
1.5
2.8
−0.2
26
+2
150
8
−0.2
18.5
+2.8 nA
INPUT NOISE VOLTAGE
INPUT NOISE CURRENT
INPUT RESISTANCE
en
in
fO = 1 Hz to 100 Hz2
fO = 1 Hz to 100 Hz2
150
8
nV rms
pA rms
Differential Mode3
RIN
45
45
MΩ
GΩ
V
INPUT RESISTANCE COMMON MODE
INPUT VOLTAGE RANGE4
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE SIGNAL VOLTAGE GAIN
OUTPUT VOLTAGE SWING
RINCM
IVR
200
14
200
14
13
130
115
5000
13.5
12.5
12.0
0.1
13
115
110
2000
13.5
12.5
12.0
0.1
CMRR
PSRR
AVO
VCM = 13 V
VS = 3 V to 18 V
RL ≥ 2 kΩ, VO = 10 V5
RL ≥ 10 kΩ
RL ≥ 2 kΩ
RL ≥ 1 kΩ
140
125
12,000
14.0
13.0
12.5
0.3
140
120
6000
14.0
13.0
12.5
0.3
0.6
60
dB
dB
V/mV
V
V
VO
V
SLEW RATE2
SR
BW
RO
RL ≥ 2 kΩ
V/μs
MHz
Ω
CLOSED-LOOP BANDWIDTH2
OPEN-LOOP OUTPUT RESISTANCE
POWER CONSUMPTION
AVCL = 1
0.4
0.6
0.4
60
PD
VS = 15 V, no load
VS = 3 V, no load
VS = 15 V, no load
RP = 20 kΩ
50
3.5
60
4.5
2
50
60
4.5
2
mW
mW
mA
mV
3.5
1.6
3
SUPPLY CURRENT
ISY
1.6
OFFSET ADJUSTMENT RANGE
3
1 Long-term input offset voltage stability refers to the averaged trend line of VOS vs. time over extended periods after the first 30 days of operation. Excluding the initial
hour of operation, changes in VOS during the first 30 operating days are typically less than 2.0 μV.
2 Sample tested.
3 Guaranteed by design.
4 Guaranteed by CMRR test condition.
5 To ensure high open-loop gain throughout the 10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and –10 V ≤ VO ≤ +10 V.
Rev. F | Page 3 of 16
OP177
@ VS = 15 V, −40°C ≤ TA ≤ +85°C, unless otherwise noted.
Table 2.
OP177F
Typ
OP177G
Typ
Parameter
Symbol Conditions
Min
Max Min
Max Unit
INPUT
Input Offset Voltage
VOS
TCVOS
IOS
TCIOS
IB
TCIB
IVR
CMRR
PSRR
AVO
VO
15
40
20
0.7
0.5
1.5
+2.4
15
13.5
140
115
100
1.2
4.5
85
6
μV
μV/°C
nA
pA/°C
nA
pA/°C
V
Average Input Offset Voltage Drift1
0.1
0.5
1.5
0.3
2.2
40
+4
40
Input Offset Current
Average Input Offset Current Drift2
Input Bias Current
Average Input Bias Current Drift2
Input Voltage Range3
−0.2 +2.4
8
60
13
120
110
13.5
13
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
LARGE-SIGNAL VOLTAGE GAIN4
OUTPUT VOLTAGE SWING
POWER CONSUMPTION
SUPPLY CURRENT
VCM = 13 V
140
120
110
106
dB
VS = 3 V to 18 V
dB
RL ≥ 2 kΩ, VO = 10 V 2000 6000
1000 4000
V/mV
V
RL ≥ 2 kΩ
12
13
60
20
12
13
60
PD
VS = 15 V, no load
VS = 15 V, no load
75
75
mW
mA
ISY
2.5
2
2.5
1 TCVOS is sample tested.
2 Guaranteed by endpoint limits.
3 Guaranteed by CMRR test condition.
4 To ensure high open-loop gain throughout the 10 V output range, AVO is tested at −10 V ≤ VO ≤ 0 V, 0 V ≤ VO ≤ +10 V, and −10 V ≤ VO ≤ +10 V.
TEST CIRCUITS
200kΩ
50Ω
–
V
OP177
+
O
V
O
V
=
OS
4000
Figure 3. Typical Offset Voltage Test Circuit
20kΩ
V+
–
–
INPUT
OUTPUT
OP177
+
+
V
TRIM RANGE IS
OS
TYPICALLY ±3.0mV
V–
Figure 4. Optional Offset Nulling Circuit
20kΩ
+20V
–
OP177
+
PINOUTS SHOWN FOR
P AND Z PACKAGES
–20V
Figure 5. Burn-In Circuit
Rev. F | Page 4 of 16
OP177
ABSOLUTE MAXIMUM RATINGS
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Ratings
Supply Voltage
22 V
500 mW
30 V
22 V
Indefinite
−65°C to +125°C
−40°C to +85°C
300°C
Internal Power Dissipation1
Differential Input Voltage
Input Voltage
Output Short-Circuit Duration
StorageTemperature Range
Operating Temperature Range
Lead Temperature (Soldering, 60 sec)
DICE Junction Temperature (TJ)
THERMAL RESISTANCE
θJA is specified for worst-case mounting conditions, that is, θJA
is specified for device in socket for PDIP; θJA is specified for
device soldered to printed circuit board for SOIC package.
−65°C to +150°C
1 For supply voltages less than 22 V, the absolute maximum input voltage is
equal to the supply voltage.
Table 4. Thermal Resistance
Package Type
θJA
θJC
43
43
Unit
°C/W
°C/W
8-Lead PDIP (P-Suffix)
8-Lead SOIC (S-Suffix)
103
158
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 5 of 16
OP177
TYPICAL PERFORMANCE CHARACTERISTICS
2
20
25
30
35
T
V
R
= 25°C
= ±15V
= 10kΩ
A
V = ±15V
S
S
L
DEVICE IMMERSED IN
70° OIL BATH (20 UNITS)
1
0
40
45
50
–1
–2
–10
0
10
20
30
40
50
60
70
–5
0
5
10
TIME (Seconds)
OUTPUT VOLTAGE (V)
Figure 9. Offset Voltage Change Due to Thermal Shock
Figure 6. Gain Linearity (Input Voltage vs. Output Voltage)
25
20
15
10
5
100
10
1
T
= 25°C
V = ±15V
S
A
0
–55
–35
–15
5
25
45
65
85
105
125
0
10
20
30
40
TEMPERATURE (°C)
TOTAL SUPPLY VOLTAGE, V+ TO V– (V)
Figure 10. Open-Loop Gain vs. Temperature
Figure 7. Power Consumption vs. Power Supply
16
12
8
5
4
T
R
= 25°C
= 2kΩ
A
L
3
2
1
LOT A
LOT B
LOT C
LOT D
0
–1
–2
–3
–4
4
0
–5
0
±5
±10
±15
±20
0
20
40
60
80
100
120
140
160
180
POWER SUPPLY VOLTAGE (V)
TIME (Seconds)
Figure 11. Open-Loop Gain vs. Power Supply Voltage
Figure 8. Warm-Up VOS Drift (Normalized) Z Package
Rev. F | Page 6 of 16
OP177
4
3
2
1
0
160
V
= ±15V
S
T
V
= 25°C
= ±15V
A
140
120
100
80
S
60
40
20
0
0.01
0.1
1
10
100
1k
10k
100k
1M
–50
0
50
100
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 15. Open-Loop Frequency Response
Figure 12. Input Bias Current vs. Temperature
2.0
1.5
1.0
0.5
0
150
140
130
V
= ±15V
T = 25°C
A
S
120
110
100
90
80
1
10
100
1k
10k
100k
–50
0
50
100
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 16. CMRR vs. Frequency
Figure 13. Input Offset Current vs. Temperature
130
120
110
100
80
T
V
= 25°C
= ±15V
T
= 25°C
A
A
S
60
100
90
40
20
0
80
70
60
0.1
–20
1
10
100
1k
10k
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 14. Closed-Loop Response for Various Gain Configurations
Figure 17. PSRR vs. Frequency
Rev. F | Page 7 of 16
OP177
1000
20
15
10
5
T
= 25°C
A
R
= R = 200kΩ
S2
S1
V
V
= +15V
= ±10mV
S
THERMAL NOISE OF SOURCE
RESISTORS INCLUDED
IN
POSITIVE SWING
NEGATIVE SWING
100
10
EXCLUDED
R
= 0
S
T
V
= 25°C
= ±15V
A
S
0
100
1
1
10
100
1k
1k
LOAD RESISTANCE TO GROUND (Ω)
10k
FREQUENCY (Hz)
Figure 18. Total Input Noise Voltage vs. Frequency
Figure 21. Maximum Output Voltage vs. Load Resistance
40
35
30
10
T
V
= 25°C
= ±15V
T
V
= 25°C
= ±15V
A
A
S
S
+I
SC
1
25
20
15
–I
SC
0.1
100
0
1
2
3
4
1k
10k
100k
TIME FROM OUTPUT BEING SHORTED (Minutes)
BANDWIDTH (Hz)
Figure 22. Output Short-Circuit Current vs. Time
Figure 19. Input Wideband Noise vs. Bandwidth
(0.1 Hz to Frequency Indicated)
1.50
1.25
1.00
0.75
0.50
0.25
0
32
28
24
20
16
12
8
T
V
= 25°C
= ±15V
A
T
V
= 25°C
= ±15V
A
S
S
I
I
I
I
I
I
1– (nA)
2– (nA)
3– (nA)
1+ (nA)
2+ (nA)
3+ (nA)
B
B
B
B
B
B
4
0
1k
–16
–14
–10
–6
–2
2
6
10
14
10k
100k
FREQUENCY (Hz)
1M
V
(V)
CM
Figure 23. Input Bias (IB) vs. Common-Mode Voltage (VCM
)
Figure 20. Maximum Output Swing vs. Frequency
Rev. F | Page 8 of 16
OP177
APPLICATIONS INFORMATION
THERMOCOUPLE AMPLIFIER WITH COLD-
JUNCTION COMPENSATION
GAIN LINEARITY
The actual open-loop gain of most monolithic op amps varies at
different output voltages. This nonlinearity causes errors in high
closed-loop gain circuits.
An example of a precision circuit is a thermocouple amplifier
that must accurately amplify very low level signals without
introducing linearity and offset errors to the circuit. In this
circuit, an S-type thermocouple with a Seebeck coefficient of
10.3 μV/°C produces 10.3 mV of output voltage at a temperature
of 1000°C. The amplifier gain is set at 973.16, thus, it produces
an output voltage of 10.024 V. Extended temperature ranges
beyond 1500°C are accomplished by reducing the amplifier
gain. The circuit uses a low cost diode to sense the temperature
at the terminating junctions and, in turn, compensates for any
ambient temperature change. The OP177, with its high open-
loop gain plus low offset voltage and drift, combines to yield a
precise temperature sensing circuit. Circuit values for other
thermocouple types are listed in Table 5.
It is important to know that the manufacturer’s AVO specifica-
tion is only a part of the solution because all automated testers
use endpoint testing and, therefore, show only the average gain.
For example, Figure 24 shows a typical precision op amp with a
respectable open-loop gain of 650 V/mV. However, the gain is
not constant through the output voltage range, causing non-
linear errors. An ideal op amp shows a horizontal scope trace.
Figure 25 shows the OP177 output gain linearity trace with its
truly impressive average AVO of 12,000 V/mV. The output trace
is virtually horizontal at all points, assuring extremely high gain
accuracy. Analog Devices also performs additional testing to
ensure consistent high open-loop gain at various output
voltages. Figure 26 is a simple open-loop gain test circuit.
Table 5.
Thermocouple Seebeck
Type
Coefficient R1
R2
R7
R9
K
J
S
39.2 μV/°C
50.2 μV/°C
10.3 μV/°C
110 Ω 5.76 kΩ 102 kΩ 269 kΩ
100 Ω 4.02 kΩ 80.6 kΩ 200 kΩ
100 Ω 20.5 kΩ 392 kΩ 1.07 MΩ
V
X
–10V
0V
+10V
10.000V
2
6
REF01
+15V
4
R
R
2.2µF
+
9
7
R
47kΩ
1%
3
392kΩ
1%
1.07MΩ
0.05%
A
R
≥ 650V/mV
= 2kΩ
VO
L
+15V
Figure 24. Typical Precision Op Amp
10µF
+
0.1µF
R
2
20.5kΩ
V
Y
R
1.0kΩ
0.05%
10µF
ISOTHERMAL
COLD-
JUNCTIONS
8
1%
–
+
–
COPPER
COPPER
TYPES
R
5
V
OP177
+
OUT
100Ω
(ZERO
ADJUST-
MENT)
10µF
V
X
ISOTHERMAL
BLOCK
0V
–10V
+10V
R
1
10µF
0.1µF
100Ω
1%
R
4
COLD-JUNCTION
COMPENSATION
50Ω
1%
A
R
≥ 12000V/mV
VO
= 2kΩ
–15V
ANALOG
GROUND
L
ANALOG
GROUND
Figure 25. Output Gain Linearity Trace
Figure 27. Thermocouple Amplifier with Cold Junction Compensation
V
Y
10kΩ
10kΩ
1MΩ
V
= ±10V
IN
V
X
–
OP177
+
10Ω
R
L
Figure 26. Open-Loop Gain Linearity Test Circuit
Rev. F | Page 9 of 16
OP177
PRECISION HIGH GAIN DIFFERENTIAL AMPLIFIER
ISOLATING LARGE CAPACITIVE LOADS
The high gain, gain linearity, CMRR, and low TCVOS of the
OP177 make it possible to obtain performance not previously
available in single stage, very high gain amplifier applications.
See Figure 28.
The circuit shown in Figure 29 reduces maximum slew rate but
allows driving capacitive loads of any size without instability.
Because the 100 Ω resistor is inside the feedback loop, its effect
on output impedance is reduced to insignificance by the high
open loop gain of the OP177.
R1
R2
R3
R4
For best CMR,
must equal
R
F
10pF
In this example, with a 10 mV differential signal, the maximum
errors are listed in Table 6.
+15V
0.1µF
6
R
2
R
S
2
3
7
1MΩ
–
INPUT
100Ω
+15V
OUTPUT
LOAD
OP177
0.1µF
+
C
4
0.1µF
R
1kΩ
1
7
2
3
–
–15V
6
R
3
OP177
+
4
1kΩ
Figure 29. Isolating Capacitive Loads
R
0.1µF
4
BILATERAL CURRENT SOURCE
1MΩ
The current sources shown in Figure 30 supply both positive
and negative currents into a grounded load.
–15V
Figure 28. Precision High Gain Differential Amplifier
Note that
Table 6. High Gain Differential Amp Performance
R4
R2
⎛
⎝
⎞
⎟
⎠
Type
Amount
R5
+ 1
⎜
Common-Mode Voltage
Gain Linearity, Worst Case
TCVOS
TCIOS
0.1%/V
0.02%
0.0003%/°C
0.008%/°C
ZO
=
R5 + R4
R3
−
R2
R1
and that for ZO to be infinite
R5 + R4
R3
R1
must =
R2
PRECISION ABSOLUTE VALUE AMPLIFIER
The high gain and low TCVOS assure accurate operation with
inputs from microvolts to volts. In this circuit, the signal always
appears as a common-mode signal to the op amps (for details,
see Figure 31).
Rev. F | Page 10 of 16
OP177
BASIC CURRENT SOURCE
R
100mA CURRENT SOURCE
R
3
1kΩ
3
+15V
R
1
R
1
100kΩ
2
3
2
2N2222
–
–
V
V
IN
IN
50Ω
6
6
R
2
OP177
+
OP177
+
R
100kΩ
2
3
2N2907
R
5
R
5
10Ω
R
4
R
4
990Ω
–15V
I
≤ 15mA
I
≤ 100mA
OUT
OUT
R
3
I
= V
IN
OUT
R
× R
5
1
GIVEN R = R + R , R = R
2
3
4
5
1
Figure 30. Bilateral Current Source
1kΩ
1kΩ
+15V
+15V
0.1µF
0.1µF
C
D
1
1
30pF
1N4148
7
2
3
–
7
6
2
V
–
OP177
OUT
0 < V
6
< 10V
OUT
+
OP177
+
4
3
2N4393
4
V
0.1µF
IN
R
3
2kΩ
0.1µF
–15V
–15V
Figure 31. Precision Absolute Value Amplifier
1kΩ
+15V
+15V
0.1µF
0.1µF
1N4148
NC
2N930
7
7
2
2
3
–
–
6
6
OP177
V
AD820
OUT
1kΩ
3
1kΩ
V
IN
+
+
4
4
0.1µF
C
0.1µF
H
–15V
–15V
RESET
1kΩ
Figure 32. Precision Positive Peak Detector
Rev. F | Page 11 of 16
OP177
C
C
PRECISION POSITIVE PEAK DETECTOR
R
F
In Figure 32, CH must be polystyrene, Teflon®, or polyethylene
to minimize dielectric absorption and leakage. The droop rate is
determined by the size of CH and the bias current of the AD820.
100kΩ
+15V
7
0.1µF
6
R
1kΩ
S
PRECISION THRESHOLD DETECTOR/AMPLIFIER
D
2
3
1
V
–
TH
1N4148
R
2kΩ
1
In Figure 33, when VIN < VTH, amplifier output swings negative,
V
OUT
OP177
V
reverse biasing diode D1. VOUT = VTH if RL = ∞. When VIN
≥
+
IN
4
0.1µF
VTH, the loop closes.
–15V
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
R
F
V
= V
+
(
V
− V
TH
)
1 +
OUT
TH
IN
Figure 33. Precision Threshold Detector/Amplifier
R
S
CC is selected to smooth the response of the loop.
Rev. F | Page 12 of 16
OP177
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
1
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
PIN 1
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210
(5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001-BA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 34. 8-Lead Plastic Dual In-Line Package (PDIP)
P-Suffix
(N-8)
Dimensions show in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 35. 8-Lead Standard Small Outline Package (SOIC_N)
S-Suffix
(R-8)
Dimensions shown in millimeters and( inches)
Rev. F | Page 13 of 16
OP177
ORDERING GUIDE
Model
OP177FP
OP177FPZ1
OP177GP
OP177GPZ1
OP177FS
OP177FS-REEL
OP177FS-REEL7
OP177FSZ1
OP177FSZ-REEL1
OP177FSZ-REEL71
OP177GS
OP177GS-REEL
OP177GS-REEL7
OP177GSZ1
OP177GSZ-REEL1
OP177GSZ-REEL71
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead PDIP
8-Lead PDIP
8-Lead PDIP
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
Package Option
P-Suffix (N-8)
P-Suffix (N-8)
P-Suffix (N-8)
P-Suffix (N-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
S-Suffix (R-8)
1 Z = RoHS Compliant Part.
Rev. F | Page 14 of 16
OP177
NOTES
Rev. F | Page 15 of 16
OP177
NOTES
©1995–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00289-0-3/09(F)
Rev. F | Page 16 of 16
相关型号：
OPZ177GPZ
IC OP-AMP, 100 uV OFFSET-MAX, 0.6 MHz BAND WIDTH, PDIP8, PLASTIC, MS-001BA, DIP-8, Operational Amplifier
ADI
OPZ200GPZ
IC DUAL OP-AMP, 300 uV OFFSET-MAX, 0.5 MHz BAND WIDTH, PDIP8, PLASTIC, DIP-8, Operational Amplifier
ADI
OPZ213FPZ
IC DUAL OP-AMP, 325 uV OFFSET-MAX, 3.4 MHz BAND WIDTH, PDIP8, PLASTIC, MS-001 DIP-8, Operational Amplifier
ADI
OPZ275GPZ
IC DUAL OP-AMP, 1250 uV OFFSET-MAX, 9 MHz BAND WIDTH, PDIP8, PLASTIC, DIP-8, Operational Amplifier
ADI
OPZ290GPZ
IC DUAL OP-AMP, 750 uV OFFSET-MAX, 0.02 MHz BAND WIDTH, PDIP8, MO-095AA, PLASTIC, DIP-8, Operational Amplifier
ADI
OPZ467GPZ
IC QUAD OP-AMP, 1000 uV OFFSET-MAX, 22 MHz BAND WIDTH, PDIP14, PLASTIC, MS-001, DIP-14, Operational Amplifier
ADI
OPZ90GPZ
IC OP-AMP, 675 uV OFFSET-MAX, 0.02 MHz BAND WIDTH, PDIP8, PLASTIC, DIP-8, Operational Amplifier
ADI
©2020 ICPDF网 联系我们和版权申明