SSM2311CBZ-REEL [ADI]
Filterless High Efficiency Mono 3 W Class-D Audio Amplifier; 滤波的高效单声道3瓦D类音频放大器
| 型号： | SSM2311CBZ-REEL |
| 厂家： | 
ADI |
| 描述： | Filterless High Efficiency Mono 3 W Class-D Audio Amplifier |
| 文件： | 总20页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Filterless High Efficiency
Mono 3 W Class-D Audio Amplifier
SSM2311
The SSM2311 features a high efficiency, low noise modulation
scheme that does not require any external LC output filters. The
modulation continues to provide high efficiency even at low output
power. It operates with 90% efficiency at 1.4 W into 8 Ω or 85%
efficiency at 3 W into 3 Ω from a 5.0 V supply and has an SNR that
is better than 98 dB. Spread-spectrum pulse density modulation
is used to provide lower EMI-radiated emissions compared with
other Class-D architectures.
FEATURES
Filterless Class-D amplifier with Σ-Δ modulation
No sync necessary when using multiple Analog Devices, Inc.,
Class-D amplifiers
3 W into 3 Ω load and 1.4 W into 8 Ω load at 5.0 V supply with
less than 10% total harmonic distortion (THD)
90% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
Better than 98 dB signal-to-noise ratio (SNR)
Single-supply operation from 2.5 V to 5.5 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 9-ball, 1.5 mm × 1.5 mm WLCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Default fixed 18 dB or user-adjustable gain setting
The SSM2311 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying a
logic low to the
pin.
SD
The device also includes pop-and-click suppression circuitry. This
minimizes voltage glitches at the output during turn-on and turn-
off, thus reducing audible noise on activation and deactivation.
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
The fully differential input of the SSM2311 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately VDD/2.
The default gain of SSM2311 is 18 dB, but users can reduce the gain
by using a pair of external resistors (see the Gain section).
GENERAL DESCRIPTION
The SSM2311 is a fully integrated, high efficiency, Class-D audio
amplifier. It is designed to maximize performance for mobile
phone applications. The application circuit requires a minimum
of external components and operates from a single 2.5 V to 5.5 V
supply. It is capable of delivering 3 W of continuous output power
with less than 1% THD + N driving a 3 Ω load from a 5.0 V supply.
The SSM2311 is specified over the industrial temperature range
(−40°C to +85°C). It has built-in thermal shutdown and output
short-circuit protection. It is available in a 9-ball, 1.5 mm × 1.5 mm
wafer level chip scale package (WLCSP).
FUNCTIONAL BLOCK DIAGRAM
VBATT
2.5V TO 5.0V
10µF
0.1µF
300kΩ
VDD
SSM2311
1
1
22nF
22nF
R
R
37.5kΩ
EXT
IN+
OUT+
OUT–
AUDIO IN+
AUDIO IN–
FET
DRIVER
MODULATOR
IN–
37.5kΩ
EXT
300kΩ
SD
POP-AND-CLICK
SUPPRESSION
BIAS
OSCILLATOR
SHUTDOWN
GND
300kΩ
(37.5kΩ + R
GAIN =
)
EXT
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V /2.
DD
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
SSM2311
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Application Circuits ......................................................... 13
Application Notes........................................................................... 15
Overview ..................................................................................... 15
Gain.............................................................................................. 15
Pop-and-Click Suppression ...................................................... 15
Layout .......................................................................................... 15
Input Capacitor Selection.......................................................... 16
Proper Power Supply Decoupling ............................................ 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
REVISION HISTORY
1/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
SSM2311
SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 Ω, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min Typ
Max
Unit
DEVICE CHARACTERISTICS
Output Power
PO
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0V
RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0V
RL = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6V
RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
RL = 4 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6V
RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0V
RL = 4 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6V
RL = 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V
RL = 3 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6V
RL = 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0V
RL = 3 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6V
POUT = 1.4 W, 8 Ω, VDD = 5.0 V
1.2
0.615
W
W
W
W
W
W
W
W
W
W
W
W
%
1.53
0.77
2
1.4
2.3
1.6
3
1.8
3.3
2.5
89
Efficiency
η
Total Harmonic Distortion + Noise
THD + N PO = 3 W into 3 Ω, f = 1 kHz, VDD = 5.0V
0.5
0.2
%
%
PO = 1 W into 8 Ω, f = 1 kHz, VDD = 5.0 V
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
Average Switching Frequency
Differential Output Offset Voltage
POWER SUPPLY
VCM
1.0
VDD − 1.0
V
CMRRGSM VCM = 2.5 V 100 mV at 217 Hz input referred
fSW
VOOS
60
800
2.0
dB
kHz
mV
G = 18 dB
12.0
5.0
Supply Voltage Range
Power Supply Rejection Ratio
VDD
PSRR
PSRRGSM
Guaranteed from PSRR test
VDD = 2.5 V to 5.0 V, dc input floating/ground
VRIPPLE = 100 mV at 217 Hz, inputs ac GND,
CIN = 0.1 μF
2.5
70
V
dB
dB
85
60
Supply Current
ISY
VIN = 0 V, no load, VDD = 5.0 V
VIN = 0 V, no load, VDD = 3.6 V
VIN = 0 V, no load, VDD = 2.5 V
SD = GND
5.5
4.5
4.0
20
mA
mA
mA
nA
Shutdown Current
ISD
GAIN CONTROL
Closed-Loop Gain
Differential Input Impedance
Av
ZIN
18
37.5
dB
kΩ
SD = VDD
SHUTDOWN CONTROL
Input Voltage High
Input Voltage Low
Turn-On Time
VIH
VIL
tWU
tSD
ISY ≥ 1 mA
ISY ≤ 300 nA
SD rising edge from GND to VDD
SD falling edge from VDD to GND
SD = GND
1.2
0.5
30
V
V
ms
μs
kΩ
Turn-Off Time
5
Output Impedance
ZOUT
>100
NOISE PERFORMANCE
Output Voltage Noise
en
VDD = 3.6 V, f = 20 Hz to 20 kHz, inputs are
ac grounded, AV = 18 dB, A weighting
POUT = 1.4 W, RL = 8 Ω
35
98
μV
dB
Signal-to-Noise Ratio
SNR
Rev. 0 | Page 3 of 20
SSM2311
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 2.
Parameter
Rating
Supply Voltage
Input Voltage
6 V
VDD
VDD
Table 3. Thermal Resistance
Package Type
PCB
1S0P1 162 38.5 °C/W
2S0P1 76
21 °C/W
θJA
θJB
Unit
Common-Mode Input Voltage
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature (Soldering, 60 sec)
9-Ball, 1.5 mm × 1.5 mm WLCSP
−65°C to +150°C
−40°C to +85°C
−65°C to +165°C
300°C
1 Referencing the JEDEC thermal standard.
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 4 of 20
SSM2311
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
BALL A1
CORNER
1
2
3
A
B
C
SSM2311
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
Figure 2. SSM2311 WLCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
2C
SD
Shutdown Input. Active low digital input.
Noninverting Input.
Inverting Input.
1A
1C
IN+
IN−
3C
1B
OUT−
VDD
Inverting Output.
Power Supply.
2A, 3B
3A
2B
GND
OUT+
PVDD
Ground.
Noninverting Output.
Power Supply.
Rev. 0 | Page 5 of 20
SSM2311
TYPICAL PERFORMANCE CHARACTERISTICS
100
100
10
R
= 8Ω, 33µH
GAIN = 6dB
L
GAIN = 18dB
R
= 4Ω, 33µH
L
V
= 2.5V
DD
10
1
VDD = 2.5V
1
0.1
0.1
VDD = 3.6V
V
= 3.6V
DD
V
= 5V
DD
0.01
0.001
0.01
0.001
VDD = 5V
0.0001
0.001
0.01
0.1
1
10
0.0001
0.001
0.01
0.1
1
10
10
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 3. THD + N vs. Output Power into 8 Ω, AV = 18 dB
Figure 6. THD + N vs. Output Power into 4 Ω, AV = 6 dB
100
10
100
10
R
= 8Ω, 33µH
GAIN = 18dB
L
GAIN = 6dB
R
= 3Ω, 33µH
L
V
= 2.5V
V
= 2.5V
DD
DD
1
1
0.1
V
= 3.6V
0.1
DD
V
= 3.6V
DD
V
1
= 5V
DD
0.01
0.01
V
= 5V
DD
0.001
0.0001
0.001
0.0001
0.001
0.01
0.1
0.001
0.01
0.1
1
10
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 4. THD + N vs. Output Power into 8 Ω, AV = 6 dB
Figure 7. THD + N vs. Output Power into 3 Ω, AV = 18 dB
100
10
100
10
RL = 3ꢀ, 33µH
GAIN = 18dB
R
= 4Ω, 33µH
GAIN = 6dB
L
V
= 2.5V
DD
V
= 2.5V
DD
1
1
V
= 3.6V
DD
V
= 3.6V
DD
0.1
0.1
0.01
0.001
0.001
0.001
V
= 5V
V
1
= 5V
DD
DD
0.0001
0.001
0.01
0.1
1
10
0.0001
0.001
0.01
0.1
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 5. THD + N vs. Output Power into 4 Ω, AV = 18 dB
Figure 8. THD + N vs. Output Power into 3 Ω, AV = 6 dB
Rev. 0 | Page 6 of 20
SSM2311
100
10
100
10
V
= 5V
V
= 3.6V
DD
DD
GAIN = 18dB
= 8ꢀ, 33µH
GAIN = 18dB
= 8ꢀ, 33µH
R
R
L
L
1
1
1W
0.5W
0.1
0.1
0.5W
0.01
0.001
0.01
0.001
0.25W
0.125W
0.25W
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
FREQUENCY (Hz)
10k
100k
Figure 12. THD + N vs. Frequency, VDD = 3.6 V, RL = 8 Ω, AV = 18 dB
Figure 9. THD + N vs. Frequency, VDD = 5.0 V, RL = 8 Ω, AV = 18 dB
100
100
V
= 5V
V
= 3.6V
DD
DD
GAIN = 18dB
= 4ꢀ, 33µH
GAIN = 18dB
= 4ꢀ, 33µH
R
R
L
L
10
1
10
1
2W
1W
0.1
0.1
0.5W
1W
0.01
0.001
0.01
0.001
0.5W
0.25W
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 10. THD + N vs. Frequency, VDD = 5.0 V, RL = 4 Ω, AV = 18 dB
Figure 13. THD + N vs. Frequency, VDD = 3.6 V, RL = 4 Ω, AV = 18 dB
100
100
V
= 5V
V
= 3.6V
DD
DD
GAIN = 18dB
= 3ꢀ, 33µH
GAIN = 18dB
R = 3ꢀ, 33µH
L
R
L
10
1
10
1
1.5W
3W
0.1
0.1
0.75W
1.5W
0.01
0.001
0.01
0.001
0.75W
0.38W
10
100
1k
FREQUENCY (Hz)
10k
100k
10
100
1k
10k
100k
FREQUENCY (Hz)
Figure 11. THD + N vs. Frequency, VDD = 5.0 V, RL = 3 Ω, AV = 18 dB
Figure 14. THD + N vs. Frequency, VDD = 3.6 V, RL = 3 Ω, AV = 18 dB
Rev. 0 | Page 7 of 20
SSM2311
100
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.9
3.4
3.2
V
= 2.5V
DD
NO LOAD
GAIN = 18dB
= 8ꢀ, 33µH
R
L
10
1
0.25W
0.1
0.125W
0.01
0.001
0.075W
10
100
1k
FREQUENCY (Hz)
10k
100k
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.8
5.0
SUPPLY VOLTAGE (V)
Figure 15. THD + N vs. Frequency, VDD = 2.5 V, RL = 8 Ω, AV = 18 dB
Figure 18. Supply Current vs. Supply Voltage, No Load
100
12
10
8
V
= 2.5V
DD
GAIN = 18dB
R
= 4ꢀ, 33µH
L
10
1
0.5W
V
= 5V
DD
6
0.1
V
= 3.6V
DD
V
4
= 2.5V
DD
0.01
0.001
2
0.125W
0.25W
10k
0
10
100
1k
FREQUENCY (Hz)
100k
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
SHUTDOWN VOLTAGE (V)
Figure 16. THD + N vs. Frequency, VDD = 2.5 V, RL = 4 Ω, AV = 18 dB
Figure 19. Shutdown Current vs. Shutdown Voltage
100
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 2.5V
f = 1kHz
GAIN = 18dB
= 8ꢀ, 33µH
DD
GAIN = 18dB
= 3ꢀ, 33µH
R
L
R
L
10
1
0.75W
10%
1%
0.1
0.38W
0.01
0.001
0.2W
10
100
1k
FREQUENCY (Hz)
10k
100k
2.5
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
Figure 17. THD + N vs. Frequency, VDD = 2.5 V, RL = 3 Ω, AV = 18 dB
Figure 20. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, AV = 18 dB
Rev. 0 | Page 8 of 20
SSM2311
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
3.5
3
f = 1kHz
GAIN = 18dB
f = 1kHz
GAIN = 6dB
R
= 4ꢀ, 33µH
R
= 4ꢀ, 33µH
L
L
2.5
2.0
1.5
1.0
0.5
0
10%
10%
1%
1%
2.5
3.0
3.5
4.0
4.5
5.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 21. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, AV = 18 dB
Figure 24. Maximum Output Power vs. Supply Voltage, RL = 4 Ω, AV = 6 dB
4.5
4.5
f = 1kHz
f = 1kHz
GAIN = 18dB
GAIN = 6dB
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
R
= 3ꢀ, 33µH
R
= 3ꢀ, 33µH
L
L
10%
10%
1%
1%
2.5
3.0
3.5
4.0
4.5
5.0
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 22. Maximum Output Power vs. Supply Voltage, RL = 3 Ω, AV = 18 dB
Figure 25. Maximum Output Power vs. Supply Voltage, RL = 3 Ω, AV = 6 dB
2.0
100
90
f = 1kHz
GAIN = 6dB
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
R
= 8ꢀ, 33µH
L
V
= 5V
DD
80
70
60
50
40
30
20
10
0
V
= 3.6V
DD
V
= 2.5V
DD
10%
1%
0.2
0
R
= 8ꢀ, 33µH
L
2.5
3.0
3.5
4.0
4.5
5.0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
Figure 23. Maximum Output Power vs. Supply Voltage, RL = 8 Ω, AV = 6 dB
Figure 26. Efficiency vs. Output Power into 8 Ω
Rev. 0 | Page 9 of 20
SSM2311
100
0.30
0.25
0.20
0.15
0.10
0.05
0
V
= 2.5V
DD
90
80
70
60
50
40
30
20
10
0
V
= 5V
DD
V
= 3.6V
DD
V
= 5V
DD
R
= 4ꢀ, 33µH
R
= 4ꢀ, 33µH
L
L
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
OUTPUT POWER (W)
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
OUTPUT POWER (W)
Figure 27. Efficiency vs. Output Power into 4 Ω
Figure 30. Power Dissipation vs. Output Power into 4 Ω at VDD = 5.0 V
100
90
80
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
V
= 2.5V
DD
V
= 5V
DD
V
= 3.6V
DD
V
R
= 5V
= 3ꢀ, 33µH
DD
R
= 3ꢀ, 33µH
L
L
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 28. Efficiency vs. Output Power into 3 Ω
Figure 31. Power Dissipation vs. Output Power into 3 Ω at VDD = 5.0 V
0.14
0.12
0.10
0.08
0.06
0.04
0.10
0.08
0.06
0.04
0.02
V
R
= 5V
= 8ꢀ, 33µH
DD
L
V
R
= 3.6V
= 8ꢀ, 33µH
DD
L
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 29. Power Dissipation vs. Output Power into 8 Ω at VDD = 5.0 V
Figure 32. Power Dissipation vs. Output Power into 8 Ω at VDD = 3.6 V
Rev. 0 | Page 10 of 20
SSM2311
600
500
400
300
200
100
0
0.24
0.22
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
V
R
= 3.6V
= 4ꢀ, 33µH
DD
L
V
= 3.6V
DD
V
= 5V
DD
V
= 2.5V
DD
R
= 4ꢀ, 33µH
L
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 36. Supply Current vs. Output Power into 4 Ω
Figure 33. Power Dissipation vs. Output Power into 4 Ω at VDD = 3.6 V
800
700
600
500
400
300
200
100
0
0.40
V
R
= 3.6V
= 3ꢀ, 33µH
DD
L
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
= 3.6V
DD
V
= 5V
DD
V
= 2.5V
DD
R
= 3ꢀ, 33µH
L
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4
OUTPUT POWER (W)
OUTPUT POWER (W)
Figure 37. Supply Current vs. Output Power into 3 Ω
Figure 34. Power Dissipation vs. Output Power into 3 Ω at VDD = 3.6 V
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
350
300
V
= 3.6V
DD
250
200
150
100
50
V
= 5V
DD
V
= 2.5V
DD
R
= 8ꢀ, 33µH
L
0
10
100
1k
10k
100k
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
FREQUENCY (Hz)
OUTPUT POWER (W)
Figure 38. Power Supply Rejection Ratio vs. Frequency
Figure 35. Supply Current vs. Output Power into 8 Ω
Rev. 0 | Page 11 of 20
SSM2311
0
7
6
R
= 8ꢀ, 33µH
L
–10
–20
–30
–40
–50
–60
–70
–80
5
4
3
2
1
0
–1
–2
10
100
1k
10k
100k
–10
0
10
20
30
40
50
60
70
80
90
FREQUENCY (Hz)
TIME (ms)
Figure 39. Common-Mode Rejection Ratio vs. Frequency
Figure 41. Turn-On Response
0
–20
7
6
V
V
R
= 3.6V
= 1V rms
= 8ꢀ, 33µH
DD
RIPPLE
OUTPUT
L
SD INPUT
5
–40
4
–60
3
2
–80
1
–100
–120
–140
0
–1
–2
10
100
1k
10k
100k
–20
0
20
40
60
80
100 120 140 160 180
FREQUENCY (Hz)
TIME (ms)
Figure 40. Crosstalk vs. Frequency
Figure 42. Turn-Off Response
Rev. 0 | Page 12 of 20
SSM2311
TYPICAL APPLICATION CIRCUITS
VBATT
2.5V TO 5.0V
10µF
0.1µF
300kꢀ
VDD
SSM2311
1
1
22nF
22nF
37.5kꢀ
37.5kꢀ
IN+
IN–
OUT+
OUT–
AUDIO IN+
AUDIO IN–
FET
DRIVER
MODULATOR
300kꢀ
BIAS
SD
POP/CLICK
SUPPRESSION
OSCILLATOR
SHUTDOWN
GND
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V /2.
DD
Figure 43. Differential Input Configuration
VBATT
2.5V TO 5.0V
10µF
0.1µF
300kꢀ
VDD
SSM2311
1
22nF
22nF
37.5kꢀ
IN+
IN–
OUT+
OUT–
AUDIO IN+
FET
DRIVER
MODULATOR
1
37.5kꢀ
300kꢀ
BIAS
SD
POP/CLICK
SUPPRESSION
OSCILLATOR
SHUTDOWN
GND
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V /2.
DD
Figure 44. Single-Ended Input Configuration
Rev. 0 | Page 13 of 20
SSM2311
VBATT
2.5V TO 5.0V
10µF
0.1µF
300kꢀ
VDD
SSM2311
1
1
22nF
22nF
R
R
37.5kꢀ
EXT
IN+
OUT+
AUDIO IN+
AUDIO IN–
FET
DRIVER
MODULATOR
IN–
OUT–
37.5kꢀ
EXT
300kꢀ
BIAS
SD
POP/CLICK
SUPPRESSION
OSCILLATOR
SHUTDOWN
GND
300kꢀ
(37.5kꢀ + R
GAIN =
)
EXT
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V /2.
DD
Figure 45. Differential Input Configuration, User-Adjustable Gain
VBATT
10µF
2.5V TO 5.0V
0.1µF
300kꢀ
VDD
SSM2311
1
1
22nF
22nF
R
R
37.5kꢀ
EXT
EXT
IN+
OUT+
OUT–
AUDIO IN+
FET
DRIVER
MODULATOR
IN–
37.5kꢀ
300kꢀ
SD
POP/CLICK
SUPPRESSION
BIAS
OSCILLATOR
SHUTDOWN
GND
300kꢀ
(37.5kꢀ + R
GAIN =
)
EXT
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V /2.
DD
Figure 46. Single-Ended Input Configuration, User-Adjustable Gain
Rev. 0 | Page 14 of 20
SSM2311
APPLICATION NOTES
track length for lowest DCR, and use 1 oz or 2 oz of copper PCB
traces to further reduce IR drops and inductance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs to
minimize losses due to parasitic trace resistance.
OVERVIEW
The SSM2311 mono Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external components
count, conserving board space and thus reducing the system’s cost.
The SSM2311 does not require an output filter, but instead relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and the human ear to fully recover the audio
component of the square-wave output. While many Class-D ampli-
fiers use some variation of pulse-width modulation (PWM), the
SSM2311 uses Σ-Δ modulation to determine the switching
pattern of the output devices. This provides a number of important
benefits. Σ-Δ modulators do not produce a sharp peak with
many harmonics in the AM frequency band, as pulse-width
modulators often do. Σ-Δ modulation provides the benefits of
reducing the amplitude of spectral components at high frequencies;
that is, reducing EMI emission that might otherwise be radiated
by speakers and long cable traces. Due to the inherent spread-
spectrum nature of Σ-Δ modulation, the need for oscillator
synchronization is eliminated for designs incorporating
multiple SSM2311 amplifiers.
Proper grounding guidelines help to improve audio
performance, minimize crosstalk between channels, and
prevent switching noise from coupling into the audio signal. To
maintain high output swing and high peak output power, the
PCB traces that connect the output pins to the load and supply
pins should be as wide as possible to maintain the minimum
trace resistances. It is also recommended to use a large-area
ground plane for minimum impedances.
In addition, good PCB layouts isolate critical analog paths from
sources of high interference. High frequency circuits (analog
and digital) should be separated from low frequency ones.
Properly designed multilayer printed circuit boards can reduce
EMI emission and increase immunity to the RF field by a factor of
10 or more compared with double-sided boards. A multilayer
board allows a complete layer to be used for the ground plane,
whereas the ground plane side of a double-sided board is often
disrupted with signal crossover. If the system has separate analog
and digital ground and power planes, the analog ground plane
should be underneath the analog power plane, and, similarly, the
digital ground plane should be underneath the digital power
plane. There should be no overlap between analog and digital
ground planes or analog and digital power planes.
The SSM2311 also offers protection circuits for overcurrent and
temperature protection.
GAIN
The SSM2311 has a default gain of 18 dB, but can be reduced by
using a pair of external resistors with a value calculated as follows:
External Gain Settings = 300k/(37.5k + Rext)
70
60
50
40
30
20
10
0
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers can occur when
shutdown is activated or deactivated. Voltage transients as low
as 10 mV can be heard as an audio pop in the speaker. Clicks
and pops can also be classified as undesirable audible transients
generated by the amplifier system and therefore as not coming
from the system input signal. Such transients can be generated
when the amplifier system changes its operating mode. For example,
the following can be sources of audible transients: system power-up/
power-down, mute/unmute, input source change, and sample rate
change. The SSM2311 has a pop-and-click suppression architecture
that reduces these output transients, resulting in noiseless activation
and deactivation.
–10
30
100
FREQUENCY (MHz)
1000
Figure 47. EMI Emissions from SSM2311
LAYOUT
As output power continues to increase, care needs to be taken to
lay out PCB traces and wires properly between the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Ensure that track widths are at least 200 mil for every inch of
Rev. 0 | Page 15 of 20
SSM2311
PROPER POWER SUPPLY DECOUPLING
INPUT CAPACITOR SELECTION
To ensure high efficiency, low THD, and high PSRR, proper power
supply decoupling is necessary. Noise transients on the power
supply lines are short-duration voltage spikes. Although the actual
switching frequency can range from 10 kHz to 100 kHz, these
spikes can contain frequency components that extend into the
hundreds of megahertz. The power supply input needs to be
decoupled with a good quality low ESL, low ESR capacitor—usually
of around 4.7 μF. This capacitor bypasses low frequency noises
to the ground plane. For high frequency transients noises, use a
0.1 μF capacitor as close as possible to the VDD pin of the device.
Placing the decoupling capacitor as close as possible to the SSM2311
helps maintain efficiency performance.
The SSM2311 does not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input capacitors
are required if the input signal is not biased within this recom-
mended input dc common-mode voltage range, if high-pass
filtering is needed (Figure 43), or if using a single-ended source
(Figure 44). If high-pass filtering is needed at the input, the input
capacitor along with the input resistor of the SSM2311 forms a
high-pass filter whose corner frequency is determined by the
following equation:
fC = 1/(2π × RIN × CIN)
The input capacitor can significantly affect the performance of
the circuit. Not using input capacitors degrades both the output
offset of the amplifier and the PSRR performance.
Rev. 0 | Page 16 of 20
SSM2311
OUTLINE DIMENSIONS
0.65
0.59
0.53
1.575
1.515
1.455
SEATING
PLANE
3
2
1
A
B
C
0.35
0.32
0.29
BALL 1
IDENTIFIER
1.750
1.690
1.630
0.50 BSC
BALL PITCH
TOP VIEW
(BALL SIDE DOWN)
0.28
0.24
0.20
BOTTOM VIEW
(BALL SIDE UP)
Figure 48. 9-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-9-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
CB-9-1
CB-9-1
Branding
A1G
A1G
SSM2311CBZ-R21
SSM2311CBZ-REEL1
SSM2311CBZ-REEL71
SSM2311-EVALZ1
SSM2311-MINI-EVALZ1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
9-Ball Wafer Level Chip Scale Package [WLCSP]
9-Ball Wafer Level Chip Scale Package [WLCSP]
9-Ball Wafer Level Chip Scale Package [WLCSP]
Evaluation Board
CB-9-1
A1G
Evaluation Board, 7 mm × 7 mm
1 Z = RoHS Compliant Part.
Rev. 0 | Page 17 of 20
SSM2311
NOTES
Rev. 0 | Page 18 of 20
SSM2311
NOTES
Rev. 0 | Page 19 of 20
SSM2311
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06161-0-1/08(0)
Rev. 0 | Page 20 of 20
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