AK7742EN [AKM]
Consumer Circuit, 0.40 MM PITCH, QFN-48;
| 型号： | AK7742EN |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | Consumer Circuit, 0.40 MM PITCH, QFN-48 商用集成电路 |
| 文件： | 总19页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AK7742]
AK7742
24bit 2ch ADC + 24bit 4ch DAC with Audio DSP
GENERAL DESCRIPTION
The AK7742 is a highly integrated audio digital processor, including two stereo 24bit DAC’s and one
stereo ADC with input selector. The stereo DAC and ADC feature high performance, archiving 106dB and
96dB dynamic range respectively, 8kHz to 96kHz sampling rate are supported. The audio DSP has
1536step/fs parallel processing power, and 74k-bit delay memory allows surround processing, acoustic
effect and parametric equalizers. As the AK7742 is a RAM based DSP, it is programmable for user
requirements. The AK7742 is available in a space saving small 48pin LQFP package.
FEATURES
■ DSP:
- Word length: 24bit (Data RAM 24bit floating point)
- Instruction cycle: 13.6 ns (1536step/fs fs=48kHz; 9216step/fs fs=8kHz)
- Multiplier 20 x 16 → 36bit (double precision available)
- Divider 20 / 20 → 20bit
- ALU: 40bit arithmetic operation (overflow margin 4bit) 24bit floating point arithmetic and
logic operation
- Program RAM: 1536 x 36bit
- Coefficient RAM: 1536 x 16bit
- Data RAM: 1536 x 24-bit (24bit floating point)
- Delay RAM: 74kbit (3072 x 24bit)
- Sampling frequency: 8kHz ~ 96kHz
- Master / Slave operation
- Serial signal input port (4ch) MSB justified 24bit / LSB justified 24 / 20 / 16bit and I2S
- Serial signal output port (6ch) MSB justified 24bit / LSB justified 24 / 16bit and I2S
■ ADC: 2ch (stereo)
- 24bit 64 x Over-sampling delta sigma (fs=8kHz~48kHz)
- DR, S/N: 96dB (fs=48kHz, fully differential input)
- S/(N+D): 84dB (fs=48kHz)
- Differential, Single-end Inputs
- Digital HPF (fc=1Hz)
- 3:1 Analog input selector
- Digital Volume (24dB~-103dB, 0.5dB Step, Mute)
■ DAC: 4ch (two stereo pairs)
- 24bit 128 x Over-sampling advanced multi-bit (fs=8kHz~96kHz)
- DR, S/N: 106dB
- S/(N+D): 92dB
- Differential output
- Digital Volume (12dB~-115dB, 0.5dB Step, Mute)
■ DSP Through Mode
■ I2C BUS interface for micro-controller
■ Power supply: +3.3V ±0.3V, internal regulator for 1.8V
■ Operating temperature range: -20°C~70°C (AK7742EQ), -20°C~85°C (AK7742EN)
■ Package: 48pin LQFP, 0.5mm pitch (AK7742EQ)
48pin QFN, 0.4mm pitch (AK7742EN)
MS1024-E-00_PB
2008/11
- 1 -
[AK7742]
■ Block Diagram
LFLT
XTO
2
3
3
DVDD
VSS1
pull down
Hi-z
AVDD
VSS2
3
2
Open Drain
XTI
BICK
VCOM
LRCK
REF
CLKGEN & CONT
AVDRV
IRESETN
CKM[2:0]
ASEL[1:0]
3
TEST1
2
1
2
2
AIN3L,AIN3R
AIN2L,AIN2R
SELDO3
ADC
DVOL
CLKOE
0
1
CLKO/SDOUT3
AIN1LP,AIN1LN
AIN1RP,AIN1RN
0
4
SDOUTAD
DIN3
DOUT3
AOUT2LP
AOUT2LN
DVOL
DAC2
DAC1
SELDO5[1:0]
0
DOUT5
AOUT2RP
AOUT2RN
1
2
3
SDINDA2
JX0E
JX0
AOUT1LP
AOUT1LN
DVOL
SDIN2 / JX0
DIN2
0
AOUT1RP
AOUT1RN
DOUT4
DOUT1
1
2
3
SDINDA1
SELDO4[1:0]
JX1E
JX1
OUT1E
1
0
SDOUT1
SDIN1 / JX1
DIN1
SELDO1
SELDO2[1:0]
3
DOUT2
GPO
OUT2EN
2
SO/RDY/GPO/SDOUT2
I2CSEL
1
0
RDY
SO
MICIF
CAD1
SCL
CAD0
DS
SDA
Figure 1. Block Diagram
MS1024-E-00_PB
2008/11
- 2 -
[AK7742]
DLP0, DLP1
CP0, CP1
DP0, DP1
DLRAM
3072W x 24-Bit
OFREG
64W x 13-Bit
DRAM
1536W x 24-Bit
CRAM
1536W x 16-Bit
CBUS(16-Bit)
DBUS(24-Bit)
Micon I/F
Control
MPX16
X
MPX20
Serial I/F
PRAM
1536w x 36-Bit
DEC
Y
Multiply
16 x 20 → 36-Bit
PC
Stack : 5level(max)
TMP 8 x 24-Bit
24-Bit
36-Bit
PTMP(LIFO) 6 x 24-Bit
MUL
DBUS
SHIFT
40-Bit
40-Bit
A
B
2 x 24,16-Bit
DIN3 (ADC)
ALU
40-Bit
2 x 24,20,16-Bit DIN2
2 x 24,20,16-Bit DIN1
Overflow Margin: 4-Bit
40-Bit
2 x 24,16-Bit
2 x 24,16-Bit
2 x 24,20,16-Bit
DOUT5 (DAC2)
∼
DR0
3
DOUT4 (DAC1)
DOUT3
40-Bit
Over Flow Data
Generator
2 x 24,20,16-Bit DOUT2
DOUT1
2 x 24,20,16-Bit
Division
20÷20→20
Peak Detector
Figure 2. AK7742 DSP Block
MS1024-E-00_PB
2008/11
- 3 -
[AK7742]
■ Ordering Guide
AK7742EQ
-20 ∼ +70°C
-20 ∼ +85°C
48pin LQFP (0.5mm pitch)
48pin QFN (0.4mm pitch)
Evaluation board for the AK7742
AK7742EN
AKD7742
■ Pin Layout
AK7742EQ
37
38
39
40
41
42
43
44
45
46
47
48
AOUT1RN
AOUT1RP
AOUT1LN
CLKO/SDOUT3
24
23
22
21
20
19
18
17
16
15
14
13
BICK
LRCK
AOUT1LP
VSS1
VSS2
DVDD
48pin LQFP
VCOM
AVDD
I2CSEL
IRESETN
CKM[0]
CKM[1]
SDIN2/JX0
SDIN1/JX1
SDOUT1
(TOP VIEW)
AIN1RN
AIN1RP
AIN1LN
AIN1LP
AIN3R
pin
Input
Output
I/O
Power
MS1024-E-00_PB
2008/11
- 4 -
[AK7742]
AK7742EN
AOUT1RN
37
38
CLKO/SDOUT3
BICK
24
23
22
21
20
19
18
17
AOUT1RP
AOUT1LN
AOUT1LP
LRCK
VSS2
39
40
DVDD
I2CSEL
IRESETN
VSS1
41
42
43
44
45
46
47
48
AK7742EN
VCOM
AVDD
Top View
CKM[0]
AIN1RN
CKM[1]
16
15
AIN1RP
AIN1LN
SDIN2/JX0
SDIN1/JX1
SDOUT1
AIN1LP
AIN3R
14
13
MS1024-E-00_PB
2008/11
- 5 -
[AK7742]
PIN FUNCTION
No.
1
2
3
4
Pin name
AIN3L
AIN2R
AIN2L
AVDD
VSS1
I/O
Function
Classification
Analog input
Analog input
Analog input
Analog power supply
Analog power supply
I
I
I
ADC Lch Single-end input 3 pin
ADC Rch Single-end input 2 pin
ADC Lch Single-end input 2 pin
Power supply pin for analog section 3.0V ~ 3.6V
Analog ground 0V
5
Filter connection pin for PLL
6
7
LFLT
O
Analog output
Test
Connect C=12nF to VSS1. “L” output during initial reset.
Test pin (internal pull-down resistor)
Connect to VSS2
Clock mode select pin 2
Power supply pin for digital section 3.0V ~ 3.6V
Digital ground 0V
TEST1
I
I
8
9
CKM[2]
DVDD
Mode select
Digital power supply
Digital power supply
10 VSS2
Master clock input pin
11 XTI
I
When using a crystal oscillator, connect it between this pin and XTO.
When using external main clock, input to this pin with CMOS level.
Crystal oscillator output pin
Clock
When using a crystal oscillator, connect it between this pin and XTI.
When not using crystal oscillator, leave open. Output during initial reset is
not determined.
12 XTO
O
Clock
O DSP serial data output pin
“L” output during initial reset
13 SDOUT1
Data interface
14 SDIN1/JX1
15 SDIN2/JX0
16 CKM[1]
17 CKM[0]
18 IRESETN
I
I
I
I
I
Serial data input pin 1 / JX1
Serial data input pin 2 / JX0
Clock mode select pin 1
Clock mode select pin 0
Reset pin (for initialization)
Data interface
Data interface
Mode select
Mode select
Reset
I2CBUS select pin
19 I2CSEL
I
Microcomputer I/F
Connect to DVDD
20 DVDD
21 VSS2
Power supply pin for digital section 3.0V ~ 3.6V
Digital ground 0V
Digital power supply
Digital power supply
I/O LR channel select clock pin
“L” output during initial reset with master mode.
I/O Serial bit clock pin
“L” output during initial reset with master mode.
O Clock output / DSP serial data output pin
“L” output during initial reset
22 LRCK
Data interface
Data interface
Clock
23 BICK
24 CLKO/SDOUT3
Serial data output pin / Data write ready output pin / General purpose output
SO/RDY/GPO/
SDOUT2
25
O
/ DSP serial data output pin
“L” output during initial reset
Microcomputer I/F
26 SDA
27 SCL
28 CAD0
29 CAD1
30 VSS1
I/O SDA I2C bus interface
Microcomputer I/F
Microcomputer I/F
Microcomputer I/F
Microcomputer I/F
Analog power supply
I
I
I
SCL I2C bus interface
I2C bus address pin 0
I2C bus address pin 1
Analog ground 0V
MS1024-E-00_PB
2008/11
- 6 -
[AK7742]
AVDRV Pin
31 AVDRV
O
Analog power supply
Connect 1μF to VSS1. Never to use for external circuit. “L” output during
initial reset
32 AVDD
Power supply pin for analog section 3.0V ~ 3.6V
O DAC2 Rch differential inverted analog output pin
“Hi-Z” output during initial reset
Analog power supply
Analog output
33 AOUT2RN
O DAC2 Rch differential non-inverted analog output pin
“Hi-Z” output during initial reset
O DAC2 Lch differential inverted analog output pin
“Hi-Z” output during initial reset
O DAC2 Lch differential non-inverted analog output pin
“Hi-Z” output during initial reset
O DAC1 Rch differential inverted analog output pin
“Hi-Z” output during initial reset
O DAC1 Rch differential non-inverted analog output pin
“Hi-Z” output during initial reset
O DAC1 Lch differential inverted analog output pin
“Hi-Z” output during initial reset
34 AOUT2RP
35 AOUT2LN
36 AOUT2LP
37 AOUT1RN
38 AOUT1RP
39 AOUT1LN
Analog output
Analog output
Analog output
Analog output
Analog output
Analog output
O DAC1 Lch differential non-inverted analog output pin
“Hi-Z” output during initial reset
40 AOUT1LP
41 VSS1
Analog output
Analog ground 0V
Analog power supply
Analog common voltage
42 VCOM
O
Analog output
Connect 0.1μF and 2.2μF in parallel to VSS1. Never to use for external
circuit. “L” output during initial reset
43 AVDD
44 AIN1RN
45 AIN1RP
46 AIN1LN
47 AIN1LP
48 AIN3R
Power supply pin for analog section 3.0V ~ 3.6V
Analog power supply
Analog input
Analog input
Analog input
Analog input
I ADC Rch differential inverted analog input pin
I ADC Rch differential non-inverted analog input pin
I ADC Lch differential inverted analog input pin
I
I
ADC Lch differential non-inverted analog input pin
ADC Rch Single-end input 3 pin
Analog input
Note:
Digital input pins are never to be left open.
If analog input pins (AIN1LP, AIN1LN, AIN1RP, AIN1RN, AIN2L, AIN2R, AIN3L, AIN3R) are not used, leave
them open.
MS1024-E-00_PB
2008/11
- 7 -
[AK7742]
ABSOLUTE MAXMUM RATING
(VSS1=VSS2=0V: Note 1)
Item
Symbol
min
max
Unit
Power supply voltage (AVDD= DVDD)
Analog
AVDD
DVDD
IIN
-0.3
-0.3
-
4.3
4.3
±10
V
V
mA
Digital
Input current (except for power supply pin)
Analog input voltage (Note 2)
AIN1LP, AINL1N, AIN1RP, AINR1N,
AIN2L, AIN2R, AIN3L, AIN3R
Digital input voltage (Note 3)
VINA
-0.3
(AVDD+0.3) or 4.3
V
VIND
Ta
Ta
-0.3
-20
-20
-65
(DVDD+0.3) or 4.3
V
Operating ambient
temperature
AK7742EQ
AK7742EN
70
70
150
ºC
ºC
ºC
Storage temperature
Tstg
Note 1. All indicated voltages are with respect to ground. VSS1 and VSS2 must be the same voltage.
Note 2. The maximum value of analog input voltage is smaller value between (AVDD+0.3)V and 4.3V.
Note 3. The maximum value of digital input voltage is smaller value between (DVDD+ 0.3)V and 4.3V.
WARNING: Operating at or beyond these limits may result in permanent damage to the device. Normal operation is
not guaranteed at these critical conditions.
RECOMMENDED OPERATING CONDITIONS
(VSS1=VSS2=0V: Note 1)
Item
Symbol
min
typ
max
Unit
Power supply voltage
Analog
Digital
AVDD
DVDD
3.0
3.0
3.3
3.3
3.6
3.6
V
V
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in the datasheet.
Note) Do not turn off the power of the AK7742 during the power supplies of surrounding devices are turned on. DVDD
must not exceed the pull-up of SDA and SCL of I2C BUS. (The diode exists for DVDD in the SDA and SCL pins.)
MS1024-E-00_PB
2008/11
- 8 -
[AK7742]
ANALOG CHARACTERISTICS
■ ADC Characteristics
(Ta=25ºC; AVDD=DVDD=3.3V; BICK=64fs; signal frequency 1kHz; Measurement bandwidth=20Hz~20kHz,
fs=48kHz, ADC differential input, CKM mode 0 (CKM[2:0]=000), unless otherwise specified)
Parameter
min
typ
max
Unit
Resolution
Dynamic characteristics
S/(N+D) (-1dBFS)
Dynamic range (A-weighted)
S/N (A-weighted)
24
Bits
Stereo
ADC
(Note 4)
(Note 4)
(Note 4)
76
88
88
90
84
96
96
dB
dB
dB
dB
Inter-channel isolation (f=1kHz) (Note 5)
DC accuracy
105
Channel gain mismatch
0.1
0.3
dB
Analog input
Input voltage (differential input) (Note 6)
±1.85
1.85
41
±2.00
2.00
62
±2.15
2.15
Vp-p
Vp-p
kΩ
Input voltage (single-end input)
Input impedance
(Note 7)
(Note 8)
Note 4. This value is not guaranteed for single-ended inputs.
Note 5. Indicates isolation between L and R when -1dBFS signal is applied.
Note 6. Target input pins are AIN1LP, AIN1LN, AIN1RP, AIN1RN.
Note 7. Target input pins are AIN2L, AIN2R, AIN3L, AIN3R.
Note 8. Target input pins are AIN1LP, AIN1LN, AIN1RP, AIN1RN, AIN2L, AIN2R, AIN3L, AIN3R.
■ DAC Characteristics
(Ta=25ºC; AVDD=DVDD=3.3V; BICK=64fs; signal frequency 1kHz; Measurement bandwidth=20Hz~20kHz,
fs=48kHz, RL=5KΩ, CL= 15pF; CKM mode 0 (CKM[2:0]=000), unless otherwise specified)
Parameter
min
typ
max
Unit
Resolution
Dynamic characteristics
S/(N+D) (0dBFS)
Dynamic range (A-weighted)
S/N (A-weighted)
24
Bits
Stereo
DAC
80
90
90
90
92
dB
dB
dB
dB
106
106
100
Inter-channel isolation (f=1kHz)(Note 9)
DC accuracy
Channel gain mismatch
Analog output
Output voltage (Note 10)
Load resistance
0.2
0.5
3.96
30
dB
3.36
5
3.66
Vp-p
kΩ
pF
Load capacitance
Note 9. Indicates isolation between each DAC’s of Lch and Rch when -1dBFS signal is applied.
Note 10. Full scale output voltage. The output voltage scales with AVDD.
MS1024-E-00_PB
2008/11
- 9 -
[AK7742]
DC CHARACTERISTICS
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V)
Parameter
High level input voltage
Low level input voltage
SCL, SDA High level input voltage
SCL, SDA Low level input voltage
High level output voltage Iout=-100μA
Low level output voltage Iout=100μA (Note 12)
SDA Low level output voltage Iout=3mA
Input leak current
Input leak current (pull-down)
Input leak current XTI pin
Symbol
VIH
VIL
VIH
VIL
VOH
VOL
VOL
Iin
min
80%DVDD
typ
max
Unit
V
V
V
V
V
V
V
(Note 11)
(Note 11)
20%DVDD
30%DVDD
70%DVDD
DVDD-0.5
0.5
0.4
±10
(Note 13)
(Note 14)
μA
μA
μA
Iid
Iix
22
26
Note 11. Except for the SCL, SDA pin.
Note 12. Except for the SDA pin.
Note 13. Except for the TEST1 pin, XTI pin.
Note 14. The TEST1 pin has an internal pull-down device, nominally 150kΩ.
POWER CONSUMPTION
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V(typ=3.3V, max=3.6V))
Parameter
min
typ
max
Unit
Power supply current (Note 15)
Normal Operation
AVDD+DVDD
75
2
122
mA
mA
Reset (IRESETN= “L” reference data)
AVDD+DVDD (Note 16)
Note 15. Depends on the system frequency and contents of DSP program.
Note 16. This is a reference value when using a crystal oscillator. Since most of the supply current at the initial reset state
is in the oscillator section, the value may vary according to the crystal type and the external circuit. This value is
just reference.
MS1024-E-00_PB
2008/11
- 10 -
[AK7742]
DIGITAL FILTER CHARACTERISTICS
■ ADC
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN), AVDD=DVDD=3.0~3.6V, fs=48kHz; Note 17)
Parameter
Pass band (±0.005dB)
(-0.02dB)
(-6.0dB)
Stop band
Pass band ripple
Stop band attenuation (Note 19, Note 20)
Group delay distortion
Group delay (Ts=1/fs)
Symbol
min
0
typ
max
21.5
Unit
kHz
kHz
kHz
kHz
dB
dB
μs
Ts
(Note 18)
PB
21.768
24.00
SB
PR
SA
∆GD
GD
26.5
80
(Note 18)
±0.005
0
30
Digital filter + Analog filter characteristics
Amplitude characteristic 20Hz~20.0kHz
±0.01
dB
Note 17. Each parameter is related to the sampling frequency (fs). HPF response is not included.
Note 18. Pass band is from DC to 21.5kHz when fs=48kHz.
Note 19. Stop band is from 26.5kHz to 3.0455MHz when fs=48kHz.
Note 20. When fs=48kHz, the analog modulator samples the analog input at 3.072MHz. Therefore the input signal is not
attenuated by the digital filter in multiple bands (n x 3.072MHz ±21.99kHz; n=0, 1, 2, 3 …) of the sampling
frequency.
■ DAC
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN), AVDD=DVDD=3.0~3.6V, fs=48kHz; Note 17)
Parameter
Symbol
min
typ
max
Unit
Digital filter
Pass band ±0.07dB
(-6.0dB)
Stop band
Pass band ripple
Stop band attenuation
(Note 21)
(Note 21)
PB
0
-
26.2
21.7
-
kHz
kHz
kHz
dB
dB
Ts
24.0
SB
PR
SA
GD
±0.01
64
-
Group delay
(Ts=1/fs) (Note 22)
24
Digital filter + Analog filter
Amplitude characteristic 0~20.0kHz
±0.5
dB
Note 21. Pass band and Stop band parameter is related to sampling frequency(fs). PB=0.4535fs (at-0.05dB),
SB=0.5465fs.
Note 22.The digital filter’s delay is calculated as the time from setting 24-bit data into the input register until an analog
signal is output.
MS1024-E-00_PB
2008/11
- 11 -
[AK7742]
SWITCHING CHARACTERISTICS
■ System Clock
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
min
typ
max
Unit
XTI
a)with a crystal oscillator
Frequency(256fs)
CKM[2:0]= 000
fs=44.1KHz
fs=48KHz
fXTI
-
11.2896
12.288
-
MHz
b)with an external clock
Duty cycle
Frequency(256fs)
CKM[2:0]= 000, 010
Frequency (384fs)
CKM[2:0]= 001
Duty
fXTI
40
11.0
50
60
12.4
%
MHz
fs=44.1KHz
fs=48KHz
11.2896
12.288
16.9344
18.432
fs=44.1KHz
fs=48KHz
fXTI
Fs
16.5
18.6
96
MHz
kHz
7.35
48
LRCK frequency (Note 23)
BICK frequency
32
64
64
64
fs
ns
ns
a) CKM[2:0]= 001, 010
High level width
Low level width
Frequency
tBCLKH
tBCLKL
fBCLK
0.46
3.072
6.144
MHz
64
50
fs
%
b) CKM[2:0]= 011 (Note 25)
Duty cycle
Duty
40
60
Frequency
fBCLK
2.75
3.072
3.1
MHz
32
50
fs
%
c) CKM[2:0]= 100 (Note 26)
Duty cycle
Duty
40
60
Frequency
fBCLK
230
256
258
kHz
64
50
fs
%
d) CKM[2:0]= 101 (Note 27)
Duty cycle
Duty
40
60
Frequency
fBCLK
460
512
516
kHz
Note 23. LRCK frequency and sampling rate (fs) should be the same.
Note 24. The BICK must be divided 32, 48 or 64 clocks correctly. (BICK can be selected from 32fs, 48fs or 64fs)
Note 25. When BICK is resource of internal MCLK. The BICK must be divided 64 clocks correctly. 64fs fixed.
Note 26. When BICK is resource of internal MCLK. The BICK must be divided 32 clocks correctly. 32fs fixed.
Note 27. When BICK is resource of internal MCLK. The BICK must be divided 64 clocks correctly. 64fs fixed.
MS1024-E-00_PB
2008/11
- 12 -
[AK7742]
■ Reset
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
min
typ
max
Unit
IRESET
(Note 28)
tRST
600
ns
Note 28. It is necessity that the power is supplied and master clock is input when the IRESET pin goes to “H”.
■ Audio Interface
1) SDIN1, SDIN2, SDOUT1, SDOUT2, SDOUT3
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V, CL=20pF)
Parameter
Symbol
min
typ
max
Unit
Slave mode
BICK frequency
BICK low level width
BICK high level width
Delay time from BICK “↑” to LRCK (Note 29)
Delay time from LRCK to BICK “↑” (Note 29)
Serial data input latch setup time
Serial data input latch hold time
Delay time from LRCK to serial data output
Delay time from BICK “↓” to serial data output (Note 30) tBSOD
fBCLK
tBCLKL
tBCLKH
tBLRD
tLRBD
tBSIDS
tBSIDH
tLRD
32
150
150
40
40
40
40
-10
-10
64
fs
ns
ns
ns
ns
ns
ns
ns
ns
40
40
Master mode
BICK frequency
BICK duty cycle
Delay time from BICK “↑” to LRCK
Delay time from LRCK to BICK “↑”
Serial data input latch setup time
Serial data input latch hold time
fBCLK
64
50
fs
%
ns
ns
ns
ns
ns
tBLRD
tLRBD
tBSIDS
tBSIDH
40
40
40
40
-30
Delay time from BICK “↓” to serial data output (Note 30) tBSOD
40
Note 29. BICK rising edge must not occur at the same time as LRCK edge.
Note 30. The serial data output is synchronized to BICK falling edge, and held until next BICK falling (spec -10ns) in
Slave mode. In case of the LRCK edge comes before BICK edge, data will be held until LRCK edge (spec
-10ns). In Master mode, serial data is held until 30ns before falling edge of BICK. Therefore, please use BICK
rising edge in both slave and master modes for a safety latch.
.
MS1024-E-00_PB
2008/11
- 13 -
[AK7742]
■ I2CBUS Interface
(Ta=-20°C ~70°C (AK7742EQ), Ta=-20°C ~85°C (AK7742EN); AVDD=DVDD=3.0~3.6V)
Parameter
Symbol
min
typ
max
Unit
I2C Timing
SCL clock frequency
fSCL
tBUF
tHD:STA
400
KHz
μs
μs
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first Clock
pulse)
1.3
0.6
Clock Low Time
Clock High Time
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
1.3
0.6
0.6
0
μs
μs
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Pulse Width of Spike Noise Suppressed
by Input Filter
μs
μs
μs
μs
μs
μs
ns
0.9
0.1
0.3
0.3
tF
tSU:STO
tSP
0.6
0
50
Capacitive load on bus
Cb
400
pF
Note 31. I2C is a registered trademark of Philips Semiconductors.
MS1024-E-00_PB
2008/11
- 14 -
[AK7742]
PACKAGE (AK7742EQ)
48pin LQFP (Unit: mm)
1.70Max
9.0 ± 0.2
0.13 ± 0.13
7.0
1.4± 0.05
36
25
37
24
48
13
12
0.09 ∼ 0.20
0.5
0.22 ± 0.08
0.10 M
0° ∼ 10°
0.10
0.3 ∼ 0.75
■ Materials and Lead Specification
Package:
Epoxy
Lead frame:
Lead-finish:
Copper
Soldering (Pb free) plate
MS1024-E-00_PB
2008/11
- 15 -
[AK7742]
PACKAGE (AK7742EN)
48pin QFN (Unit: mm)
6.20 ± 0.10
6.00 ± 0.05
0.45 ± 0.10
0.20 ± 0.05
B
Exposed
Pad
48
48
4-C0.5
1
1
12
A
4.40TYP
0.40
0.18
±0.05
M
0.05
C
C
0.05
0.45 ±0.10
Note: The exposed pad must be open or connected to the ground.
■ Materials and Lead Specification
Package:
Epoxy
Lead frame:
Lead-finish:
Copper
Soldering (Pb free) plate
MS1024-E-00_PB
2008/11
- 16 -
[AK7742]
MARKING (AK7742EQ)
AKM
AK7742EQ
XXXXXXX
1
XXXXXXX: Date code identifier (7 digits)
MARKING (AK7742EN)
AKM
AK7742EN
XXXXXXX
48
1
XXXXXXX: Date code identifier (7 digits)
MS1024-E-00_PB
2008/11
- 17 -
[AK7742]
REVISION HISTORY
Page Contents
Date (YY/MM/DD) Revision Reason
08/11/07 00 First Edition
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
MS1024-E-00_PB
2008/11
- 18 -
[AK7742]
Thank you for your access to AKEMD product information.
More detail product information is available, please contact our
sales office or authorized distributors.
MS1024-E-00_PB
2008/11
- 19 -
相关型号：
©2020 ICPDF网 联系我们和版权申明