AKD4621-B [AKM]
AK4621 Evaluation board Rev.2; AK4621评估板Rev.2号
| 型号： | AKD4621-B |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | AK4621 Evaluation board Rev.2 |
| 文件： | 总50页 (文件大小：979K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
[AKD4621-B]
AKD4621-B
AK4621 Evaluation board Rev.2
GENERAL DESCRIPTION
The AKD4621-B is an evaluation board for the AK4621, the 24Bit A/D & D/A converter. The AKD4621-B
can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D→D/A). The
AKD4621-B also has the digital audio interface and can achieve the interface with digital audio systems
via opt-connector.
Ordering guide
AKD4621-B
--- Evaluation board for AK4621
(Cable for connecting with printer port of IBM-AT compatible PC
and control software are packed with this. This control software
does not operate on Windows NT.)
FUNCTION
Digital interface
-
-
DIT (AK4114): optical or BNC
DIR (AK4114): optical or BNC
10pin header for serial control interface
-15V +15V
AGND DGND
Regulator
BNC
LIN
Input
Buffer
Opt In
AK4114
(DIR&DIT)
RIN
Opt Out
BNC
AK4621
Output
Buffer
LOUT
ROUT
10pin Header
Control Data
Figure 1. AKD4621-B Block Diagram
* Circuit diagram are attached at the end of this manual.
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[AKD4621-B]
Evaluation Board Manual
Operation sequence
1) Set up of the power supply lines
Each of the power supply lines should be distributed from the power supply units.
Name
Color
Typ
Using
Default setting
of jack of jack Voltage
+15V
Green
+15V
Power supply for the plus terminal of OPAmp
Power supply for the regulator: T1: +15V→+5V
(Power supply for AVDD and VREF of AK4621,
power supply for Bias of OPAmp, and
Connect to +15V
(Must be connected)
power supply for the Regulator: T2: +5V→+3.3V
(Power supply for DVDD and TVDD of AK4621))
Power supply for the regulator: T3: +15V→+3.3V
(Power supply for AVDD, DVDD, TVDD of AK4114,
Power supply for logic)
-15V
GND
Blue
-15V
0V
Power supply for the minus terminal of OPAmp
Connect to -15V
(Must be connected)
Black
Analog ground
Digital ground
Connect to GND
(Must be connected)
Table 1. Set up of the power supply lines
2) Set up the evaluation modes, jumper pins and DIP switch. (See the followings.)
3) Power on
The AK4621 should be reset once bringing SW2 (PDN) “L” upon power-up.
<KM100802>
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[AKD4621-B]
Evaluation modes
Applicable evaluation modes
(1) Evaluation of A/D-D/A Loop back (Default)
(2) Evaluation of DAC
(3) Evaluation of ADC
1) Evaluation of A/D-D/A Loop back (Default)
1-1) Sampling speed & MCLK frequency
a) Parallel mode (Default)
Sampling
Speed of
AK4621
Normal
Speed
MCLK
Frequency of
AK4621
SW1-1 SW1-4 SW1-6 SW1-7
SW3-4
SW3-5
(P/S)
(DFS0) (CKS1) (CKS0) (OCKS1) (OCKS0)
ON
OFF
ON
OFF
OFF
ON
ON
ON
OFF
OFF
512fs
256fs
(Default)
Double
Speed
ON
OFF
Table 2. Sampling Speed & Master clock Frequency in parallel mode
* Parallel mode does not support quad speed mode.
b) Serial mode
Sampling
Speed of
AK4621
MCLK
Frequency of
AK4621
SW1 DFS1 DFS0 CMODE CKS1 CKS0
SW3-4
(OCKS1) (OCKS0)
SW3-5
(P/S)
bit
bit
bit
bit
bit
Normal
Speed
OFF
0
0
0
0
1
ON
OFF
512fs
Double
Speed
Quad Speed
OFF
OFF
0
1
1
0
0
0
0
0
1
1
OFF
ON
OFF
ON
256fs
128fs
Table 3. Sampling Speed & Master clock Frequency in serial mode
* In serial mode, SW1-4 (DFS0), SW1-6 (CKS1) and SW1-7 (CSK0) should be always “OFF”, and DFS1, DFS0, CKS1,
CKS0 and CMODE bits in the AK4621 should be set via the printer port (PORT3).
<KM100802>
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[AKD4621-B]
1-2) AK4114’s master clock mode & reference X’tal frequency
SW3-6 SW3-7
Mode
1
PLL
X'tal
Clock source SDTO
(CM1) (CM0)
OFF ON
OFF
ON
X'tal DAUX (Default)
Table 4. AK4114’S Clock Operation Mode
SW3-1
(XTL1)
ON
SW3-2
(XTL0)
OFF
X’tal Frequency
24.576MHz
(Default)
Table 5. Reference X’tal frequency
1-3) Set up the digital filter
a) Parallel mode (Default)
SW1-2
(SDFIL)
Digital Filter
OFF
Short Delay
ON
Sharp Roll-off
(Default)
Table 6. Digital Filter Selection in parallel mode
b) Serial mode
SW1-2
(SDFIL)
SDAD
bit
Digital Filter
OFF
OFF
0
1
Sharp Roll-off
Short Delay
Table 7. Digital Filter Selection in serial mode
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[AKD4621-B]
2) Evaluation of D/A using DIR. (Optical link)
The DIR generates MCLK, BICK, LRCK and SDATA from the received data through optical
connector (PORT1). PORT1 is also used for the evaluation using such as CD test disk.
BNC connector is recommended for an evaluation of the Sound quality.
2-1) DIR input interface (Default: JP2 (RX3)="OPT")
JP2
Jumper
(RX3)
OPT (Default) or BNC
Normal Speed & Double Speed
Quad Speed
BNC
Table 8. DIR Input Interface
2-2) Sampling speed & MCLK frequency
a) Parallel mode (Default)
Sampling
MCLK
Frequency of
AK4621
SW1-1 SW1-4 SW1-6 SW1-7
SW3-4
SW3-5
Speed of
AK4621
Normal
Speed
Normal
Speed
(P/S)
(DFS0) (CKS1) (CKS0) (OCKS1) (OCKS0)
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
OFF
256fs
512fs
256fs
(Default)
ON
Double
Speed
ON
OFF
Table 9. Sampling Speed & Master clock Frequency in parallel mode
* Parallel mode does not support quad speed mode.
b) Serial mode
Sampling
Speed of
AK4621
Normal
Speed
MCLK
Frequency of
AK4621
SW1-1 DFS1 DFS0 CMODE CKS1 CKS0
SW3-4
(OCKS1) (OCKS0)
SW3-5
(P/S)
OFF
OFF
bit
bit
bit
bit
bit
0
0
0
0
0
OFF
ON
OFF
OFF
256fs
512fs
Normal
Speed
0
0
0
0
1
Double
Speed
Quad Speed
OFF
OFF
0
1
1
0
0
0
0
0
1
1
OFF
ON
OFF
ON
256fs
128fs
Table 10. Sampling Speed & Master clock Frequency in serial mode
* In serial mode, SW1-4 (DFS0), SW1-6 (CKS1) and SW1-7 (CSK0) should be always “OFF”, and DFS1, DFS0, CKS1,
CKS0 and CMODE bits in the AK4621 should be set via the printer port (PORT3).
<KM100802>
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[AKD4621-B]
2-3) AK4114’s master clock mode & reference X’tal frequency
SW3-6 SW3-7
Mode
0
PLL
X'tal
Clock source SDTO
PLL RX
(CM1) (CM0)
OFF OFF
ON
OFF
Table 11. Clock Operation Mode
SW3-1
(XTL1)
ON
SW3-2
(XTL0)
ON
X’tal Frequency
OFF
Table 12. Reference X’tal frequency
2-4) Set up the digital filter
a) Parallel mode (Default)
SW1-2
(SDFIL)
Digital Filter
OFF
ON
Minimum Delay
Sharp Roll-off
Table 13. Digital Filter Selection in parallel mode
b) Serial mode
Set up the register of the AK4621 via the pint port (PORT3).
SW1-2
(SDFIL)
OFF
SDAD SLOW
Digital Filter
bit
bit
0
0
Sharp Roll-off
Slow Roll-off
OFF
0
1
OFF
1
0
Minimum Delay
Table 14. Digital Filter Selection in serial mode
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[AKD4621-B]
3) Evaluation of A/D using DIT. (Optical link)
DIT generates audio bi-phase signal from received data and which is output through optical connector (PORT2).
It is possible to connect AKM’s D/A converter evaluation boards on the digital-amplifier which equips DIR
input.
3-1) DIT output interface (Default: JP7 (TX) ="OPT")
JP7
Jumper
(TX)
OPT (Default) or BNC
Normal Speed & Double Speed
Quad Speed
BNC
Table 15. DIT Output Interface
3-2) Sampling speed & MCLK frequency
a) Parallel mode (Default)
Sampling
MCLK
Frequency of
AK4621
SW1-1 SW1-4 SW1-6 SW1-7
SW3-4
SW3-5
Speed of
AK4621
Normal
Speed
Normal
Speed
(P/S)
(DFS0) (CKS1) (CKS0) (OCKS1) (OCKS0)
ON
OFF
OFF
ON
OFF
OFF
OFF
OFF
ON
ON
OFF
ON
OFF
OFF
OFF
256fs
512fs
256fs
(Default)
ON
Double
Speed
ON
OFF
Table 16. Sampling Speed & Master clock Frequency in parallel mode
* Parallel mode does not support quad speed mode.
<KM100802>
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[AKD4621-B]
b) Serial mode
Sampling
Speed of
AK4621
Normal
Speed
MCLK
Frequency of
AK4621
SW1-1 DFS1 DFS0 CMODE CKS1 CKS0
SW3-4
(OCKS1) (OCKS0)
SW3-5
(P/S)
OFF
OFF
bit
bit
bit
bit
bit
0
0
0
0
0
OFF
ON
OFF
OFF
256fs
512fs
Normal
Speed
0
0
0
0
1
Double
Speed
Quad Speed
OFF
OFF
0
1
1
0
0
0
0
0
1
1
OFF
ON
OFF
ON
256fs
128fs
Table 17. Sampling Speed & Master clock Frequency in serial mode
* In serial mode, SW1-4 (DFS0), SW1-6 (CKS1) and S1-7 (CSK0) should be always “OFF”, and DFS1, DFS0, CKS1,
CKS0 and CMODE bits in the AK4621 should be set via the printer port (PORT3).
3-3) AK4114’s master clock mode & reference X’tal frequency
3-3-1) PLL is used as clock source
Synchronized signal should be set via PORT1 (optical) or J6 (BNC).
SW3-6 SW3-7
(CM1) (CM0)
OFF OFF
Mode
0
PLL
ON
X'tal
OFF
Clock source SDTO
PLL RX
Table 18. Clock Operation Mode (PLL)
SW3-1
(XTL1)
ON
SW3-2
(XTL0)
ON
X’tal Frequency
OFF
Table 19. Reference X’tal frequency (PLL)
3-3-2) X’tal is used as clock source (Default)
SW3-6 SW3-7
(CM1) (CM0)
Mode
1
PLL
OFF
X'tal
ON
Clock source SDTO
X’tal DAUX (Default)
OFF
ON
Table 20. Clock Operation Mode (X’tal)
SW3-1
(XTL1)
SW3-2
(XTL0)
X’tal Frequency
ON
OFF
24.576MHz
(Default)
Table 21. Reference X’tal frequency (X’tal)
<KM100802>
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[AKD4621-B]
3-4) Set up the digital filter
a) Parallel mode (Default)
SW1-2
(SDFIL)
OFF
Digital Filter
Short Delay
ON
Sharp Roll-off
(Default)
Table 22. Digital Filter Selection in parallel mode
b) Serial mode
SW1-2
(SDFIL)
SDAD
bit
Digital Filter
OFF
OFF
0
1
Sharp Roll-off
Short Delay
Table 23. Digital Filter Selection in serial mode
<KM100802>
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[AKD4621-B]
Set up of DIP Switch: SW1, SW3
1) Set-up of SW1 (Mode set-up of AK4621)
1-1) Audio data format in parallel mode
DIF
Mode
SDTO
SDTI
LRCK
BICK
(SW1-5)
24bit MSB Justified
I2S Compatible
H/L
L/H
(Default)
2
3
OFF
24bit MSB Justified
I2S Compatible
≥48fs
≥48fs
ON
Table 24. Audio data format (Parallel mode)
1-2) De-emphasis control in parallel mode
DEM0 pin
MODE
(SW1-3)
OFF
ON
ON (44.1KHz)
OFF
(Default)
Table 25. De-emphasis control (Parallel mode)
1-3) Parallel mode/ serial mode
P/S pin
MODE
(SW1-1)
OFF
ON
Serial
Parallel
(Default)
Table 26. Set up P/S pin
2) Set-up of SW3 (AK4114’s mode set-up)
2-1) Audio data format
DIF0
Mode
SDTO
SDTI
LRCK
BICK
(SW3-3)
24bit MSB Justified
I2S Compatible
H/L
L/H
(Default)
4
5
OFF
24bit MSB Justified
I2S Compatible
≥48fs
≥48fs
ON
Table 27. Audio data format
* DIF1=L and DIF2=H are fixed in AKD4621-B evaluation board.
Other Jumper pin set up
JP3, JP4, JP5, JP6: Input mode selection of A/D converter.
DIFF: Analog differential input mode. <Default>
SINGLE: Analog single-end mode can not be selected on this board.
JP2, JP7: The interface selection of digital input and output.
OPT: Select the optical connector.
BNC: Select the BNC connector. <Default>
<KM100802>
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[AKD4621-B]
Toggle Switch: SW2
[SW2]: Resets the AK4621 and the AK4114. Keep “H” during normal operation.
However, “L” must be input once after power supply is done.
Serial control mode
The AK4621 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3
(CR-I/F) with PC by 10-wire flat cable packed with the AKD4621-B.
Take care of the direction of connector. There is a mark at pin#1.
CSN
CCLK
Connect
AKD4621-B
CDTI
CDTO
PC
10 wire
10pin
10pin Header
flat cable
Connector
Figure 2. Connect of 10 wire flat cable
<KM100802>
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[AKD4621-B]
Analog Input Buffer Circuit
The AK4621 can accept input voltages from AGND to AVDD. The input signal range scales with the VREF voltage and
is nominally 2.82Vpp (VREF = 5V). Figure 3 shows an input buffer circuit example. This is a fully differential input
buffer circuit with an inverted amplifier (fc=370KHz,gain: −10dB).
The capacitor of 10nF between AINL+/− (AINR+/−) decreases the clock feed through noise of the modulator, and
composes a 1st order LPF (fc=360kHz) with a 22Ω resistor before the capacitor.
910
4.7k
VP+
470p
4.7k
47μ
47μ
3k
2.82Vpp
10n
Analog In
9.3Vpp
22
AIN+
VP-
Bias
NJM5532
910
AK4621
470p
AVDD
10k
3k
22
AIN-
0.1μ 10μ
AVDD = 5V
VP+ = 15V
VP- = -15V
Bias
Bias
2.82Vpp
10k
Figure 3. Input buffer circuit in differential input mode
<KM100802>
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[AKD4621-B]
Analog Output Buffer Circuit
The differential output circuit (2nd order LPF,fc=182KHz,Q=0.637,G=+3.9dB) and LPF(1st order LPF, fc=284KHz,
G=-0.84dB) is implemented on board. The differential outputs of AK4621 is buffered by non-inverted circuit and output
via Cannon connector (differential output). LPF adds differential outputs. NJM5534D is used for op-amp on this board
that has low noise and high voltage torelance characteristics. Analog signal is output via BNC connectors on the board.
The output level is about 2.8Vrms (typ@VREF=5.0V) by BNC.
+15
3.3n
-15
+
10u
100u
180
3.9n
0.1u
7
4
3
2
+
AOUTL-
6
+
-
330
10u
+
0.1u
10u
NJM5534D
560
+
0.1u
1.0n
680
100
2
-
4
6
620
620
Lch
+
3
1.0n 7NJM5534D
3.3n
180
3.9n
+
10u
10u
100u
0.1u
7
+
3
AOUTL+
+
-
6
2
330
+ 10u
0.1u
4
NJM5534D
+
0.1u
680
Figure 4. Output buffer circuit
* AKM assumes no responsibility for the trouble when using the above circuit examples.
<KM100802>
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[AKD4621-B]
Control Soft Manual
■ Evaluation Board and Control Soft Settings
1. Set an evaluation board properly.
2. Connect the evaluation board to an IBM PC/AT compatible PC by a 10wire flat cable. Be aware of the direction of
the 10pin header. When running this control soft on the Windows 2000/XP, the driver which is included in the CD
must be installed. Refer to the “Driver Control Install Manual for AKM Device Control Software” for installing the
driver. When running this control soft on the windows 95/98/ME, driver installing is not necessary. This control soft
does not support the Windows NT.
3. Proceed evaluation by following the process below.
■ Operation Screen
1. Start up the control program following the process above.
The operation screen is shown below.
Figure 5. Window of [ FUNCTION]
<KM100802>
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[AKD4621-B]
■ Operation Overview
Function, register map and testing tool can be controlled by this control soft. These controls are selected by upper tabs.
Buttons which are frequently used such as register initializing button “Write Default”, are located outside of the switching
tab window. Refer to the “■ Dialog Boxes” for details of each dialog box setting.
1. [Port Reset]: For when connecting to USB I/F board (AKDUSBIF-A)
Click this button after the control soft starts up when connecting USB I/F board (AKDUSBIF-A).
2. [Write Default]: Register Initializing
When the device is reset by a hardware reset, use this button to initialize the registers.
3. [All Write]: Executing write commands for all registers displayed.
4. [Save]: Saving current register settings to a file.
5. [Load]: Executing data write from a saved file.
6. [Data R/W]: “Data R/W” dialog box is popped up.
■ Tab Functions
[Data R/W]
Click the [Data R/W] button in the main window for data read/write dialog box.
Data write is available to specified address.
Figure 6. Window of [ Data R/W ]
Address Box : Input data address in hexadecimal numbers for data writing.
Data Box
Mask Box
: Input data in hexadecimal numbers.
: Input mask data in hexadecimal numbers.
This is “AND” processed input data.
[Write] : Writing to the address specified by “Address” box.
[Close] : Closing the dialog box and finish the process.
Data writing can be cancelled by this button instead of [Write] button.
*The register map will be updated after executing [Write] or [Read] commands.
<KM100802>
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[AKD4621-B]
[REG]: Register Map
This tab is for a register writing and reading.
Each bit on the register map is a push-button switch.
Button Down indicates “H” or “1” and the bit name is in red (when read only it is in deep red).
Button Up indicates “L” or “0” and the bit name is in blue (when read only it is in gray)
Grayout registers are Read Only registers. They can not be controlled.
The registers which is not defined in the datasheet are indicated as “---”.
Figure 7. Window of [ REG]
<KM100802>
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[AKD4621-B]
[Write]: Data Writing Dialog
It is for when changing two or more bits on the same address at the same time.
Click [Write] button located on the right of the each corresponded address for a pop-up dialog box.
When checking the checkbox, the register will be “H” or “1”, when not checking the register will be “L” or ”0”.
Click [OK] to write setting value to the registers, or click [Cancel] to cancel this setting.
Figure 8. Window of [ Register Set ]
<KM100802>
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[AKD4621-B]
[Tool]: Testing Tools
This tab screen is for evaluation testing tool.
Click buttons for each testing tool.
Figure 9. Window of [ Tool]
<KM100802>
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[AKD4621-B]
[Repeat Test]: Repeat Test Dialog
Click [Repeat Test] button to open repeat test setting dialog box.
Figure 10. Window of [ Repeat Test]
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[AKD4621-B]
[Loop Setting]: Loop Setting Dialog
Click [Loop Setting] button to open loop setting dialog box.
Figure 11. Window of [ Loop]
<KM100802>
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[AKD4621-B]
Measurement Results
[Measurement condition]
• Measurement unit
• MCLK
: Audio Precision System two Cascade (AP2)
: 512fs (fs = 48kHz), 256fs (fs = 96kHz), 128fs (fs = 192kHz)
• BICK
• fs
• Bit
: 64fs
: 48kHz, 96kHz, 192kHz
: 24bit
• Power Supply
• Interface
• Temperature
: AVDD=5V, DVDD=TVDD=3.3V
: DIT or DIR
: Room
1. ADC (Differencial)
fs=48kHz
Results
Parameter
Input signal
Measurement filter
L ch
R ch
S/(N+D)
S/(N+D)
DR
1kHz, -1dB
20kHzLPF
20kHzLPF
104.0
53.7
104.0
53.8
1kHz, -60dB
1kHz, -60dB 20kHzLPF, A-weighted
116.1
116.1
116.1
116.1
S/N
“0” data
20kHzLPF, A-weighted
fs=96kHz
Parameter
Results
Input signal
Measurement filter
L ch
R ch
S/(N+D)
S(N+D)
DR
1kHz, -1dB
40kHzLPF
40kHzLPF
102.8
49.5
102.8
49.6
1kHz, -60dB
1kHz, -60dB 40kHzLPF, A-weighted
115.1
115.2
115.2
115.4
S/N
“0” data
40kHzLPF, A-weighted
fs=192kHz
Parameter
Results
Input signal
Measurement filter
L ch
R ch
S/(N+D)
S(N+D)
DR
1kHz, -1dB
40kHzLPF
40kHzLPF
102.7
49.9
102.8
50.1
1kHz, -60dB
1kHz, -60dB 40kHzLPF, A-weighted
“0” data 40kHzLPF, A-weighted
115.3
115.5
115.6
115.6
S/N
<KM100802>
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[AKD4621-B]
2. DAC
fs=48kHz
Results
Results
Results
Parameter
Input signal
Measurement filter
L ch
R ch
S/(N+D)
S/(N+D)
DR
1kHz, -1dB
20kHzLPF
20kHzLPF
99.8
52.7
100.2
52.7
1kHz, -60dB
1kHz, -60dB 22kHzLPF, A-weighted
114.8
115.0
114.8
114.9
S/N
“0” data
22kHzLPF, A-weighted
fs=96kHz
Parameter
Input signal
Measurement filter
L ch
R ch
S/(N+D)
S/(N+D)
DR
1kHz, -1dB
40kLPF
40kLPF
99.2
50.0
99.4
50.0
1kHz, -60dB
1kHz, -60dB 40kHzLPF, A-weighted
114.9
115.0
114.9
115.0
S/N
“0” data
40kHzLPF, A-weighted
fs=192kHz
Parameter
Input signal
Measurement filter
L ch
R ch
S/(N+D)
S/(N+D)
DR
1kHz, -1dB
40kHzLPF
40kHzLPF
99.2
49.7
99.4
49.8
1kHz, -60dB
1kHz, -60dB 40kHzLPF, A-weighted
“0” data 40kHzLPF, A-weighted
114.8
115.1
114.7
115.1
S/N
<KM100802>
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[AKD4621-B]
3. PLOT DATA
3.1 ADC (fs=48kHz)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
-90
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 12. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
-90
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 13. FFT (fin=1kHz, Input Level=-60dBFS)
- 23 -
<KM100802>
2010/12
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 14. FFT (Noise Floor)
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
d
B
F
S
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-140
-120
-100
-80
-60
-40
-20
dBr
Figure 15. THD+N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 24 -
[AKD4621-B]
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
d
B
F
S
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 16. THD +N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 17. Linearity (fin=1kHz)
<KM100802>
2010/12
- 25 -
[AKD4621-B]
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
d
B
F
S
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 18. Frequency Response(Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
d
B
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 19. Crosstalk
<KM100802>
2010/12
- 26 -
[AKD4621-B]
3.2 ADC (fs=96kHz)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
-90
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 20. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 21. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 27 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 22. FFT (Noise Floor)
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
d
B
F
S
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-140
-120
-100
-80
-60
-40
-20
dBr
Figure 23. THD +N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 28 -
[AKD4621-B]
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
d
B
F
S
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 24. THD +N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 25. Linearity (fin=1kHz)
<KM100802>
2010/12
- 29 -
[AKD4621-B]
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
d
B
F
S
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 26. Frequency Response(Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
d
B
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 27. Crosstalk
<KM100802>
2010/12
- 30 -
[AKD4621-B]
3.3 ADC (fs=192kHz)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
-90
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 28. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
-90
F
S
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 29. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 31 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
F
S
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 30. FFT (Noise Floor)
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
d
B
F
S
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-140
-120
-100
-80
-60
-40
-20
dBr
Figure 31. THD+N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 32 -
[AKD4621-B]
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
d
B
F
S
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 32. THD+N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
F
S
-70
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 33. Linearity (fin=1kHz)
<KM100802>
2010/12
- 33 -
[AKD4621-B]
+0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
d
B
F
S
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 34. Frequency Response(Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
d
B
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 35. Crosstalk
<KM100802>
2010/12
- 34 -
[AKD4621-B]
3.4 DAC (fs=48kHz)
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
d
B
r
-100
-110
-120
-130
-140
-150
-160
-170
A
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 36. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
r
-90
-100
-110
-120
-130
-140
-150
-160
-170
A
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 37. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 35 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
r
-90
-100
-110
-120
-130
-140
-150
-160
-170
A
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 38. FFT (Noise Floor)
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
-87.5
-90
-92.5
-95
A
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 39. THD+N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 36 -
[AKD4621-B]
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
-87.5
-90
-92.5
-95
A
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 40. THD +N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
A
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 41. Linearity (fin=1kHz)
<KM100802>
2010/12
- 37 -
[AKD4621-B]
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
d
B
r
A
-2.2
-2.4
-2.6
-2.8
-3
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 42. Frequency Response (Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
d
B
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 43. Crosstalk
<KM100802>
2010/12
- 38 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
r
-90
-100
-110
-120
-130
-140
-150
-160
-170
A
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 44. Out-of-band Noise
<KM100802>
2010/12
- 39 -
[AKD4621-B]
3.5 DAC (fs=96kHz)
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
d
B
r
-100
-110
-120
-130
-140
-150
-160
-170
A
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 45. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
r
-90
-100
-110
-120
-130
-140
-150
-160
-170
A
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 46. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 40 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
r
-90
-100
-110
-120
-130
-140
-150
-160
-170
A
-180
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 47. FFT (Noise Floor)
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
-87.5
-90
-92.5
-95
A
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 48. THD +N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 41 -
[AKD4621-B]
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
-87.5
-90
-92.5
-95
A
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 49. THD +N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
A
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 50. Linearity (fin=1kHz)
<KM100802>
2010/12
- 42 -
[AKD4621-B]
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
d
B
r
A
-2.2
-2.4
-2.6
-2.8
-3
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 51. Frequency Response (Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
d
B
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
40 50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 52. Crosstalk
<KM100802>
2010/12
- 43 -
[AKD4621-B]
3.6 DAC (fs=192kHz)
+0
-10
-20
-30
-40
-50
-60
-70
-80
-90
d
B
r
-100
-110
-120
-130
-140
-150
-160
-170
A
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 53. FFT (fin=1kHz, Input Level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
r
-90
-100
-110
-120
-130
-140
-150
-160
-170
A
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 54. FFT (fin=1kHz, Input Level=-60dBFS)
<KM100802>
2010/12
- 44 -
[AKD4621-B]
+0
-10
-20
-30
-40
-50
-60
-70
-80
d
B
r
-90
-100
-110
-120
-130
-140
-150
-160
-170
A
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 55. FFT (Noise Floor)
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
-87.5
-90
-92.5
-95
A
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 56. THD+N vs. Input level (fin=1kHz)
<KM100802>
2010/12
- 45 -
[AKD4621-B]
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
-82.5
-85
d
B
r
-87.5
-90
-92.5
-95
A
-97.5
-100
-102.5
-105
-107.5
-110
-112.5
-115
-117.5
-120
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 57. THD+N vs. Input Frequency (Input level=-1dBFS)
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
A
-80
-90
-100
-110
-120
-130
-140
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 58. Linearity (fin=1kHz)
<KM100802>
2010/12
- 46 -
[AKD4621-B]
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
d
B
r
A
-2.2
-2.4
-2.6
-2.8
-3
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 59. Frequency Response (Input level=-1dBFS)
-80
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
-102.5
-105
-107.5
-110
d
B
-112.5
-115
-117.5
-120
-122.5
-125
-127.5
-130
-132.5
-135
-137.5
-140
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 60. Crosstalk
<KM100802>
2010/12
- 47 -
[AKD4621-B]
REVISION HISTORY
Date
Manual
Board
Reason
Page
Contents
(yy/mm/dd)
Revision
Revision
2010/03/12 KM100800
2010/03/12 KM100801
0
1
First Edition
Evaluation Board
Change
Device Rev. Change
AK4621: Rev.A → Rev.B
2010/12/07 KM100802
2
Modification
21~47 Device revision was changed.:
Rev.BÆRev.C
Update of measurement results and Plots.
Modification
49
Circuit diagram was changed.
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
Microdevices Corporation (AKM) or authorized distributors as to current status of the products.
z AKM assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use
of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKM products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKM assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKM. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places
the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer
or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
<KM100802>
2010/12
- 48 -
5
4
3
2
1
T1
AVDD
C14
VREF
T2
LP2950A
NJM78M05FA
R77
R501
10
(short)
1
3
3
1
VOP+
VOP+
IN
OUT
IN
OUT
VREF
CODEC_3.3V
+
+
C3
C6
+
C12
C13
C15
+
C1
0.1u
C2
0.1u
C4
0.1u
C5
0.1u
10u
470u
0.1u
0.1u
47u
47u
AVDD
Bias
AGND
AGND
D
C
B
A
D
C
B
A
T3
TA48M33F
R500
10
for 74HC14/74LVC157
IN
OUT
+3.3V
+
C7
0.1u
C8
0.1u
C9
C10
C11
(short)
L5
PORT1
VCC
47u
0.1u
0.1u
4114_AVDD
3
1
2
+3.3V
4114_AVDD
C16
C17
2
1
+
GND
OUT
C18
10u
R1
0.1u
10u
TORX141
OPT
BNC
C19
0.1u
470
JP2
RX3
R2
J1
18k
C22
C23
C20
10u
C21
0.1u
BNC_RX
+
+
0.47u
U1
R3
75
0.1u
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
30
RX
VCOM
AINR+
AINR-/NC
AINL+
AINL-/NC
VREF
AOUTR+
AOUTR-
AOUTL+
AOUTL-
VSS2
DVDD
TVDD
SDFIL
DEM0
PDN
DFS0
AOUTR+
AOUTR-
AOUTL+
AOUTL-
29
28
27
26
25
24
23
22
21
20
19
18
17
16
AINR+
AINL+
VREF
AINR-
AINL-
INT1
+
C24
C25
AGND
VSS1
AVDD
AK4621
1
2
3
4
5
6
7
8
9
36
10u
0.1u
CODEC_3.3V
+3.3V
AVDD
P/S
IPS0/RX4
AVSS
DIF0/RX5
TEST2
DIF1/RX6
AVSS
DIF2/RX7
IPS1/IIC
P/SN
INT0
OCKS0/CSN
OCKS1/CCLK
CM1/CDTI
CM0/CDTO
PDN
SDFIL
DEM0
C26
R4
AGND
R6
35
34
33
32
31
30
29
28
27
26
25
OCKS0
OCKS1
CM1
CM0
PDN
P/S
MCLK
LRCK/DSDR
BICK/DCLK
SDTO
SDTI/DSDL
OVFR/DZFR
R5
51
5p
DIF0/RX5
PDN
DFS0
XTI
XTO
U2
AK4114
51
CSN/DIF
CCLK/CKS1
CDTI/CKS0
OVFL/DZFL
CSN/DIF
CCLK/CKS1
CDTI/CKS0
X1
C27
R7
51
XTI
XTO
XTI
XTO
DAUX
MCKO2
BICK
5p
24.576MHz
10
11
12
XTL0
XTL1
XTL0
XTL1
VIN
51
SDTO
DIF2-0="100"; MSB justified; Master Mode
OVFL/DZFL
PORT2
IN
R8
51
C130
C131 C132 C133
OVFR/DZFR
3
2
+3.3V
SW1
(open)
10p (open)(open)
VCC
+3.3V
1
2
3
4
5
6
7
14
13
12
11
10
9
1
GND
C28
0.1u
+3.3V
TOTX141
C29
10u
AK4114 Mode_setting
+
+3.3V
SW3
JP7
C31
TEST1
1
2
3
4
5
6
7
14
13
12
11
10
9
OPT
BNC
C30
0.1u
0.1u
8
C32
10u
AK4621 Mode_setting
J6
R78
5.1
T4
DA02
TX
R183
240
BNC_TX
8
RP2
RP1
7
6
5
4
3
2
1
XTL1
XTL0
TX
XTL1
XTL0
R184
150
7
6
5
4
3
2
1
P/S
P/S
DIF0/RX5
OCKS1
OCKS0
CM1
SDFIL
DEM0
DFS0
DIF
DIF0/RX5
OCKS1
OCKS0
CM1
SDFIL
DEM0
DFS0
DIF
1:1
CM0
CKS1
CKS0
CM0
CKS1
CKS0
+3.3V
+3.3V
47K
47K
R11
10k
R12
10k
R13
10k
D1
R10
10k
R14
PORT3
1S1588
U3A
U3B
1
2
3
4
5
10 CSN
U4
1
2
3
4
9
8
7
6
CCLK
CDTI
PDN
470
2
3
5
4
1A
1B
2A
2B
3A
3B
4A
4B
1Y
CSN/DIF
C33
0.1u
74HC14_0
74HC14_0
DIF
H
L
R16
470
R15
470
7
2Y
3Y
4Y
CCLK/CKS1
CDTI/CKS0
SW2
6
CKS1
CKS0
CR-I/F
11
10
14
13
9
PDN
12
1
15
A/B
G
P/S
Title
74LVC157
- 49 -
AKD4621-B
Size
A3
Document Number
Rev
1
AK4621
Date:
Monday, December 06, 2010
Sheet
1
of
2
1
5
4
3
2
5
4
3
2
1
C34
J2
SINGLE
DIFF
JP3
LIN
LIN
R19
4.7k
(open)
R18
910
R17
47k
VOP_ADC-
VOP_ADC-
C35
C36 (open)
C37
3.3n
NJM5534D
470p
+
C38
0.1u
C39
10u
R20
C40
47u
R21
3k
R22
22
R101
0
C41
100u
R23
330
R24
180
4.7k
SINGLE
DIFF
JP4
AINL
U6
-
2
3
D
C
B
A
D
C
B
A
+
C42
0.1u
C43
10u
-
1
2
3
3
2
AOUTL+
+
AINL+
+
1
6
U8A
NJM5532
C44
100p
+
-
U5A
NJM5532
R25
10k
R26
560
C45
3.9n
VOP_ADC+
VOP_ADC+
R28
910
C47
10u
C48
1n
+
C49
10n
C46
0.1u
R27
680
R29
620
R30
(short)
VOP_ADC-
C50
C51
100p
R31
1.2k
C55
(short)
C54
(open)
R32
100
J3
LOUT
-
+
C52
100p
C53
(open)
R34
(short)
2
3
470p
6
C57
3.3n
C58
47u
R38
3k
R33
620
R36
(open)
C56
(open)
NJM5534D
Bias
R37
10k
R40
22
U7
+
C59
0.1u
C60
10u
R39
560
C61
1n
-
+
6
5
NJM5534D
7
AINL-
R102
0
C62
100u
R41
330
R42
180
U5B
NJM5532
U9
3
AOUTL-
+
-
6
C63
100p
2
VOP_ADC+
+
C64
0.1u
C65
10u
R43
10k
R44
10k
+
C66
3.9n
C67
0.1u
C68
10u
C70
10u
+
C69
0.1u
R45
680
C71
100p
R46
1.2k
C73
J4
RIN
C72
100p
VOP_DAC+
VOP_DAC-
SINGLE
DIFF
JP5
RIN
(open)
R48
910
R47
47k
R49
4.7k
C74
3.3n
VOP_ADC-
NJM5534D
VOP_ADC-
C75
+
C77 (open)
C76
10u
C78
0.1u
R103
0
C79
100u
R50
330
R51
180
470p
U11
+
C80
0.1u
C81
10u
3
AOUTR+
+
-
R52
4.7k
6
C83
R53
47u 3k
R54
22
C82
100p
2
SINGLE
DIFF
JP6
AINR
-
6
5
R55
10k
R56
560
-
+
7
2
3
AINR+
C84
3.9n
+
1
U10B
NJM5532
U12A
C86
10u
C87
1n
NJM5532
+
C85
0.1u
VOP_ADC+
R57
680
R58
620
R59
(short)
VOP_ADC+
R61
910
C88
100p
R60
1.2k
C93
(short)
C90
10n
C92
(open)
R62
100
J5
ROUT
VOP_ADC-
-
C89
100p
C91
(open)
R64
(short)
2
3
C94
6
+
C96
3.3n
R63
620
R65
(open)
C95
(open)
NJM5534D
470p
U13
+
C97
0.1u
C98
10u
R66
560
C99
1n
NJM5534D
C100
47u
R69
3k
R104
0
C101
100u
R70
330
R71
180
Bias
R68
10k
R72
22
U14
-
+
6
5
3
AOUTR-
+
-
7
6
AINR-
C102
100p
2
U12B
NJM5532
R73
10k
+
C103
3.9n
C104
0.1u
C105
10u
VOP_ADC+
+
C106
0.1u
C107
10u
R74
10k
C109
10u
+
C108
0.1u
R75
680
C110
100p
R76
1.2k
for NJM5532
C111
100p
VOP_ADC-
+
+
+
+
VOP_ADC-
VOP_ADC-
C113
10u
C114
0.1u
C115
10u
C116
0.1u
C117
10u
C118
0.1u
C119
10u
C120
0.1u
-
-
6
5
2
7
1
+
+
3
U8B
NJM5532
U10A
NJM5532
for NJM5532
VOP_ADC+
VOP_ADC+
VOP_ADC+
+
+
+
+
C122
10u
C123
0.1u
C124
10u
C125
0.1u
C126
10u
C127
0.1u
C128
10u
C129
0.1u
R503
R505
VOP_ADC-
VOP_DAC-
VOP_ADC+
10
10
R502
R504
-15V
VOP_DAC+
VOP+
+15V
L6
10
10
L7
1
2
1
2
(short)
+
C112
47u
(short)
+
C121
47u
Title
- 50 -
AKD4621-B
Size
A2
Document Number
Rev
Analog_I/O
1
Date:
Monday, December 06, 2010
Sheet
of
2
2
5
4
3
2
1
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