AKD4665A-A [AKM]
20bit CODEC with built-in Input PGA and Headphone Amplifier; 20位编解码器内置PGA的输入和耳机放大器
| 型号： | AKD4665A-A |
| 厂家： | 
ASAHI KASEI MICROSYSTEMS |
| 描述： | 20bit CODEC with built-in Input PGA and Headphone Amplifier |
| 文件： | 总39页 (文件大小：875K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ASAHI KASEI
[AKD4665A-A]
AKD4665A-A
AK4665A Evaluation board Rev.1
GENERAL DESCRIPTION
AKD4665A-A is an evaluation board for the AK4665A, 20bit CODEC with built-in Input PGA and
Headphone Amplifier. The AKD4665A-A can evaluate A/D converter and D/A converter separately in
addition to loopback mode (A/D → D/A). AKD4665A-A also has the digital audio interface and can
achieve the interface with digital audio systems via opt-connector.
Ordering guide
AKD4665A-A
---Evaluation board for AK4665A
(Cable for connecting with printer port of IBM-AT, compatible PC and control
software are packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT/DIR with optical input/output
• RCA connector for an external clock input
• 10pin Header for serial control mode
HVDD AVDD DVDD TVDDLVC_IN GND
5V
3V
Regulator
up-I/F
MIC-Jack
AINL1/
MICIN
10pin Header
AINR1
DSP
LIN/RIN/MIN
AK4665A
10pin Header
LOUT
ROUT
HPL
AK4114
HPR
HP-Jack
Opt In
Opt Out
Figure 1. AKD4665A-A Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual.
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ASAHI KASEI
[AKD4665A-A]
Evaluation Board Manual
Operation sequence
1) Set up the power supply lines.
1-1) When AVDD, DVDD, HVDD, TVDD and LVC are supplied from the regulator. (AVDD, DVDD, HVDD,
TVDD and LVC_IN jack should be open.). See “Other jumper pins set up (page 5)”. <default>
[REG]
(red )
= 5V
[HVDD] (orange)
[AVDD] (orange)
[DVDD] (orange)
[TVDD] (blue)
[LVC_IN] (blue)
[VD_IN] (orenge)
[AGND] (black)
[DGND] (black)
= open
= open
= open
= open
= open
: 3V is supplied to HVDD of AK4665A from regulator.
: 3V is supplied to AVDD of AK4665A from regulator.
: 3V is supplied to DVDD of AK4665A from regulator.
: 3V is supplied to TVDD of AK4665A from regulator.
: 3V is supplied to logic block of LVC from regulator.
= 2.7 ∼ 3.6V : for other logic (typ. 3V)
= 0V
= 0V
: for analog ground
: for logic ground
1-2) When AVDD, DVDD, HVDD, TVDD and LVC are not supplied from the regulator. (AVDD, DVDD,
HVDD, TVDD and LVC jack should be junction.) See “Other jumper pins set up (page 5)”.
[REG]
(red)
= “REG” jack and JP2 should be open.
[HVDD] (orange)
[AVDD] (orange)
[DVDD] (orange)
[TVDD] (blue)
[LVC_IN] (blue)
[VD_IN] (orenge)
[AGND] (black)
[DGND] (black)
= 2.6 ∼ 3.6V : for HVDD of AK4665A (typ. 3V)
= 2.6 ∼ 3.6V : for AVDD of AK4665A (typ. 3V)
= 2.6 ∼ 3.6V : for DVDD of AK4665A (typ. 3V)
= 1.6 ∼ 3.6V : for TVDD of AK4665A (typ. 3V)
= 1.65 ∼ 5.5V: for logic block of LVC (typ. 3V)
= 2.7 ∼ 3.6V : for other logic (typ. 3V)
= 0V
= 0V
: for analog ground
: for logic ground
Each supply line should be distributed from the power supply unit.
AVDD and DVDD each must be same voltage level, and TVDD and LVC_IN each too.
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4665A and AK4114 should be reset once bringing SW1, 2 “L” upon power-up.
Evaluation mode
In case of AK4665A evaluation using AK4114, same audio interface format should be set for both AK4665A
and AK4114. About AK4665A’s audio interface format, refer to datasheet of AK4665A. About AK4114’s
audio interface format, refer to Table 2 in this manual.
Applicable Evaluation Mode
(1) Evaluation of loop-back mode (Default)
(2) Evaluation of using DIR of AK4114 (opt-connector)
(3) Evaluation of using DIT of AK4114 (opt-connector)
(4) All interface signals including master clock are fed externally.
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
(1) Evaluation of loop-back mode (Default)
Nothing should be connected to PORT3. PORT1(TORX141), or X’tal mode of the AK4114 is used.
When an external clock through an RCA connector (J10: MCLK) is supplied, short JP12 (XTI). JP13 (EXT) and
R28 should be properly selected in order to much the output impedance of the clock generator. Then X’tal(X1)
and capacitance (C35,C36) should be removed.
JP12
XTI
JP19
JP14
JP15
JP16
JP18
SDTI
JP17
DIR_MCLK DIR_BICK
BICK_INV
DIR_LRCK
SDTO
THR
INV
ADC
DIR
(2) Evaluation of using DIR of AK4114 (opt-connector)
PORT1(TORX141), is used. DIR generates MCLK, BICK, LRCK and SDTI from the received data through
optical connector (TORX141). Used for the evaluation using CD test disk. Nothing should be connected to
PORT3.
JP12
XTI
JP19
JP14
JP15
JP16
JP18
SDTI
JP17
DIR_MCLK DIR_BICK
BICK_INV
DIR_LRCK
SDTO
THR
INV
ADC
DIR
(3) Evaluation of using DIT of AK4114 (opt-connector)
PORT1(TORX141) and PORT2(TOTX141), or X’tal mode of the AK4114 and PORT2(TOTX141) is used.
DIT generates audio bi-phase signal from received data and which is output through optical connector
(TOTX141). It is possible to connect AKM’s D/A converter evaluation boards on the digital-amplifier which
equips DIR input.
Nothing should be connected to PORT3.
When an external clock through a RCA connector (J10: MCLK) is supplied, short JP12 (XTI). JP13 (EXT) and
R28 should be properly selected in order to much the output impedance of the clock generator. Then X’tal(X1)
and capacitance (C35,C36) should be removed.
JP12
XTI
JP19
JP14
JP15
JP16
JP18
SDTI
JP17
DIR_MCLK DIR_BICK
BICK_INV
DIR_LRCK
SDTO
THR
(4) All interface signals including master clock are fed externally.
When all interface signals through PORT3 are supplied, the jumper pins should be set to the following.
INV
ADC
DIR
JP12
XTI
JP19
JP14
JP15
JP16
JP18
SDTI
JP17
DIR_MCLK DIR_BICK
BICK_INV
DIR_LRCK
SDTO
THR
INV
ADC
DIR
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
DIP Switch set up
[SW2] (MODE) : Mode Setting of AK4114
ON is “H”, OFF is “L”.
No.
1
2
Name
DIF0
DIF1
DIF2
Default
OFF
OFF
ON (“H”)
OFF (“L”)
AK4114 Audio Format Setting
See Table 2
3
ON
Clock Operation Mode select
See Table 3
Master Clock Frequency Select
See Table 4
4
5
CM0
OFF
OFF
OCKS1
Table 1. Mode Setting for AK4114
Register setting
Setting for AK4114 Audio Interface Format
for AK4665A Audio Interface
Format
Mode
DIF2 DIF1 DIF0
DAUX
SDTO
DIF1
DIF0
0
2
4
5
0
0
1
1
0
1
0
0
0
0
0
1
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
16bit, Right justified
20bit, Right justified
24bit, Left justified
24bit, I2S
0
0
1
1
0
1
0
1
Default
Table 2. Setting for AK4114 Audio Interface Format
SW2-#4 (CM0)
Clock Mode
PLL Mode
X’tal Mode
Clock source
PORT1 (TORX141)
X1 (X'tal) or J10 (RCA)
SDTO
RX (Optical)
DAUX (ADC)
OFF
ON
Default
Table 3. Clock Operation Mode select
SW2-#5 (OCKS1)
PLL Mode
256fs
X’tal Mode
256fs
512fs
Default
OFF
ON
512fs
Table 4. Master Clock Frequency Select
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
Other jumper pins set up
1. JP1 (GND)
OPEN
: Analog ground and Digital ground
: Separated.
SHORT
: Common. (The connector “DGND” can be open.) <Default>
2. JP3 (REG)
OPEN
: HVDD of the AK4665A
: HVDD is supplied from “HVDD ” jack.
SHORT
: HVDD is supplied from the regulator (“HVDD” jack should be open). < Default >
3. JP3 (AVDD_SEL) : AVDD of the AK4665A
OPEN
SHORT
: AVDD is supplied from “AVDD ” jack.
: AVDD is supplied from “HVDD” (“AVDD” jack should be open). < Default >
4. JP4 (DVDD_SEL) : DVDD of the AK4665A
OPEN
SHORT
: DVDD is supplied from “DVDD ” jack. < Default >
: DVDD is supplied from “HVDD” (“DVDD” jack should be open).
5. JP6 (TVDD_SEL), JP7 (LVC_SEL):
Logic block of LVC is
supplied from
JP6
JP7
TVDD is supplied from
“TVDD” jack
“TVDD” jack
“TVDD” jack
“DVDD”
Note
-
OPEN OPEN
OPEN TVDD
“LVC_IN” jack
“TVDD” jack
“VD_IN” jack
“LVC_IN” jack
“TVDD”
“LVC_IN” jack should be
open.
“LVC_IN” jack should be
open.
OPEN
VD
SHORT OPEN
SHORT TVDD
“TVDD” jack should be open.
“TVDD” and “LVC_IN” jack
should be open.
“DVDD”
<Default>
TVDD” and “LVC_IN” jack
should be open.
SHORT
VD
“DVDD”
“VD” jack
Table 5. JP6 (TVDD_SEL), JP7 (LVC_SEL) select
6. JP5 (MPWR) : Connection between MPWR pin and MICIN pin of the AK4665A
OPEN
: MPWR is not connected to MICIN.
SHORT
: MPWR is connected to MICIN. < Default >
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
The function of the toggle SW
[SW1] (DIR) : Power control of AK4114. Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
[SW3] (PDN) : Power control of AK4665A. Keep “H” during normal operation.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
Serial Control
The AK4665A can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4
(CTRL) with PC by 10 wire flat cable packed with the AKD4665A-A
CSN
SCL/CCLK
Connect
SDA/CDTI
SDA/(ACK)
PC
10 wire
flat cable
10pin
Connector
10pin Header
AKD4665A-A
Figure 2. Connect of 10 wire flat cable
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
Analog Input / Output Circuits
(1) Input Circuits
a) MIC/AINL1/AINR1 Input Circuit
J1
MIC-JACK
6
4
3
JP8
MIC_SEL
JACK
RCA
INT
J3
C25
AINL1/MICIN
1u
2
2
1
AINL1
3
1
R16
(open)
MR-552LS
J5
AINR1
C26
1u
2
2
1
AINR1
3
1
R17
(open)
MR-552LS
Figure 3. MIC/AINL1/AINR1 Input Circuit
(a-1) Analog signal is input to MICIN pin via J1 (MIC-JACK) connector.
JP8
MIC_SEL
RCA JACK
(a-2) Analog signal is input to MICIN pin via J3 (AINL1/MICIN) connector.
JP12
MIC_SEL
RCA JACK
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
b) LIN/RIN/MIN Input Circuit
J8
LIN/RIN/MIN
JP10
2
LIN
RIN
MIN
LIN
RIN
MIN
3
1
C27
0.047u
R21
(open)
LIN/RIN/MIN
MR-552LS
Figure 4. LIN/RIN/MIN Input Circuit
(2) Output Circuits
a) LOUT/ROUT Output Circuit
C23
R12
220
J2
LOUT
1
2
2
3
1
LOUT
4.7u
R13
10k
MR-552LS
C24
R14
220
J4
ROUT
1
2
2
3
1
ROUT
4.7u
R15
10k
MR-552LS
Figure 5. LOUT/ROUT Output Circuit
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
b) HPL/HPR Output Circuit
J6
HPL
2
3
1
R18
16
MR-552LS
R19
(short)
JP9
HPL
HPL
HPR
J7
HP
6
R20
(short)
4
3
JP11
HPR
J9
HPR
2
3
1
R22
16
MR-552LS
Figure 6. HPL/HPR Output Circuit
(b-1) HPL and HPR pins are outputted from J7 (mini jack).
JP9
JP11
HPR
HPL
(b-2) HPL and HPR pins are outputted from J6 and J9.
JP9
JP11
HPR
HPL
∗ AKM assumes no responsibility for the trouble when using the above circuit examples.
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
2. Control Software Manual
Set-up of evaluation board and control software
1. Set up the AKD4665A-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4665A-A by 10-line type flat cable (packed with AKD4665A-A). Take
care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AKD4665A-A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd4665a-a.exe” to set up the control program.
5. Then please evaluate according to the follows.
Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
3. Click “Write default” button
Explanation of each buttons
1. [Port Reset] :
2. [Write default] :
3. [All Write] :
4. [Function1] :
5. [Function2] :
6. [Function3] :
7. [Function4] :
8. [Function5]:
Set up the USB interface board (AKDUSBIF-A) when using the board.
Initialize the register of the AK4665A.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
9. [SAVE] :
10. [OPEN] :
11. [Write] :
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to the AK4665A, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Input registers address in 2 figures of hexadecimal.
Data Box:
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to the AK4665A, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DATT
There are dialogs corresponding to register of 05h, 0Ah, 0Bh and 0Ch.
Address Box:
Start Data Box:
End Data Box:
Interval Box:
Step Box:
Input registers address in 2 figures of hexadecimal.
Input starts data in 2 figures of hexadecimal.
Input end data in 2 figures of hexadecimal.
Data is written to the AK4665A by this interval.
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to the AK4665A, click [OK] button. If not, click [Cancel] button.
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
4. [SAVE] and [OPEN]
4-1. [SAVE]
All of current register setting values displayed on the main window are saved to the file. The extension of file name is
“akr”.
<Operation flow>
(1) Click [SAVE] Button.
(2) Set the file name and click [SAVE] Button. The extension of file name is “akr”.
4-2. [OPEN]
The register setting values saved by [SAVE] are written to the AK4665A. The file type is the same as [SAVE].
<Operation flow>
(1) Click [OPEN] Button.
(2) Select the file (*.akr) and Click [OPEN] Button.
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [START] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file
name is “aks”.
Figure 7. Window of [F3]
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed.
When [F4] button is clicked, the window as shown in Figure 8 opens.
Figure 8. [F4] window
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3].
The sequence file name is displayed as shown in Figure 9. ( In case that the selected sequence file name is
“DAC_Stereo_ON.aks”)
Figure 9. [F4] window(2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name
is “*.ak4”.
[OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the
change.
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to
buttons and then executed. When [F5] button is clicked, the window as shown in Figure 10 opens.
Figure 10. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure 11. (In case that the selected file name is
“DAC_Output.akr”)
(2) Click [WRITE] button, then the register setting is executed.
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
Figure 11. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file
name is “*.ak5”.
[OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note
(1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder.
(2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be
loaded again in order to reflect the change.
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
MEASUREMENT RESULTS
[Measurement condition]
• Measurement unit : Audio Precession System Two Cascade
• MCLK
• BICK
• fs
: 11.2896MHz
: 64fs
: 44.1kHz
• Bit
: 20bit
• Power Supply
: AVDD = DVDD = HVDD = TVDD = 3.0V
• Measurement Filter : 10Hz ∼ 20kHz
• Temperature : Room
Parameter
MIC-Amp: (MICIN pin Æ ADC)
Result (Lch / Rch)
Unit
THD+N
D-Range
S/N
(-1dBFS Output)
(-60dB Output, A-weighted)
(A-weighted)
-90.6 / -90.4
93.4 / 93.4
93.4 / 93.4
dB
dB
dB
Parameter
Result (Lch / Rch)
Unit
Analog Input Characteristics: (AINL1/AINR1 pins Æ ADC Æ IVOL),
IVOL=0dB, ALC1= OFF
THD+N
D-Range
S/N
(-1dBFS Output)
(-60dB Output, A-weighted)
(A-weighted)
-91.6 / -91.2
94.5 / 94.5
94.6 / 94.6
dB
dB
dB
Parameter
Result (Lch / Rch)
Unit
Headphone-Amp: (DAC Æ HPL/HPR pins),
RL=16Ω, HPG bit = “0”, ATTL7-0=ATTR7-0 bits=0dB
THD+N
D-Range
S/N
(0dBFS Output)
(-60dB Output, A-weighted)
(A-weighted)
-58.7 / -58.7
88.4 / 88.2
88.5 / 88.2
dB
dB
dB
Parameter
Result (Lch / Rch)
Unit
Stereo Line Output: (DAC Æ LOUT/ROUT pins),
ATTL7-0 = ATTR7-0 = ATTS3-0 bits = 0dB
THD+N
D-Range
S/N
(0dBFS Output)
(-60dB Output, A-weighted)
(A-weighted)
-84.5 / -84.1
88.7 / 88.4
88.8 / 88.5
dB
dB
dB
<KM082201>
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ASAHI KASEI
[AKD4665A-A]
PLOT DATA
1.ADC (AINL1/AINR1 Æ ADC) PLOT DATA
AKM
AKD4665 ADC(mic) THD+N vs.Input Level (fs=44.1kHz, fin=1kHz)
-60
-62
-64
-66
-68
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
-90
-92
-94
-96
-98
d
B
F
S
-100
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
dBr
Figure 12. THD+N vs. Input Level
AK4665 ADC(AIN) THD+N vs. Input Frequency (fs=44.1kHz, Input=-1dB)
AKM
-60
-62.5
-65
-67.5
-70
-72.5
-75
-77.5
-80
d
B
F
S
-82.5
-85
-87.5
-90
-92.5
-95
-97.5
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 13. THD+N vs. Input Frequency (Input Level = -1dBFS)
<KM082201>
2006/05
- 19 -
ASAHI KASEI
[AKD4665A-A]
AKM
AK4665 ADC(AIN) Linearity (fs=44.1kHz, fin=1kHz)
+0
-10
-20
-30
-40
d
B
F
S
-50
-60
-70
-80
-90
-100
-110
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure 14. Linearity
AK4665 ADC(AIN) Frequency Response (fs=44.1kHz, Input=-1dB)
AKM
+0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
d
B
F
S
-2.2
-2.4
-2.6
-2.8
-3
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 15. Frequency Response
<KM082201>
2006/05
- 20 -
ASAHI KASEI
[AKD4665A-A]
AKM
AK4665 ADC(AINL1/AINR1) FFT (fs=44.1kHz, fin=1kHz, Input=-1dB)
FFT point=16384, Avg=8
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
-80
S
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 16. FFT Plot (Input level=-1dBFS)
AKM
AK4665 ADC(AINL1/AINR1) FFT (fs=44.1kHz, fin=1kHz, Input=-60dB)
FFT point=16384, Avg=8
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
-80
S
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 17. FFT Plot (Input level=-60dBFS)
<KM082201>
2006/05
- 21 -
ASAHI KASEI
[AKD4665A-A]
AKM
AK4665 ADC(AINL1/AINR1) FFT (fs=44.1kHz, Input=no signal)
FFT point=16384, Avg=8
+0
-10
-20
-30
-40
-50
-60
-70
d
B
F
-80
S
-90
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 18. FFT Plot (no signal input)
Figure 19. Crosstalk
<KM082201>
2006/05
- 22 -
ASAHI KASEI
[AKD4665A-A]
2. DAC (DAC Æ LOUT/ROUT) PLOT DATA
AKM
AK4665 DAC(LINEOUT) THD+N vs.Input Level (fs=44.1kHz, input=0dB)
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
d
B
r
A
-90
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 20. THD+N vs. Input Level
AK4665 DAC(LINEOUT) THD+N vs.Input Frequency(fs=44.1kHz, input=0dB)
AKM
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
d
B
r
A
-90
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 21. THD+N vs. Input Frequency (Input Level = 0dBFS)
<KM082201>
2006/05
- 23 -
ASAHI KASEI
[AKD4665A-A]
AKM
AK4665 DAC(LINEOUT) Linearity (fs=44.1kHz, input=0dB)
+0
-10
-20
-30
-40
d
B
-50
r
-60
A
-70
-80
-90
-100
-110
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 22. Linearity
AKD4665 DAC(LINEOUT) Frequency Response (fs=44.1kHz, Input=0dB)
AKM
+0.5
+0.4
+0.3
+0.2
+0.1
+0
-0.1
d
B
r
-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
A
-1
2k
4k
6k
8k
10k
Hz
12k
14k
16k
18k
20k
Figure 23. Frequency Response
<KM082201>
2006/05
- 24 -
ASAHI KASEI
[AKD4665A-A]
AKM
AK4665 DAC(LINEOUT) FFT (fs=44.1kHz, fin=1kHz, Input=0dB)
FFT point=16384, Avg=8
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 24. FFT Plot (Input level=0dBFS)
AKM
AK4665 DAC(LINEOUT) FFT (fs=44.1kHz, fin=1kHz, Input=-60dB)
FFT point=16384, Avg=8
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 25. FFT Plot (Input level=-60dBFS)
<KM082201>
2006/05
- 25 -
ASAHI KASEI
[AKD4665A-A]
AKM
AK4665 DAC(LINEOUT) FFT (fs=44.1kHz, Input=no data)
FFT point=16384, Avg=8
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 26. FFT Plot (no data input)
AKM
AK4665 DAC(LINEOUT) Out band noise (fs=44.1kHz, Input=no data)
FFT point = 16384, Avg = 8
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 27. Out band noise (no data input)
<KM082201>
2006/05
- 26 -
ASAHI KASEI
[AKD4665A-A]
Figure 28. Crosstalk
<KM082201>
2006/05
- 27 -
ASAHI KASEI
[AKD4665A-A]
3. DAC (DAC Æ HPL/HPR) PLOT DATA
AKM
AKD4665 DAC(HP) THD+N vs.Input Level (fs=44.1kHz, fin=1kHz)
-50
-52
-54
-56
-58
-60
-62
-64
-66
-68
-70
-72
-74
-76
-78
-80
-82
-84
-86
-88
d
B
r
A
-90
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 29. THD+N vs. Input Level
AK4665 DAC(HP) Input Frequency (fs=44.1kHz, Input=0dB)
AKM
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
d
B
r
A
-100
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 30. THD+N vs. Input Frequency (Input Level = 0dBFS)
<KM082201>
2006/05
- 28 -
ASAHI KASEI
[AKD4665A-A]
AKM
AK4665 DAC(HP) FFT (fs=44.1kHz, fin=1kHz, Input=0dB)
FFT point=16384, Avg=8
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 31. FFT Plot (Input level=0dBFS)
AKM
AK4665 DAC(HP) FFT (fs=44.1kHz, fin=1kHz, Input=0dB)
FFT point=16384, Avg=8
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 32. FFT Plot (Input level=-60.0dBFS)
<KM082201>
2006/05
- 29 -
ASAHI KASEI
[AKD4665A-A]
AKM
AK4665 DAC(HP) FFT (fs=44.1kHz, Input=no data)
FFT point=16384, Avg=8
+0
-10
-20
-30
-40
-50
-60
d
B
r
-70
-80
-90
A
-100
-110
-120
-130
-140
-150
-160
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 33. FFT Plot (no data input)
Figure 34. Crosstalk
<KM082201>
2006/05
- 30 -
ASAHI KASEI
[AKD4665A-A]
Revision History
Date
(YY/MM/DD)
05/12/19
Manual
Revision
KM082200
KM082201
Board
Revision
Reason
Contents
0
1
First Edition
Circuit
change
06/05/17
A 2Ω resistor was inserted at HVDD line in series.
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
<KM082201>
2006/05
- 31 -
A
B
C
D
E
T1
TA48M03F
REG
JP1
GND
REG1
HVDD1 AVDD1 DVDD1 TVDD1
AGND1
T45_BK
T45_R T45_O T45_O T45_O T45_B
IN
OUT
C1
+
C2
0.1u
C3
0.1u
47u
DGND
AGND
E
D
C
B
A
E
D
C
B
A
REG
HVDD
AVDD
DVDD
TVDD
LVC_IN1 VD_IN1
T45_B T45_O
DGND1
CN1
HVDD
32pin_4
T45_BK
JP2
REG
L1
R100
2
1
2
2
2
2
4665_HVDD
C5
4.7u
2
C4
(short)
+
1
47u
C6
2.2u
2
LVC_IN VD_IN
1
R2
51
R3
51
R4
51
R5
51
AVDD
R1
10
JP3
AVDD_SEL
4665_AVDD
C7
0.1u
L2
C8
0.1u
1
C9
0.1u
U1
C10
47u
(short)
+
R6 51
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
LRCK
MICIN
MPWR
AINL1
AINR1
LIN
CN3
1
CN2
24
C11
0.22u
JP5
MPWR
DVDD
R8 51
R10 51
R7 51
R11 51
LRCK
MCLK
BICK
JP4
DVDD_SEL
MCLK
BICK
INT
L3
1
R9 2.2k
2
3
4
5
6
7
23
C12
47u
(short)
+
22
AINL1
SDTI
SDTI
21
AINR1
LIN
SDTO
TVDD
JP6
TVDD_SEL
SDTO
TVDD
DVSS
DVDD
20
4665A
L4
1
19
RIN
RIN
C13
47u
(short)
+
+
C14
10u
C15
0.1u
18
MIN
8
MIN
C16
0.1u
17
LOUT
32pin_1
LOUT
32pin_3
C17
2.2u
C18 C19
0.1u 2.2u
LVC_IN
1
JP7
TVDD LVC_SEL
1
2
L5
2
C20
10u
LVC
C21
47u
(short)
+
VD
CN4
32pin_2
VD_IN
1
L6
(short)
2
VD
C22
47u
+
Title
Size
AKD4665A-A
Document Number
Rev
1
A3
AK4665A
Date:
Sheet
of
Wednesday, May 17, 2006
1
4
A
B
C
D
E
A
B
C
D
E
J1
MIC-JACK
6
4
3
JP8
C23
R12
220
J2
E
D
C
B
A
E
D
C
B
A
JACK
RCA
MIC_SEL
LOUT
1
2
2
3
1
INT
LOUT
4.7u
R13
10k
MR-552LS
C24
R14
220
J4
ROUT
1
2
2
3
1
ROUT
J3
C25
1u
4.7u
AINL1/MICIN
R15
10k
2
3
1
2
1
MR-552LS
AINL1
R16
(open)
MR-552LS
J5
AINR1
C26
1u
1
2
3
1
2
J6
HPL
AINR1
2
3
1
R17
(open)
MR-552LS
R18
16
MR-552LS
R19
(short)
JP9
HPL
HPL
HPR
J7
HP
6
R20
(short)
4
3
J8
LIN/RIN/MIN
JP10
2
4
1
3
5
2
3
1
LIN
RIN
MIN
JP11
HPR
LIN
RIN
MIN
6
C27
0.047u
R21
(open)
LIN/RIN/MIN
MR-552LS
J9
HPR
2
3
1
R22
16
MR-552LS
Title
Size
AKD4665A-A
Document Number
Rev
1
A3
ANALOG
Date:
Sheet
of
Wednesday, May 17, 2006
2
4
A
B
C
D
E
A
B
C
D
E
C28 C29
0.1u 0.1u
VD
VD
L7
(short)
74HC14_1
U2B
U2A
R23
10k
VD
D1
E
D
C
B
A
E
D
C
B
A
74HC14_1
VD
HSU119
PORT1
VCC
GND
OUT
C30
0.1u
3
2
1
C31
10u
1
2
1
4
3
R24
470
2
VD
TORX141
L
H
C33
0.1u
C32
0.1u
SW1
DIR
C34
0.47u
R25
18k
U4
SW2
DIF0
1
2
3
4
5
10
9
8
7
6
VD
U3A
DIF1
DIF2
R26
1k
LED1
ERF
CM0
OCKS1
1
2
36
35
34
33
32
31
30
29
28
27
26
25
1
2
K
A
IPS0
INT0
OCKS0
OCKS1
CM1
VD
74HC04
MODE
NC
RP1
6
5
4
3
2
1
3
DIF0
OCKS1
CM0
OCKS1
4
TEST2
DIF1
NC
47k
5
CM0
CM0
6
PDN
AK4114
C35 5p
C36
7
DIF2
IPS1
P/SN
XTL0
XTL1
VIN
XTI
X1
JP12
XTI
R27
51
MCLK
J10
11.2896MHz
5p
8
2
3
1
XTO
9
MR-552LS
DAUX
MCKO2
BICK
DAUX
JP13
EXT
10
11
12
R28
51
DIR_BICK
DIR_SDTI
SDTO
C37
0.1u
C38
0.1u
DIR_LRCK
DIR_MCLK
1
2
1
2
C39
10u
C40
10u
VD
VD
PORT2
IN
VCC
GND
3
2
1
VD
C41
0.1u
TOTX141
Title
Size
AKD4665A-A
Document Number
Rev
1
A3
DIR/DIT
Date:
Sheet
of
Wednesday, May 17, 2006
3
4
A
B
C
D
E
A
B
C
D
E
LVC
1
2
3
4
5
6
7
8
9
R29 1k
VD
LVC
U5A
VD
2
1
DAUX
SDTO
RP2
R-PACK8R
U2C
U2D
74HC14_1
74LVC07
E
D
C
B
A
E
D
C
B
A
R30
10k
VD
74HC14_1 VD
D2
C46
0.1u
HSU119
VD
5
6
9
8
U6A
PDN1
2
1
SDTI
BICK
MCLK
SDTI1
BICK1
L
H
74LVC07
SW3
PDN
C42
0.1u
VD
VD
VD
U6B
4
6
3
74LVC07
U6C
5
MCLK1
U2E
74HC14_1
74LVC07
VD
U6D
INV JP15
JP14
1
11
10
8
9
DIR_BICK
LRCK
LRCK1
2
BICK1
3
74LVC07
DIR_BICK
THR BICK_INV
U6E
10
12
2
11
CCLK/SCL
CSN/CAD0
PDN
CCLK1/SCL
CSN1/CAD0
PDN1
74LVC07
JP16
LRCK1
DIR_LRCK
DIR_MCLK
U6F
DIR_LRCK
JP19
13
PORT3
74LVC07
MCLK
BICK
LRCK
SDTI
VD
1
2
3
4
5
10 GND
9
8
7
6
GND
VD
NC
U8A
DIR_MCLK
NC
JP17
SDTO
1
DSP
74LVC07
SDTO
MCLK1
VD
VD
C44
0.1u
R31
10k
LVC
JP18
C45
0.1u
VD
1
ADC
C47
0.1u
U3B
DAUX
2
3
4
SDTI1
3
DIR
DIR_SDTI
74HC04
SDTI
U5C
74LVC07
5
U8C
6
5
6
U3C
6
5
9
74LVC07
CSN1/CAD0
CCLK1/SCL
74HC04
VD
U8B
U5D
U8D
74LVC07
9
R32
R33
R34
10k
10k
10k
R36
R35
R37
470
470
470
U3D
8
VD
9
8
8
3
4
74LVC07
CDTI/SDA
74HC04
PORT4
A1-10PA-2.54DSA
74LVC07
VD
U5E
U8E
C43
U3E
10
1
2
3
4
5
10 CSN
11
13
11
10
12
11
10
12
9
8
7
6
SCL/CCLK
SDA/CDTI
SDA(ACK)
74LVC07
74LVC07
0.1u
74HC04
R38
R39
51
1k
U2F
13
74HC14_1
U5F
U8F
LVC
U5B
12
U3F
12
13
13
uP-I/F
74LVC07
74LVC07
VD
74HC04
4
3
74LVC07
Title
Size
AKD4665A-A
Document Number
Rev
1
A3
Interface
Date:
Sheet
of
Wednesday, May 17, 2006
4
4
A
B
C
D
E
相关型号：
AKD4683-B
24bit CODEC that has two channels of ADC and four channels of DAC with internal DIR, DIT
AKM
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