APW7062B_08 [ANPEC]
Synchronous Buck PWM Controller; 同步降压PWM控制器
| 型号： | APW7062B_08 |
| 厂家： | 
ANPEC ELECTRONICS COROPRATION |
| 描述： | Synchronous Buck PWM Controller |
| 文件： | 总18页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APW7062B
Synchronous Buck PWM Controller
Features
General Description
The APW7062B is a voltage mode and synchronous PWM
controller which drives dual N-Channel MOSFETs. It inte-
grates the control, monitoring, and protection functions
into a single package, provides one controlled power
outputs with under-voltage and over-current protection.
APW7062B provides excellent regulation for output load
variation. An internal 0.8V temperature-compensated
reference voltage is designed to meet the requirement of
low output voltage applications. It includes a 200kHz free-
running triangle-wave oscillator that is adjustable from
70kHz to 800kHz.
·
·
·
Simple Single-Loop Control Design
- Voltage-Mode PWM Control
Fast Transient Response
- Full 0–100%DutyRatio
Excellent Output Voltage Regulation
- 0.8V Internal Reference
- ± 1% Over Line Voltage and Temperature
·
Over Current Fault Monitor
- Uses Upper MOSFETs RDS (ON)
·
·
Converter Can Source and Sink Current
Small Converter Size
The power-on-reset (POR) circuit monitors the VCC, EN,
and OCSET input voltage to start-up or shutdown the IC.
The over-current protection (OCP) monitors the output
current by using the voltage drop across the upper
MOSFET’s RDS(ON), eliminating the need for a current sens-
ing resistor. The under-voltage protection (UVP) moni-
tors the voltage of the FB pin for short-circuit protection.
The over-current protection trip cycle the soft-start func-
tion until the fault events be removed. Under-voltage pro-
tection will shutdown the IC directly.
- 200kHz Free-Running Oscillator
- Programmable from 70kHz to 800kHz
·
·
14-Lead SOIC Package
Lead Free and Green Devices Available
(RoHS Compliant)
Applications
Pin Configuration
1
2
3
4
5
6
7
RT
OCSET
SS
VCC
·
·
·
·
Graphic Cards
14
13
12
11
10
9
PVCC
DDR Memory Power Supply
DDR Memory Termination Voltage
Low-Voltage Distributed Power Supplies
LGATE
PGND
BOOT
COMP
FB
UGATE
PHASE
EN
8
GND
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise
customers to obtain the latest version of relevant information to verify before placing orders.
Copyright ã ANPEC Electronics Corp.
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Rev. A.4 - Oct., 2008
APW7062B
Ordering and Marking Information
Package Code
APW7062B
K : SOP-14
Operating Ambient Temperature Range
Assembly Material
Handling Code
C : 0 to 70 oC
Handling Code
TR : Tape & Reel
Assembly Material
Temperature Range
Package Code
L : Lead Free Device G : Halogen and Lead Free Device
APW7062B
APW7062B K :
XXXXX - Date Code
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Absolute Maximum Ratings (Note 1)
Symbol
Parameter
Rating
30
Unit
V
VCC
VCC to GND
VBOOT
VPHASE
BOOT to GND
30
V
PHASE to GND
30
V
Operating Junction Temperature
Storage Temperature
0~150
-65 ~ 150
260
oC
oC
oC
TSTG
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
Note 1 : Stresses above those listed in bsolute Maximum Ratings may cause permanent damage to the device.
Electrical Characteristics
APW7062B
Unit
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
VCC SUPPLY CURRENT
ICC
Nominal Supply
Shutdown Supply
POWER-ON-RESET
Rising VCC Threshold
EN=VCC; UGATE and LGATE Open
EN=0V
-
-
2
-
mA
250
350
mA
VOCSET=4.5VDC
VOCSET=4.5VDC
VOCSET=4.5VDC
-
-
10.4
V
V
V
V
Falling VCC Threshold
8.8
0.8
-
-
-
-
2.0
-
Enable-Input Threshold Voltage
Rising VOCSET Threshold
1.27
OSCILLATOR
Free Running Frequency
Total Variation
RT=OPEN, VCC=12
6kW < RT to GND < 200kW
RT=OPEN
170
-15
-
200
-
230
+15
-
kHz
%
Ramp Amplitude
1.9
VP-P
DVOSC
REFERENCE VOLTAGE ACCURACY
Reference Voltage Tolerance
PWM Error Amplifier
-1
-
-
+1
-
DVREF
%
VREF
0.80
V
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APW7062B
Electrical Characteristics (Cont.)
APW7062B
Unit
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
GATE DRIVERS
IUGATE
RUGATE
ILGATE
RLGATE
TD
Upper Gate Source
Upper Gate Sink
VBOOT=12V, VUGATE=6V
650
800
4
-
7
-
mA
W
ILGATE=0.3A
-
Lower Gate Source
Lower Gate Sink
Dead Time
PVCC=12V, VLGATE=6V
ILGATE=0.3A
550
700
4
mA
W
-
-
7
-
VOUT=2.5V, IOUT=1A, RT=OPEN
50
ns
PROTECTION
FB Under Voltage
-
170
8
50
200
10
-
%
IOCSET
ISS
OCSET Current Source
Soft-Start Current
VOCSET=4.5VDC
230
12
mA
mA
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APW7062B
Typical Operating Characteristics
Power Up
Power Down
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
VCC(5V/div)
SS(2V/div)
VCC(5V/div)
SS(2V/div)
VOUT(1V/div)
VOUT(1V/div)
Time(10ms/div)
Time(10ms/div)
Enable (EN = VCC)
Shutdown(EN=GND)
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
EN(10V/div)
SS(2V/div)
EN(10V/div)
VCC=12V, VIN=12V
VOUT=2.5V, L=2.2uH
SS(2V/div)
VOUT(1V/div)
VOUT(1V/div)
Time(10ms/div)
Time(2ms/div)
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APW7062B
Typical Operating Characteristics (Cont.)
Load Transient Response
Under Voltage Protection
VCC=12V, VIN=12V
VOUT=2.5V, RT=Open
L=2.2uH
VCC=12V, VIN=12V
VOUT(100mV/div)
VOUT=2.5V, L=2.2uH
VOUT(2V/div)
SS(5V/div)
IL(10A/div)
IOUT(2A/div)
UGATE(20V/div)
Time(20ms/div)
Time(20ms/div)
UGATE Rising
UGATEFalling
VCC=12V, VIN=12V
VOUT=2.5V, RT=Open
VCC=12V, VIN=12V
VOUT=2.5V, RT=Open
UGATE(10V/div)
UGATE(10V/div)
LGATE(10V/div)
Phase(10V/div)
LGATE(10V/div)
Phase(10V/div)
Time(50ms/div)
Time(50ms/div)
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APW7062B
Typical Operating Characteristics (Cont.)
UGATE Source Current vs. UGATE Voltage
UGATE Sink Current vs. UGATE Voltage
1.2
1
1.4
1.2
1
VBOOT=12V
VBOOT=12V
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
UGATE Voltage (V)
UGATE Voltage (V)
LGATE Source Current vs. LGATE Voltage
1.4
1.2
LGATE Sink Current vs. LGATE Voltage
1.2
1
PVCC=12V
PVCC=12V
1
0.8
0.6
0.4
0.2
0
0.8
0.6
0.4
0.2
0
0
2
4
6
8
10
12
0
2
4
6
8
10
12
LGATE Voltage (V)
LGATE Voltage (V)
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APW7062B
Typical Operating Characteristics (Cont.)
Over Current Protection
RT Resistance vs. Switching Frequency
10000
1000
100
10
VOUT(1V/div)
RT pull up to 12V
SS(5V/div)
IL(10A/div)
RT pull down to GND
UGATE(20V/div)
1
10
100
1000
Time(20ms/div)
Switching Frequency (kHz)
VCC=12V, VIN=12V, VOUT=2.5V,
ROCEST=1KW, RT=Open, RDS(ON)=14mW,
IOUT=16.3A, L=2.2uH, LOUT=16.3A
Reference Voltage vs. Junction Temperature
Switching Frequency vs. Junction Temperature
0.8
220
VCC=12V
RT=Open
210
0.798
0.796
0.794
0.792
0.79
200
190
180
170
160
-40 -20
0
20 40 60 80 100 120
-40 -20
0
20 40 60 80 100 120
Junction Temperature (°C)
Junction Temperature (°C)
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APW7062B
Block Diagram
VCC
OCSET
GND
Power-On
Reset
EN
SS
IOCSET
200mA
VCC
BOOT
ISS
10mA
UGATE
O.C.P
Comparator
Soft Start
PHASE
5.8V
U.V.P
Comparator
:
2
50%VREF
PVCC
PWM
Comparator
Gate
Control
LGATE
Error
Amp
PGND
VREF
Oscillator
Triangle
Wave
COMP
FB
RT
Typical Application Circuit
12V
C1
R1
10R
1uF
D1
12V
L1
R3
1K
1N4148
R2
10K
1uH
+
+
+
U1
C3
C6
C4
100uF
16V
APW7062B
8
7
6
5
C5
4.7uF
470uF
16V
30mR
470uF
16V
30mR
R4
1
2
3
4
5
6
7
14
13
12
11
10
9
RT
OCSET
SS
COMP
FB
EN
VCC
PVCC
LGATE
PGND
BOOT
UGATE
PHASE
C2
1nF
4
NC
Q1
APM4220
R5
2R2
8
1
2
3
GND
1.2V
C8
0.1uF
C7
0.1uF
L2
8
7
6
5
R10
15K
2.2uH
SHDN
R7
NC
+
+
C10
1000uF
6.3V
C9
1000uF
6.3V
C13
47pF
D2
SR24
2A/40V
C11
4.7uF
Q2
APM4220
R6
0R
C12
8200pF
4
30mR
30mR
1
2
3
R8
1KF
1%
C12
NC
R9
2KF
1%
R8
æ
è
ö
÷
ø
VOUT = VREF ´ 1+
ç
R9
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APW7062B
Function Pin Description
RT (Pin1)
output is rising rapidly. Until the output is in regulation at
t2, the clamp on the COMP is released. This method pro-
vides a rapid and controlled output voltage rise.
When over-current protection occurs, the VOUT is
shutdown, and re-soft-start again, if the over current con-
dition still exists in soft-start, the VOUT is shutdowned
again. After the SS reaches 4.5V, the SS is discharged to
zero. The soft-start is recurring until the over current con-
dition is eliminated.
This pin can adjust the switching frequency. Connect a
resistor from the RT to the GND for increasing the switch-
ing frequency:
4.15´ 106
FS = 200kHz +
RT
(RT to GND,FS = 200kHz to 400kHz)
Conversely, connect a resistor from the RT to the VCC for
decreasing the switching frequency:
VOLTAGE
3.51´ 107
FS = 200kHz -
RT
VSOFT-START
(RT to VCC,FS = 200kHz to 75kHz)
OCSET (Pin2)
VOUT
This pin serves two functions: a shutdown control and
the setting of over current-limit threshold. Pulling this pin
below 1.27V will shutdown the controller, forcing the
UGATE and LGATE signals to be at 0V.
Error Amp
Output
VOSC(MIN)
VSS=1.2V
A resistor (Rocset) connected between this pin and the drain
of the high side MOSFET will determine the over current
limit. An internal 200mA current source will flow through
this resistor, creating a voltage drop, which will be com-
pared with the voltage across the high side MOSFET.
The threshold of the over current limit is therefore given
by:
TIME
t0
t1
t2
t3
Figure 1. Soft-Start Interval
C
=
SS ´ (VOSC(MIN)+t1)
t2
ISS
IOCSET
(
200uA ´ ROCSET
)
VOUT
IPEAK =
SteadyState´ DVOSC
CSS
tSoftStart= t3 - t2
=
´
RDS(ON)
ISS
VIN
To avoid the noise interference from switching transient,
a delay time is designed in the OCP comparator.
The over-current protection is active only when the high
side MOSFET is turned on longer than 300ns.
Where :
t1=1.2V
CSS = Soft-Start Capacitor
ISS = Soft-Start Current = 10mA
SS (Pin3)
VOSC(MIN) = Bottom of Oscillator = 1.35V
VIN = Input Voltage
Connect a capacitor from the pin to the GND to set the
soft-start interval of the converter. An internal 10mA current
source charges this capacitor to 5.8V. The SS voltage
clamps the error amplifier output, and Figure1 shows the
soft-start interval. At t1, the SS voltage reaches the valley
of the oscillator’s triangle wave. The PWM comparator
starts to generate a PWM signal to control logic, and the
DVosc = Peak to Peak Oscillator Voltage = 1.9V
DVOUTSteadyState = Steady State Output Voltage
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APW7062B
Function Pin Description (Cont.)
COMP (Pin4)
BOOT (Pin 10)
This pin is the output of the error amplifier. Add an exter-
nal resistor and capacitor network to provide the loop com-
pensation for the PWM converter (see Application
Information).
This pin provides the supply voltage to the high side
MOSFET driver. For driving logic levelN-channel MOSEFT,
a bootstrap circuit can be used to create a suitable driver’s
supply.
FB(Pin5)
PGND(Pin11)
FB pin is the inverter input of the error amplifier and it
receives the feedback voltage from an external resis-tive
divider across the output (VOUT). The output voltage is
determined by:
Power ground for the gate diver. Connect the lower
MOSFET source to this pin.
LGATE (Pin 12)
Connect the pin to the external MOSFET, and provides
the gate drive signal for the lower MOSFET.
ROUT
RGND
æ
è
ö
÷
ø
VOUT = 0.8V´ 1+
ç
Where ROUT is the resistor connected from the VOUT to the
FB and RGND is the resistor connected from the FB to the
PVCC (Pin13)
GND.
This pin provides a supply voltage for the lower gate
drive, connect it to the VCC pin in common use.
If the FB voltage is under 50% VREF because of the short
circuit or other influence , it will cause the under-voltage
protection, and the device is shutdowned. Remove the
error condition and restart the VCC voltage or pull the EN
from low to high once, the device can be enabled again.
VCC (Pin14)
This pin provides a supply voltage for the device. When
the VCC is above the rising threshold 10.4V, the device is
turned on; conversely, when the VCC is below the falling
threshold, the device is turned off.
EN (Pin6)
Pull the pin higher than 2V to enable the device, and pull
the pin lower than 0.8V to shutdown the device. In
shutdown, the SS is discharged and the UGATE and
LGATE pins are held low. The EN pin is the open-collector,
and it will not be floating.
GND(Pin7)
Signal ground for the IC.
PHASE (Pin8)
This pin is connected to the source of the high-side
MOSFET and is used to monitor the voltage drop across
the high-side MOSFET for over-current protection.
UGATE(Pin9)
Connect the pin to external MOSFET, and provides the
gate drive for the upper MOSFET.
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APW7062B
Application Information
Component Selection Guidelines
Output Capacitor Selection
and vice versa. The maximum ripple current occurs at the
maximum input voltage. A good starting point is to choose
the ripple current to be approximately 30% of the maxi-
mum output current.
The selection of COUT is determined by the required effec-
tive series resistance (ESR) and voltage rating rather than
the actual capacitance requirement. Therefore, select high
performance low ESR capacitors that are intended for
switching regulator applications. In some applications,
multiple capacitors have to be paralled to achieve the
desired ESR value. If tantalum capacitors are used, make
sure they are surge tested by the manufactures. If in doubt,
consult the capacitors manufacturer.
Once the inductance value has been chosen, select an
inductor that is capable of carrying the required peak cur-
rent without going into saturation. In some types of
inductors, especially core that is make of ferrite, the ripple
current will increase abruptly when it saturates. This will
result in a larger output ripple voltage.
Input Capacitor Selection
Compensation
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
current rating requirement is approximately IOUT/2 , where
IOUT is the load current. During power up, the input capaci-
tors have to handle large amount of surge current. If tanta-
lum capacitors are used, make sure they are surge tested
by the manufactures. If in doubt, consult the capacitors
manufacturer.
The output LC filter introduces a double pole, which con-
tributes with –40dB/decade gain slope and 180 degrees
phase shift in the control loop. A compensation network
between the COMP pin and the ground should be added.
The simplest loop compensation network is shown in
Figure 5.
The output LC filter consists of the output inductor and
output capacitors. The transfer function of the LC filter is
given by:
1+ s´ ESR´ COUT
s2 ´ L´ COUT + s´ ESR +1
GAINLC
=
For high frequency decoupling, a ceramic capacitor be-
tween 0.1mF to 1mF can be connected between the VCC
and the ground pin.
The poles and zero of this transfer function are:
1
FLC
=
Inductor Selection
2´ p´ L´ COUT
1
The inductance of the inductor is determined by the out-
put voltage requirement. The larger the inductance, the
lower the inductor’s current ripple. This will translate into
lower output ripple voltage. The ripple current and ripple
voltage can be approximated by:
FESR
=
2´ p ´ ESR´ COUT
The FLC is the double poles of the LC filter, and FESR is the
zero introduced by the ESR of the output capacitor.
VIN - VOUT
FSx L
VOUT
VIN
PHASE
L
Output
IRIPPLE
=
x
COUT
ESR
DVOUT = IRIPPLE x ESR
where Fs is the switching frequency of the regulator.
There is a tradeoff exists between the inductor’s ripple
current and the regulator load transient response time. A
smaller inductor will give the regulator a faster load tran-
sient response at the expense of higher ripple current
Figure 2. The Output LC Filter
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APW7062B
Application Information (Cont.)
The compensation circuit is shown in Figure 5. R3 and
C1 introduce a zero and C2 introduces a pole to reduce
the switching noise. The transfer function of error ampli-
fier is given by:
Compensation (Cont.)
FLC
-40dB/dec
FESR
é
ù
ú
æ
1 ö
sC1ø
1
sC2 û
gm´ çR3 +
÷//
gm´ Zo
gm´
ê
=
GAINAMP =
=
ç
÷
è
ë
Gain
-20dB/dec
R3sC1+1
C1+ C2
R3´ C1´ C2 ø
æ
ö
s´ çs+
÷
÷
ç
è
The poles and zero of the compensation network are:
Frequency
Figure 3. The Output LC Filter Gain & Frequency
1
FP =
C1´ C2
The PWM modulator is shown in Figure 4. The input is
the output of the error amplifier and the output is the PHASE
node. The transfer function of the PWM modulator is given
2´ p´ R3´
C1+ C2
1
FZ
=
2´ p ´ R3 ´ C1
by:
VIN
DVOSC
VOUT
GAINPWM =
VIN
Error
Amplifier
R1
Driver
FB
-
COMP
PWM
Comparator
R2
+
R3
C1
VOSC
VREF
C2
Output of
Error
PHASE
Amplifier
Figure 5. Compensation Network
Driver
Figure 4. The PWM Modulator
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APW7062B
Application Information (Cont.)
Compensation (Cont.)
MOSFETSelection
The closed loop gain of the converter can be written as:
The selection of the N-channel power MOSFETs are de-
termined by the RDS(ON), reverse transfer capacitance (CRSS
)
R2
R1+R2
x GAINAMP
GAINLC x GAINPWM x
and maximum output current requirement.The losses in
the MOSFETs have two components: conduction loss and
transition loss. For the upper and lower MOSFET, the
losses are approximately given by the following :
Figure 6 shows the converter gain and the following guide-
lines will help to design the compensation network.
1.Select the desired zero crossover frequency FO:
(1/5 ~ 1/10) x FS >FO>FZ
PUPPER = Iout2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FS
PLOWER = Iout2(1+ TC)(RDS(ON))(1-D)
Use the following equation to calculate R3:
DVOSC FESR R1+R2 FO
where IOUT is the load current
R3 =
´
´
´
2
VIN
R2
gm
TC is the temperature dependency of RDS(ON)
FS is the switching frequency
FLC
Where:
gm=900mA/V
tsw is the switching interval
D is the duty cycle
2.Place the zero FZ before the LC filter double poles FLC:
FZ = 0.75 x FLC
Note that both MOSFETs have conduction losses while
the upper MOSFET include an additional transition loss.
The switching internal, tsw, is the function of the reverse
transfer capacitance CRSS. Figure 7 illustrates the switch-
ing waveform internal of the MOSFET.
Calculate the C1 by the equation:
1
C1 =
2´ p ´ R1´ FLC ´ 0.75
The (1+TC) term is to factor in the temperature depen-
dency of the RDS(ON) and can be extracted from the “RDS(ON)
vs Temperature” curve of the power MOSFET.
3. Set the pole at the half the switching frequency:
FP = 0.5xFS
Calculate the C2 by the equation:
Layout Consideration
C1
C2 =
In high power switching regulator, a correct layout is im-
portant to ensure proper operation of the regulator. In
general, interconnecting impedances should be mini-
mized by using short and wide printed circuit traces. Sig-
nal and power grounds are to be kept separate and finally
combined using ground plane construction or single point
grounding. Figure 8 illustrates the layout, with bold lines
indicating high current paths. Components along the bold
lines should be placed close together. Below is a check-
list for your layout:
p´ R3´ C1´ FS - 1
FZ=0.75FLC
FP=0.5FS
20×log(gm×R3)
Compensation
Gain
FLC
VIN
FO
· Keep the switching nodes (UGATE, LGATE, and
PHASE) away from sensitive small signal nodes since
these nodes are fast moving signals. There fore keep
traces to these nodes as short as possible.
20×log
?VOSC
Converter
Gain
FESR
PWM &
Filter Gain
· The ground return of CIN must return to the combine
COUT (-) terminal.
Frequency
· Capacitor CBOOT should be connected as close to the
BOOT and PHASE pins as possible.
Figure 6. Converter Gain & Frequency
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Rev. A.4 - Oct., 2008
APW7062B
Application Information (Cont.)
Layout Consideration (Cont.)
VDS
tsw
Time
Figure 7. Switching waveform across MOSFET
VIN
CIN
APW7062B
+
11
12
PGND
L
O
A
D
LGATE
COUT
9
8
Q1
UGATE
PHASE
Q2
+
L1
VOUT
Figure 8. Recommended Layout Diagram
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Rev. A.4 - Oct., 2008
APW7062B
Package Information
SOP-14
D
SEE VIEW A
c
e
b
GAUGE PLANE
SEATING PLANE
L
VIEW A
SOP-14
S
Y
M
B
O
L
MILLIMETERS
INCHES
MIN.
MAX.
1.75
0.25
MIN.
MAX.
A
0.069
0.010
0.004
0.049
0.012
0.007
A1
A2
b
0.10
1.25
0.31
0.17
8.55
5.80
3.80
0.020
0.010
0.51
0.25
8.75
6.20
4.00
c
D
0.337
0.228
0.150
0.344
0.244
0.157
E
E1
e
1.27 BSC
0.050 BSC
0.010
0.016
0.020
0.050
0.25
0.40
0.50
1.27
h
L
°
°
0
0
8
0
8
Note: 1. Follow JEDEC MS-012 AB.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.
3. Dimension “E” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.
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Rev. A.4 - Oct., 2008
APW7062B
Carrier Tape & Reel Dimensions
P0
P2
P1
OD0
A
K0
A0
A
OD1
B
B
SECTION A-A
SECTION B-B
d
T1
Application
SOP-14
A
H
T1
C
d
D
W
E1
F
16.4+2.00 13.0+0.50
330.0±2.00 50 MIN.
1.5 MIN.
D1
20.2 MIN.
16.0±0.30 1.75±0.10
7.50±0.10
K0
-0.00 -0.20
P0
P1
P2 D0
T
A0
B0
1.5+0.10
-0.00
0.6+0.00
-0.40
4.0±0.10
8.0±0.10
2.0±0.10
1.5 MIN.
6.40±0.20
9.00±0.20
2.10±0.20
(mm)
Devices Per Unit
Package Type
SOP-14
Unit
Quantity
Tape & Reel
2500
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Rev. A.4 - Oct., 2008
APW7062B
Taping Direction Information
SOP-14
USER DIRECTION OF FEED
t
Reflow Condition (IR/Convection or VPR Reflow)
tp
TP
Critical Zone
TL to TP
Ramp-up
TL
tL
Tsmax
Tsmin
Ramp-down
ts
Preheat
25
°
t 25 C to Peak
Time
Reliability Test Program
Test item
SOLDERABILITY
Method
MIL-STD-883D-2003
Description
245°C, 5 sec
HOLT
PCT
TST
ESD
Latch-Up
MIL-STD-883D-1005.7
JESD-22-B, A102
MIL-STD-883D-1011.9
MIL-STD-883D-3015.7
JESD 78
1000 Hrs Bias @125°C
168 Hrs, 100%RH, 121°C
-65°C~150°C, 200 Cycles
VHBM > 2KV, VMM > 200V
10ms, 1tr > 100mA
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Rev. A.4 - Oct., 2008
APW7062B
Classification Reflow Profiles
Profile Feature
Average ramp-up rate
(TL to TP)
Sn-Pb Eutectic Assembly
Pb-Free Assembly
3°C/second max.
3°C/second max.
Preheat
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
- Temperature Min (Tsmin)
- Temperature Max (Tsmax)
- Time (min to max) (ts)
Time maintained above:
- Temperature (TL)
183°C
60-150 seconds
217°C
60-150 seconds
- Time (tL)
Peak/Classification Temperature (Tp)
See table 1
See table 2
Time within 5°C of actual
Peak Temperature (tp)
10-30 seconds
20-40 seconds
Ramp-down Rate
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25°C to Peak Temperature
Notes: All temperatures refer to topside of the package. Measured on the body surface.
Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures
Volume mm3
350
Volume mm3
Package Thickness
<350
<2.5 mm
³ 2.5 mm
240 +0/-5°C
225 +0/-5°C
225 +0/-5°C
225 +0/-5°C
Table 2. Pb-free Process – Package Classification Reflow Temperatures
Volume mm3
Volume mm3
Volume mm3
>2000
Package Thickness
<350
350-2000
<1.6 mm
1.6 mm – 2.5 mm
³ 2.5 mm
260 +0°C*
260 +0°C*
250 +0°C*
260 +0°C*
250 +0°C*
245 +0°C*
260 +0°C*
245 +0°C*
245 +0°C*
* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated
classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL
level.
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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Rev. A.4 - Oct., 2008
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