CY7C4265-35JIT [CYPRESS]
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| 型号： | CY7C4265-35JIT |
| 厂家： | 
CYPRESS |
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CY7C4255
CY7C4265
8K/16K x 18 Deep Sync FIFOs
are 18 bits wide and are pin/functionally compatible to the
CY7C42X5 Synchronous FIFO family. The CY7C4255/65 can
be cascaded to increase FIFO depth. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and commu-
nications buffering.
Features
• High-speed, low-power, first-in first-out (FIFO)
memories
• 8K x 18 (CY7C4255)
• 16K x 18 (CY7C4265)
• 0.5 micron CMOS for optimum speed/power
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a Free-Running Clock (WCLK) and a Write En-
able pin (WEN).
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power — ICC = 45 mA
• Fully asynchronous and simultaneous read and write
operation
• Empty, Full, HalfFull, andprogrammableAlmostEmpty
and Almost Full status flags
• TTL compatible
• Retransmit function
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-runningRead Clock (RCLK) anda Read
Enable pin (REN). In addition, the CY7C4255/65 have an Output
Enable pin (OE). The read and write clocks may be tied together for
single-clock operation or the two clocks may be run independently for
asynchronous read/write applications. Clock frequencies up to 100
MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
• Depth Expansion Capability
• 64-pin TQFP and 64-pin STQFP
• Pin-compatible density upgrade to CY7C42X5 family
• Pin-compatible density upgrade to
IDT72205/15/25/35/45
Depth expansion is possible using the Cascade Input (WXI,
RXI), Cascade Output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to VSS and the FL pin of all the remaining devic-
Functional Description
es should be tied to VCC
.
The CY7C4255/65 are high-speed, low-power, first-in first-out
(FIFO) memories with clocked read and write interfaces. All
D
0 – 17
Logic Block Diagram
INPUT
REGISTER
WCLK
WEN
FLAG
PROGRAM
REGISTER
WRITE
CONTROL
FF
EF
FLAG
LOGIC
RAM
PAE
PAF
ARRAY
8K x 18
16K x 18
SMODE
WRITE
READ
POINTER
POINTER
RS
RESET
LOGIC
FL/RT
THREE–STATE
OUTPUTREGISTER
READ
CONTROL
WXI
WXO/HF
RXI
EXPANSION
LOGIC
OE
Q
0 – 17
RXO
4255–1
RCLK
REN
Cypress Semiconductor Corporation
Document #: 38-06004 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised August 11, 2004
CY7C4255
CY7C4265
Pin Configurations
TQFP/STQFP
Top View
Q
Q
48
47
D
15
D
14
D
13
D
12
1
2
14
13
GND
46
45
3
4
Q
12
Q
V
44
43
42
41
11
D
D
5
6
7
8
11
CC
10
CY7C4255
CY7C4265
Q
10
D
9
Q
9
D
D
8
7
6
GND
40
39
9
10
Q
8
D
D
D
D
D
D
38
37
36
11
12
13
Q
7
5
Q
6
4
Q
5
3
35
34
14
15
GND
2
Q
4
1
D
0
33
V
CC
16
4255–3
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the Write
Clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. The Almost Empty/Almost Full
Functional Description (continued)
The CY7C4255/65 provides five status pins. These pins are decod-
ed to determine one of five states: Empty, Almost Empty, Half Full,
Almost Full, and Full. The Half Full flag shares the WXO pin. This flag
is validinthestand-alone andwidth-expansion configurations. In
the depth expansion, this pin provides the expansion out
(WXO) information that is used to signal the next FIFO
when it will be activated.
flags become synchronous if the VCC/SMODE is tied to VSS
.
All configurations are fabricated using an advanced 0.5µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
7C4255/65-10
7C4255/65-15
7C4255/65-25
7C4255/65-35
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
100
8
66.7
10
15
4
40
15
25
6
28.6
20
35
7
10
3
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
0.5
8
1
1
2
10
45
50
15
45
50
20
45
50
Active Power Supply
Current (ICC1) (mA)
Commercial
Industrial
45
50
CY7C4255
8K x 18
CY7C4265
Density
16K x18
Package
64-pin TQFP, STQFP 64-pin TQFP, STQFP
Document #: 38-06004 Rev. *B
Page 2 of 22
CY7C4255
CY7C4265
Signal Name
D0 –17
Description
Data Inputs
I/O
Function
I
O
I
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK inpu.t
Enables the RCLK input.
Q0–17
Data Outputs
Write Enable
Read Enable
Write Clock
WEN
REN
I
WCLK
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
RCLK
Read Clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
WXO/HF
Write Expansion
Out/Half Full Flag
O
Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
EF
Empty Flag
Full Flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
Almost Empty
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied
to VCC; it is synchronized to RCLK when VCC/SMODE is tied to VSS
.
PAF
Programmable
Almost Full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to
VCC; it is synchronized to WCLK when VCC/SMODE is tied to VSS
.
LD
Load
I
I
When LD is LOW, D0–17 (Q0–17) are written (read) into (from) the programma-
ble-flag-offset register.
FL/RT
First Load/
Retransmit
Dual-Mode Pin:
Cascaded – The first device in the daisy chain will have FL tied to VSS; all other
devices will have FL tied to VCC. In standard mode or width expansion, FL is tied
to VSS on all devices.
Not Cascaded – Tied to VSS. Retransmit function is also available in stand-alone
mode by strobing RT.
WXI
RXI
RXO
RS
Write Expansion
Input
I
I
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to VSS
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to VSS
.
Read Expansion
Input
.
Read Expansion
Output
O
I
Cascaded – Connected to RXI of next device.
Reset
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
OE
Output Enable
I
When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-
nected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
VCC/SMODE Synchronous
Almost Empty/
I
Dual-Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to VCC
Synchronous Almost Empty/Almost Full flags – tied to VSS
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
.
Almost Full Flags
.
Document #: 38-06004 Rev. *B
Page 3 of 22
CY7C4255
CY7C4265
Maximum Ratings [1]
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL–STD–883, Method 3015)
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Latch-Up Current..................................................... >200 mA
Storage Temperature ................................–65°C to +150°C
Ambient Temperature with Power Applied.–55°C to +125°C
Supply Voltage to Ground Potential............... –0.5V to +7.0V
Operating Range[2]
Ambient
Range
Commercial
Industrial[3]
Temperature
0°C to +70°C
–40°C to +85°C
VCC
DC Voltage Applied to Outputs
in High Z State ............................................... –0.5V to +7.0V
5V ± 10%
5V ± 10%
DC Input Voltage ..........................................−0.5V to VCC+0.5V
Electrical Characteristics Over the Operating Range[3]
7C42X5–10 7C42X5–15 7C42X5–25 7C42X5– 35
Parameter
Description
Test Conditions
Min. Max. Min. Max. Min. Max. Min. Max. Unit
VOH
Output HIGH Voltage VCC = Min.,
IOH = –2.0 mA
2.4
2.4
2.4
2.4
V
VOL
Output LOW Voltage
VCC = Min.,
IOL = 8.0 mA
0.4
0.4
0.4
0.4
V
[4]
VIH
Input HIGH Voltage
Input LOW Voltage
2.0
–0.5
–10
VCC
0.8
2.0
–0.5
–10
VCC
0.8
2.0
–0.5
–10
VCC
0.8
2.0
–0.5
–10
VCC
0.8
V
V
[5]
VIL
IIX
Input Leakage
Current
VCC = Max.
+10
+10
+10
+10
µA
IOZL
IOZH
Output OFF,
High Z Current
OE > VIH,
VSS < VO < VCC
–10
+10
–10
+10
–10
+10
–10
+10
µA
[6]
ICC1
Active Power Supply
Current
Com’l
45
50
10
15
45
50
10
15
45
50
10
15
45
50
10
15
mA
mA
mA
mA
Ind
[7]
ICC2
Average Standby
Current
Com’l
Ind
Capacitance[8, 9]
Parameter
Description
Input Capacitance
Output Capacitance
Test Conditions
Max.
Unit
CIN
TA = 25°C, f = 1 MHz,
VCC = 5.0V
5
7
pF
pF
COUT
Notes:
1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.
2. is the “Instant On” case temperature.
3. See the last page of this specification for Group A subgroup testing information.
4. The V and V specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
T
A
IH
IL
previous device or V
.
SS
5. The V and V specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
IH
IL
previous device or V
SS.
6. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10 MHz. Outputs
are unloaded. I 1(typical) = (25 mA+(freq –20 MHz)*(1.0 mA/MHz)).
CC
7. All inputs = V
– 0.2V, except RCLK and WCLK (which are switching at frequency = 20 MHz), and FL/RT which is at V . All outputs are unloaded.
CC
ss
8. Tested initially and after any design changes that may affect these parameters.
9. Tested initially and after any process changes that may affect these parameters.
Document #: 38-06004 Rev. *B
Page 4 of 22
CY7C4255
CY7C4265
AC Test Loads and Waveforms[10, 11]
R1 1.1 KΩ
ALL INPUT PULSES
5V
3.0V
GND
90%
10%
90%
10%
OUTPUT
R2
680Ω
C
L
≤ 3 ns
≤ 3 ns
INCLUDING
JIG AND
4255–4
4255–5
SCOPE
Equivalentto:
THÉVENIN EQUIVALENT
410Ω
OUTPUT
1.91V
Switching Characteristics Over the Operating Range
7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35
Parameter
tS
Description
Clock Cycle Frequency
Min. Max. Min. Max. Min. Max. Min. Max. Unit
100
8
66.7
10
40
15
28.6 MHz
20
tA
Data Access Time
2
10
4.5
4.5
3
2
15
6
2
25
10
10
6
2
35
14
14
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
6
Data Set-Up Time
4
tDH
Data Hold Time
0.5
3
1
1
2
tENS
tENH
tRS
Enable Set-Up Time
4
6
7
Enable Hold Time
0.5
10
8
1
1
2
Reset Pulse Width[12]
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Pulse Width
Retransmit Recovery Time
Output Enable to Output in Low Z[12]
Output Enable to Output Valid
Output Enable to Output in High Z[13]
Write Clock to Full Flag
Read Clock to Empty Flag
15
10
25
15
35
20
tRSR
tRSF
tPRT
tRTR
tOLZ
tOE
10
15
25
35
30
60
0
35
65
0
45
75
0
55
85
0
3
7
7
3
8
3
12
12
15
15
20
3
15
15
20
20
25
tOHZ
tWFF
tREF
tPAFasynch
3
3
8
3
3
8
10
10
16
8
Clock to Programmable Almost-Full Flag[13]
(Asynchronous mode, VCC/SMODE tied to
12
VCC
)
tPAFsynch
tPAEasynch
tPAEsynch
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS
Clock to Programmable Almost-Empty Flag[14]
(Asynchronous mode, VCC/SMODE tied to VCC
8
12
8
10
16
10
16
15
20
15
20
20
25
20
25
ns
ns
ns
ns
)
)
Clock to Programmable Almost-Full Flag
(Synchronous mode, VCC/SMODE tied to VSS
)
tHF
Clock to Half-Full Flag
12
Notes:
10.
11.
C
C
= 30 pF for all AC parameters except for t
.
OHZ
L
L
= 5 pF for t
.
OHZ
12. Pulse widths less than minimum values are not allowed.
13. Values guaranteed by design, not currently tested.
14.
t
, t
, after program register write will not be valid until 5 ns + t
.
PAFasynch PAEasynch
PAF(E)
Document #: 38-06004 Rev. *B
Page 5 of 22
CY7C4255
CY7C4265
Switching Characteristics Over the Operating Range (continued)
7C42X5-10 7C42X5-15 7C42X5-25 7C42X5-35
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Parameter
tXO
Description
Clock to Expansion Out
6
10
15
20
ns
ns
ns
ns
tXI
Expansion in Pulse Width
Expansion in Set-Up Time
4.5
4
6.5
5
10
10
10
14
15
12
tXIS
tSKEW1
Skew Time between Read Clock and Write
Clock for Full Flag
5
6
tSKEW2
tSKEW3
Skew Time between Read Clock and Write
Clock for Empty Flag
5
6
10
18
12
20
ns
ns
Skew Time between Read Clock and Write
Clock for Programmable Almost Empty and Pro-
grammable Almost Full Flags (Synchronous
Mode only)
10
15
Document #: 38-06004 Rev. *B
Page 6 of 22
CY7C4255
CY7C4265
Switching Waveforms
Write Cycle Timing
t
CLK
t
t
CLKL
CLKH
WCLK
t
t
DH
DS
D –D
0
17
t
ENH
t
ENS
WEN
FF
NO OPERATION
t
t
WFF
WFF
[15]
t
SKEW1
RCLK
REN
4255–6
Read Cycle Timing
t
CLK
t
t
CLKL
CLKH
RCLK
t
t
ENH
ENS
REN
EF
NO OPERATION
t
REF
t
REF
t
A
VALID DATA
Q –Q
0
17
t
OLZ
t
OHZ
t
OE
OE
[16]
t
SKEW2
WCLK
WEN
4255–7
Notes:
15.
t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between
SKEW1
the rising edge of RCLK and the rising edge of WCLK is less than t
, then FF may not change state until the next WCLK rising edge.
SKEW1
16.
t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
SKEW2
the rising edge of WCLK and the rising edge of RCLK is less than t
, then EF may not change state until the next RCLK rising edge.
SKEW2
Document #: 38-06004 Rev. *B
Page 7 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Reset Timing [17]
t
RS
RS
t
RSR
REN,WEN,
LD
t
t
t
RSF
RSF
RSF
EF,PAE
FF,PAF,
HF
[18]
OE=1
Q
Q
0 – 17
OE=0
4255–8
First Data Word Latency after Reset with Simultaneous Read and Write
WCLK
t
DS
D –D
D
0
(FIRSTVALIDWRITE)
D
1
D
2
D
3
D
4
0
17
t
ENS
[19]
FRL
t
WEN
t
SKEW2
RCLK
t
REF
EF
REN
[19]
t
A
t
A
Q –Q
D
0
D
1
0
17
t
OLZ
t
OE
OE
4255–9
Notes:
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
19. When t > minimum specification, t (maximum) = t + t . When t
< minimum specification, t
(maximum) = either 2*t
+ t
or t
+
SKEW2
FRL
CLK
SKEW2
SKEW2
FRL
CLK
SKEW2
CLK
t
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW2
20. The first word is available the cycle after EF goes HIGH, always.
Document #: 38-06004 Rev. *B
Page 8 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Empty Flag Timing
WCLK
t
t
DS
DS
D0
D1
D –D
0
17
t
t
ENH
ENH
t
t
ENS
ENS
WEN
[18]
FRL
t
[18]
FRL
t
RCLK
t
t
t
t
REF
t
SKEW2
REF
REF
SKEW2
EF
REN
OE
t
A
D0
Q –Q
0
17
4255–10
Full FlagTiming
NO WRITE
NO WRITE
WCLK
[15]
[15]
t
t
DS
DATA WRITE
t
SKEW1
SKEW1
DATA WRITE
D –D
0
17
t
t
t
WFF
WFF
WFF
FF
WEN
RCLK
t
t
ENH
ENH
t
t
ENS
ENS
REN
OE
LOW
t
A
t
A
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
Q –Q
0
17
4255–11
Document #: 38-06004 Rev. *B
Page 9 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Half-Full Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
HF
HALF FULL + 1
OR MORE
HALF FULLOR LESS
HALF FULLOR LESS
HF
t
HF
RCLK
REN
t
ENS
4255–12
Programmable Almost Empty Flag Timing
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENH
ENS
t
PAE
[20]
N + 1 WORDS
IN FIFO
PAE
n WORDS IN FIFO
t
PAE
RCLK
REN
t
ENS
4255–13
Note:
21. PAE is offset = n. Number of data words into FIFO already = n.
Document #: 38-06004 Rev. *B
Page 10 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENS
ENH
WEN2
PAE
t
t
ENS
[23]
ENH
Note
22
N + 1 WORDS
INFIFO
Note
24
t
PAE synch
t
t
SKEW3
PAE synch
RCLK
REN
t
ENS
t
t
ENH
ENS
4255–14
Programmable Almost Full Flag Timing
t
t
CLKL
CLKH
25
Note
WCLK
WEN
t
t
ENH
ENS
t
PAF
FULL– M WORDS
[27]
[26]
INFIFO
PAF
FULL– (M+1) WORDS
[28]
IN FIFO
t
PAF
RCLK
REN
t
ENS
4255–15
Notes:
22. PAE offset − n.
23.
t
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and
SKEW3
the rising RCLK is less than t
, then PAE may not change state until the next RCLK.
SKEW3
24. If a read is preformed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW.
25. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255 and 16384 − (m + 1) for the CY7C4265.
26. PAF is offset = m.
27. 8192 − m words in CY7C4255 and 16384 – m words in CY7C4265.
28. 8192 − (m + 1) words in CY7C4255 and 16384 – (m + 1) CY7C4265.
Document #: 38-06004 Rev. *B
Page 11 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Programmable Almost Full Flag Timing (applies only in SMODE (SMODE is LOW))
Note 29
t
t
CLKL
CLKH
WCLK
WEN
t
t
ENS
ENH
Note
30
WEN2
PAF
t
t
t
PAF
ENS
ENH
FULL– M WORDS
[27]
IN FIFO
FULL– M + 1 WORDS
IN FIFO
t
[31]
PAF synch
t
SKEW3
RCLK
REN
t
ENS
t
t
ENH
ENS
4255–16
Write Programmable Registers
t
CLK
t
t
CLKL
CLKH
WCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
t
DH
DS
PAE OFFSET
D –D
0
17
D
D –
0
PAE OFFSET
PAF OFFSET
11
4255–17
Notes:
29. If a write is performed on this rising edge of the write clock, there will be Full − (m−1) words of the FIFO when PAF goes LOW.
30. PAF offset = m.
31.
t
is the minimum time between a rising RCLK and a rising WCLK edge for PAF to change state during that clock cycle. If the time between the edge of RCLK and
SKEW3
the rising edge of WCLK is less than t
, then PAF may not change state until the next WCLK rising edge.
SKEW3
Document #: 38-06004 Rev. *B
Page 12 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Read Programmable Registers
t
CLK
t
t
CLKL
CLKH
RCLK
LD
t
t
ENS
ENH
t
ENS
WEN
t
A
UNKNOWN
PAE OFFSET
PAF OFFSET
PAE OFFSET
Q –Q
0
17
4255–18
Write ExpansionOut Timing
t
CLKH
WCLK
Note 31
t
XO
Note 32
WXO
t
XO
t
ENS
WEN
4255–19
Read Expansion Out Timing
t
CLKH
WCLK
Note 33
t
XO
RXO
REN
t
XO
t
ENS
4255–20
Write Expansion In Timing
t
XI
WXI
t
XIS
WCLK
4255–21
Notes:
32. Write to Last Physical Location.
33. Read from Last Physical Location.
Document #: 38-06004 Rev. *B
Page 13 of 22
CY7C4255
CY7C4265
Switching Waveforms (continued)
Read Expansion In Timing
t
XI
RXI
t
XIS
RCLK
4255–22
Retransmit Timing [34, 35, 36]
FL/RT
t
PRT
t
RTR
REN/WEN
EF/FF
and all
async flags
HF/PAE/PAF
4255–23
Notes:
34. Clocks are free-running in this case.
35. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t
.
RTR
36. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t
to update these flags.
RTR
Document #: 38-06004 Rev. *B
Page 14 of 22
CY7C4255
CY7C4265
operation. When the LD pin is set LOW, and WEN is LOW, the next
offset register in sequence is written.
Architecture
The CY7C4256/65 consists of an array of 8K/16K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK,
REN, WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C4255/65 also includes the control signals WXI, RXI, WXO,
RXO for depth expansion.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then, data
can be read on the LOW-to-HIGH transition of the Read Clock
(RCLK).
Table 1. Write Offset Register
LD WEN WCLK[37]
Selection
Resetting the FIFO
0
0
Writing to offset registers:
Empty Offset
Full Offset
Upon power-up, the FIFO must be reset with a Reset (RS)
cycle. This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of RS
only if OE is asserted. In order for the FIFO to reset to its default state,
a falling edge must occur on RS and the user must not read or write
while RS is LOW.
0
1
1
1
0
1
No Operation
Write Into FIFO
No Operation
FIFO Operation
When the WEN signal is active (LOW), data present on the D0–17
pins is written into the FIFO on each rising edge of the WCLK signal.
Similarly, when the REN signal is active LOW, data in the FIFO mem-
ory will be presented on the Q0–17 outputs. New data will be present-
ed on each rising edge of RCLK while REN is active LOW and OE is
LOW. REN must set up tENS before RCLK for it to be a valid read
function. WEN must occur tENS before WCLK for it to be a valid write
function.
Flag Operation
The CY7C4255/65 devices provide five flag pins to indicate
the condition of the FIFO contents. Empty and Full are syn-
chronous. PAE and PAF are synchronous if VCC/SMODE is tied to
An output enable (OE) pin is provided to three-state the Q0–17
outputs when OE is deasserted. When OE is enabled (LOW), data in
the output register will be available to the Q0–17 outputs after tOE. If
devices are cascaded, the OE function will only output data on the
FIFO that is read enabled.
VSS
.
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write operations
are inhibited whenever FF is LOW regardless of the state of WEN.
FF is synchronized to WCLK, i.e., it is exclusively updated by each
rising edge of WCLK.
The FIFO contains overflow circuitry to disallow additional
writes when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q0–17 outputs
even after additional reads occur.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the state
of REN. EF is synchronized to RCLK, i.e., it is exclusively updated by
each rising edge of RCLK.
Programming
The CY7C4255/65 devices contain two 14-bit offset registers.
Data present on D0–13 during a program write will determine the
distance from Empty (Full) that the Almost Empty (Almost Full) flags
become active. If the user elects not to program the FIFO’s flags, the
default offset values are used (see Table 2). When the Load LD pin
is set LOW and WEN is set LOW, data on the inputs D0–13 is written
into the Empty offset register on the first LOW-to-HIGH transition of
the Write Clock (WCLK). When the LD pin and WEN are held LOW
then data is written into the Full offset register on the second
LOW-to-HIGH transition of the Write Clock (WCLK). The third transi-
tion of the Write Clock (WCLK) again writes to the Empty offset reg-
ister (see Table 1). Writing all offset registers does not have to occur
at one time. One or two offset registers can be written and then, by
bringing the LD pin HIGH, the FIFO is returned to normal read/write
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65 features programmable Almost Empty and
Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the cor-
responding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE will be asserted, signifying that
the FIFO is either Almost Full or Almost Empty. See Table 2 for a
description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transition is
causedby therisingedgeofthewriteclock andthePAE flag transition
is caused by the rising edge of the read clock.
Notes:
37. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
Document #: 38-06004 Rev. *B
Page 15 of 22
CY7C4255
CY7C4265
nal read pointer to the first physical location of the FIFO. WCLK and
RCLK may be free running but must be disabled during and tRTR
after the retransmit pulse. With every valid read cycle after retransmit,
previously accessed data is read and the read pointer is incremented
until it is equal to the write pointer. Flags are governed by the relative
locations of the read and write pointers and are updated during a
retransmit cycle. Data written to the FIFO after activation of RT are
transmitted also.
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the stand-alone and
width expansion modes. The retransmit feature is intended for
use when a number of writes equal to or less than the depth
of the FIFO have occurred and at least one word has been
read since the last RS cycle. A HIGH pulse on RT resets the inter-
The full depth of the FIFO can be repeatedly retransmitted.
Table 2. Flag Truth Table
Number of Words in FIFO
CY7C4255 – 8K x 18
CY7C4265 – 16K x 18
FF
H
H
H
H
H
L
PAF
H
HF
H
H
H
L
PAE
L
EF
L
0
0
1 to n[38]
1 to n[38]
H
L
H
H
H
H
H
(n+1) to 4096
(n+1) to 8192
8193 to (16384 –(m+1))
(16384–m)[39] to 16383
16384
H
H
4097 to (8192–(m+1))
(8192–m)[39] to 8191
H
H
L
L
H
8192
L
L
H
Notes:
38. n = Empty Offset (Default Values: CY7C4255/CY7C4265 n = 127).
39. m = Full Offset (Default Values: CY7C4255/CY7C4265 n = 127).
Document #: 38-06004 Rev. *B
Page 16 of 22
CY7C4255
CY7C4265
the Empty (Full) flags of every FIFO; the PAE and PAF flags
can be detected from any one device. This technique will avoid
reading data from, or writing data to the FIFO that is “stag-
gered” by one clock cycle due to the variations in skew be-
tween RCLK and WCLK. Figure 1 demonstrates a 36-word width
by using two CY7C4255/65s.
Width Expansion Configuration
The CY7C4255/65 can be expanded in width to provide word
widths greater than 18 in increments of 18. During width ex-
pansion mode all control line inputs are common and all flags
are available. Empty (Full) flags should be created by ANDing
RESET(RS)
RESET(RS)
DATA IN (D)
36
18
18
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
LOAD (LD)
PROGRAMMABLE(PAE)
HALF FULL FLAG (HF)
7C4255
7C4265
PROGRAMMABLE (PAF)
7C4255
7C4265
EMPTY FLAG (EF)
EF
FF
FF
EF
DATA OUT (Q)
18
36
FULL FLAG (FF)
18
FIRST LOAD (FL)
WRITE EXPANSION IN (WXI)
READ EXPANSION IN (RXI)
4255–24
Figure 1. Block Diagram of 8K x18/16K x 18 Synchronous FIFO Memory Used in a Width Expansion Configuration
Document #: 38-06004 Rev. *B
Page 17 of 22
CY7C4255
CY7C4265
3. The Write Expansion Out (WXO) pin of each device must be
tied to the Write Expansion In (WXI) pin of the next device.
Depth Expansion Configuration
(with Programmable Flags)
4. The Read Expansion Out (RXO) pin of each device must be
tied to the Read Expansion In (RXI) pin of the next device.
The CY7C4255/65 can easily be adapted to applications re-
quiring more than 8192/16384 words of buffering. Figure 2
shows Depth Expansion using three CY7C42X5s. Maximum depth
is limited only by signal loading. Follow these steps:
5. All Load (LD) pins are tied together.
6. The Half-Full Flag (HF) is not available in the Depth Expansion
Configuration.
1. The first device must be designated by grounding the First
Load (FL) control input.
7. EF, FF, PAE, and PAF are created with composite flags by
ORing together these respective flags for monitoring. The
composite PAE and PAF flags are not precise.
2. All other devices must have FL in the HIGH state.
WXO RXO
7C4255
7C4265
VCC
FL
FF
PAF
EF
PAE
WXI RXI
WXO RXO
7C4255
7C4265
DATA IN(D)
DATA OUT (Q)
VCC
FL
FF
PAF
EF
PAE
WXI RXI
WRITE CLOCK(WCLK)
WRITE ENABLE(WEN)
READ CLOCK(RCLK)
READ ENABLE(REN)
WXO RXO
7C4255
7C4265
RESET(RS)
OUTPUT ENABLE(OE)
LOAD (LD)
FF
EF
FF
EF
PAE
PAE
PAF
PAF
WXI RXI
FIRST LOAD (FL)
4255–25
Figure 2. Block Diagram of 8Kx18/16Kx18 Synchronous FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
Document #: 38-06004 Rev. *B
Page 18 of 22
CY7C4255
CY7C4265
Typical AC and DC Characteristics
NORMALIZED t vs. AMBIENT
TEMPERATURE
A
NORMALIZED t vs. SUPPLY
VOLTAGE
A
1.20
1.60
1.40
1.20
1.00
0.80
0.60
1.10
1.00
0.90
0.80
T = 25°C
V
CC
= 5.0V
5.00
A
4.00
4.50
5.00
5.50
6.00
−55.00
65.00
125.00
AMBIENT TEMPERATURE( C)
°
SUPPLY VOLTAGE (V)
NORMALIZED SUPPLY
vs. FREQUENCY
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
CURRENT
1.40
1.20
1.75
1.50
1.25
1.00
0.75
0.50
1.20
1.00
0.80
0.60
1.10
1.00
0.90
0.80
V
= 3.0V
V
= 3.0V
V =5.0V
CC
IN
IN
V
= 5.0V
T = 25°C
CC
A
T = 25°C
f = 28 MHz
f = 28 MHz
A
V
= 3.0V
IN
4.00
4.50
5.00
5.50
6.00
−55.00
5.00
65.00
125.00
20.00 30.00 40.00 50.00
FREQUENCY (MHz)
60.00
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE ( C)
°
Document #: 38-06004 Rev. *B
Page 19 of 22
CY7C4255
CY7C4265
Ordering Information
8Kx18 Deep Sync FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4255–10AC
CY7C4255-10ASC
CY7C4255–15AC
A65
A64
A65
64-Lead Thin Quad Flatpack
64-Lead Small Thin Quad Flatpack
64-Lead Thin Quad Flatpack
Commercial
15
Commercial
16Kx18 Deep Sync FIFO
Speed
Package
Name
Package
Type
Operating
Range
(ns)
Ordering Code
10
CY7C4265–10AC
CY7C4265-10ASC
CY7C4265–10AI
CY7C4265–15AC
CY7C4265-15ASC
A65
A64
A65
A65
A64
64-Lead Thin Quad Flatpack
64-Lead Small Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Thin Quad Flatpack
64-Lead Small Thin Quad Flatpack
Commercial
Industrial
15
Commercial
Package Diagrams
64-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.4 mm) A64
51-85051-A
Document #: 38-06004 Rev. *B
Page 20 of 22
CY7C4255
CY7C4265
Package Diagrams (continued)
64-Lead Thin Plastic Quad Flat Pack (14 x 14 x 1.4 mm) A65
51-85046-B
Document #: 38-06004 Rev. *B
Page 21 of 22
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C4255
CY7C4265
Document Title: CY7C4255, CY7C4265 8K/16K X 18 Deep Sync FIFOs
Document Number: 38-06004
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
106465
122257
252889
07/11/01
SZV
RBI
Change from Spec Number: 38-00468 to 38-06004
*A
*B
12/26/02
See ECN
Power up requirements added to Maximum Ratings Information
Removed PLCC package and pruned parts from Order Information
YDT
Document #: 38-06004 Rev. *B
Page 22 of 22
相关型号：
CY7C4265V-15ASCT
FIFO, 16KX18, 10ns, Synchronous, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, STQFP-64
CYPRESS
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