CYBLE-202007-01 [CYPRESS]
Telecom Circuit,;
| 型号： | CYBLE-202007-01 |
| 厂家： | 
CYPRESS |
| 描述： | Telecom Circuit, 电信 电信集成电路 |
| 文件： | 总39页 (文件大小：964K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
EZ-BLE™ PRoC™ XR Module
■ TX current consumption
❐ BLE silicon: 15.6 mA (radio only, 0 dbm)
❐ RFX2401C: 27 mA (PA/LNA only, +7.5 dBm)
General Description
The CYBLE-2X20XX-X1 is a Bluetooth Low Energy (BLE)
wireless module solution. The CYBLE-2X20XX-X1 is a turnkey
solution and includes onboard crystal oscillators, passive
components, and the Cypress PRoC™ BLE. Refer to the
CYBL1XX7X datasheet for additional details on the capabilities
of the PRoC BLE device used on this module.
■ RX current consumption
❐ BLE silicon: 16.4 mA (radio only, 0 dbm)
❐ RFX2401C: 8.0 mA (PA/LNA only)
■ Cypress CYBL1XX7X silicon low power mode support
❐ Deep Sleep: 1.3 A with watch crystal oscillator (WCO) on
❐ Hibernate: 150 nA with SRAM retention
The CYBLE-2X20XX-X1 supports a number of peripheral
functions (ADC, timers, counters, PWM) and serial
communication protocols (I2C, UART, SPI) through its
programmable architecture. The CYBLE-2X20XX-X1 includes a
royalty-free BLE stack compatible with Bluetooth 4.2 and
provides up to 19 GPIOs in a 15.0 × 23.0 × 2.0 mm package.
❐ Stop: 60 nA with XRES wakeup
Functional Capabilities
■ Up to 18 capacitive sensors for buttons or sliders
The CYBLE-2X20XX-X1 is offered in two certified versions
(CYBLE-212006-01 and CYBLE-202007-01), as well as an
uncertified version (CYBLE-202013-11). The CYBLE-212006-01
includes an integrated trace antenna. The CYBLE-202007-01
supports an external antenna via a u-FL connector. The
CYBLE-202013-11 supports an external antenna through a RF
solder pad output. The CYBLE-202013-11 does not include a RF
shield and is not regulatory certified.
■ 12-bit, 1-Msps SAR ADC with internal reference,
sample-and-hold (S/H), and channel sequencer
■ Two serial communication blocks (SCBs) supporting I2C
(master/slave), SPI (master/slave), or UART
■ Four dedicated 16-bit timer, counter, or PWM blocks
(TCPWMs)
Module Description
■ LCD drive supported on all GPIOs (common or segment)
■ Programmable low voltage detect (LVD) from 1.8 V to 3.6 V
■ I2S master interface
■ Module size: 15.00 mm × 23.00 mm × 2.00 mm
■ Extended Range:
❐ Up to 400 meters bi-directional communication[1,2]
❐ Up to 450 meters in beacon only mode[1]
■ BLE protocol stack supporting generic access profile (GAP)
Central, Peripheral, Observer, or Broadcaster roles
■ Bluetooth 4.2 qualified single-mode module
❐ QDID: 88957
❐ Declaration ID: D032786
■ Switches between Central and Peripheral roles on-the-go
■ Standard BLE profiles and services for interoperability
■ Custom profile and service for specific use cases
■ Footprint compatible options for integrated antenna or
antenna-less design options
Benefits
■ Certified to FCC, IC, MIC, KC, and CE regulations
(CYBLE-212006-01 and CYBLE-202007-01 only)
CYBLE-2X20XX-X1 is provided as a turnkey solution, including
all necessary hardware required to use BLE communication
standards.
■ Castelated solder pad connections for ease-of-use
■ 256-KB flash memory, 32-KB SRAM memory
■ Up to 19 GPIOs
■ Proven hardware design ready to use
■ Cost optimized for applications without space constraint
■ Reprogrammable architecture
■ Industrial temperature range: –40 °C to +85 °C
■ 32-bit processor (0.9 DMIPS/MHz) operating up to 48 MHz
■ Watchdog timer with dedicated internal low-speed oscillator
■ Fully certified module eliminates the time needed for design,
development and certification
■ Bluetooth SIG qualified with QDID and Declaration ID
■ Flexible communication protocol support
Power Consumption
■ Maximum TX output power: +7.5 dbm
■ RX Receive Sensitivity: –93 dbm
■ PSoC Creator™ provides an easy-to-use integrated design
environment (IDE) to configure, develop, program, and test a
BLE application
■ Received signal strength indicator (RSSI) with 1-dB resolution
Notes
1. Connection range tested module-to-module in full line-of-sight environment, free of obstacles or interference sources with output power of +7.5 dBm.
2. Specified as EZ-BLE XR module to module range. Mobile phone connection range will decrease based on the PA/LNA performance of the mobile phone used.
Cypress Semiconductor Corporation
Document Number: 002-15631 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 22, 2017
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to
quickly and effectively integrate the module into your design.
■ Overview: EZ-BLE Module Portfolio, Module Roadmap
■ EZ-BLE PRoC Product Overview
■ Knowledge Base Articles
❐ KBA212334 - Pin Mapping Differences Between the EZ-BLE
PRoC® Evaluation Boards (CYBLE-212006-EVAL/CY-
BLE-202007-EVAL/CYBLE-202013-EVAL) and the BLE Pi-
oneer Kit (CY8CKIT-042-BLE)
■ PRoC BLE Silicon Datasheet
■ Application notes: Cypress offers a number of BLE application
notes covering a broad range of topics, from basic to advanced
level. Recommended application notes for getting started with
EZ-BLE modules are:
❐ KBA97095 - EZ-BLE™ Module Placement
❐ KBA216380 - RF Regulatory Certifications for CY-
BLE-212006-01 and CYBLE-202007-01 EZ-BLE™ PRoC®
XR Modules
❐ KBA213976 -FAQ for BLE and Regulatory Certifications with
EZ-BLE modules
❐ AN96841 - Getting Started with EZ-BLE Module
❐ AN94020 - Getting Started with PRoC BLE
❐ AN97060 - PSoC® 4 BLE and PRoC™ BLE - Over-The-Air
❐ KBA210802 - Queries on BLE Qualification and Declaration
Processes
(OTA) Device Firmware Upgrade (DFU) Guide
❐ AN91162 - Creating a BLE Custom Profile
❐ AN91184 - PSoC 4 BLE - Designing BLE Applications
■ Development Kits:
❐ AN92584 - Designing for Low Power and Estimating Battery
❐ CYBLE-212006-EVAL, CYBLE-212006-01 Eval Board
❐ CYBLE-202007-EVAL, CYBLE-202007-01 Eval Board
❐ CYBLE-202013-EVAL, CYBLE-202013-11 Eval Board
❐ CY8CKIT-042-BLE, Bluetooth® Low Energy Pioneer Kit
❐ CY8CKIT-002, PSoC® MiniProg3 Program and Debug Kit
Life for BLE Applications
❐ AN85951 - PSoC® 4 CapSense® Design Guide
❐ AN95089 - PSoC® 4/PRoC™ BLE Crystal Oscillator Selec-
tion and Tuning Techniques
❐ AN91445 - Antenna Design and RF Layout Guidelines
■ Test and Debug Tools:
■ Technical Reference Manual (TRM):
❐ PRoC® BLE Technical Reference Manual
❐ PRoC Programming Specifications
❐ CYSmart, Bluetooth® LE Test and Debug Tool (Windows)
❐ CYSmart Mobile, Bluetooth® LE Test and Debug Tool
(Android/iOS Mobile App)
Two Easy-To-Use Design Environments to Get You Started Quickly
®
PSoC Creator™ Integrated Design Environment (IDE)
PSoC Creator is an Integrated Design Environment (IDE) that enables concurrent hardware and firmware editing, compiling and
debugging of PSoC 3, PSoC 4, PSoC 5LP, PSoC 4 BLE, PRoC BLE and EZ-BLE module systems with no code size limitations. PSoC
peripherals are designed using schematic capture and simple graphical user interface (GUI) with over 120 pre-verified,
production-ready PSoC Components™.
PSoC Components are analog and digital “virtual chips,” represented by an icon that users can drag-and-drop into a design and
configure to suit a broad array of application requirements.
Bluetooth Low Energy Component
The Bluetooth Low Energy Component inside PSoC Creator provides a comprehensive GUI-based configuration window that lets you
quickly design BLE applications. The Component incorporates a Bluetooth Core Specification v4.2 compliant BLE protocol stack and
provides API functions to enable user applications to interface with the underlying Bluetooth Low Energy Sub-System (BLESS)
hardware via the stack.
EZ-Serial™ BLE Firmware Platform
The EZ-Serial Firmware Platform provides a simple way to access the most common hardware and communication features needed
in BLE applications. EZ-Serial implements an intuitive API protocol over the UART interface and exposes various status and control
signals through the module’s GPIOs, making it easy to add BLE functionality quickly to existing designs.
Use a simple serial terminal and evaluation kit to begin development without requiring an IDE. Refer to the EZ-Serial webpage for
User Manuals and instructions for getting started as well as detailed reference materials.
EZ-BLE modules are pre-flashed with the EZ-Serial Firmware Platform. If you do not have EZ-Serial pre-loaded on your module, you
can download each EZ-BLE module’s firmware images on the EZ-Serial webpage.
Technical Support
■ Frequently Asked Questions (FAQs): Learn more about our BLE ECO System.
■ Forum: See if your question is already answered by fellow developers on the PSoC 4 BLE and PRoC BLE forums.
■ Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States,
you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt.
Document Number: 002-15631 Rev. *E
Page 2 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Contents
Overview ............................................................................4
Module Description ......................................................4
Pad Connection Interface ................................................6
Recommended Host PCB Layout ...................................7
Digital and Analog Capabilities
and Connections ..............................................................9
Power Supply Connections
and Recommended External Components ..................10
Connection Options ...................................................10
External Component Recommendation ....................10
Antenna Matching Network Requirements
Environmental Specifications .......................................30
Environmental Compliance .......................................30
RF Certification ..........................................................30
Safety Certification ....................................................30
Environmental Conditions .........................................30
ESD and EMI Protection ...........................................30
Regulatory Information ..................................................31
FCC ...........................................................................31
Innovation, Science and Economic
Development (ISED) Canada Certification ................32
European Declaration of Conformity .........................33
MIC Japan .................................................................33
KC Korea ...................................................................33
Packaging ........................................................................34
Ordering Information ......................................................36
Part Numbering Convention ......................................36
Acronyms ........................................................................37
Document Conventions .................................................37
Units of Measure .......................................................37
Document History Page .................................................38
Sales, Solutions, and Legal Information ......................39
Worldwide Sales and Design Support .......................39
Products ....................................................................39
PSoC® Solutions ......................................................39
Cypress Developer Community .................................39
Technical Support .....................................................39
for CYBLE-202013-11 ...............................................12
Critical Components List ...........................................14
Antenna Design .........................................................14
Qualified Antenna for CYBLE-202007-01
and CYBLE-202013-11 .............................................14
Power Amplifier (PA)
and Low Noise Amplifier (LNA) .................................14
Enabling Extended Range Feature ...........................15
Low Power Operation ................................................15
Electrical Specification ..................................................16
GPIO .........................................................................18
XRES .........................................................................19
Digital Peripherals .....................................................21
Serial Communication ...............................................23
Memory .....................................................................24
System Resources ....................................................25
Document Number: 002-15631 Rev. *E
Page 3 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Overview
Module Description
The CYBLE-2X20XX-X1 module is a complete module designed to be soldered to the applications main board.
Module Dimensions and Drawing
Cypress reserves the right to select components (including the appropriate BLE device) from various vendors to achieve the BLE
module functionality. Such selections will still guarantee that all height restrictions of the component area are maintained. Designs
should be held within the physical dimensions shown in the mechanical drawings in Figure 1. All dimensions are in millimeters (mm).
Table 1. Module Design Dimensions
Dimension Item
Specification
Length (X) 15.00 ± 0.15 mm
Width (Y) 23.00 ± 0.15 mm
Length (X) 15.00 ± 0.15 mm
Width (Y) 4.65 ± 0.15 mm
Module dimensions
Antenna location dimensions
PCB thickness
Shield height
Height (H) 0.80 ± 0.10 mm
Height (H) 1.20 ± 0.10 mm
1.20 mm typical (shield) - CYBLE-212006-01
Height (H) 1.25 mm typical (connector) - CYBLE-202007-01
0.75mm typical (crystal) - CYBLE-202013-11
Maximum component height
2.00 mm typical - CYBLE-212006-01
Total module thickness (bottom of module to highest component) Height (H) 2.05 mm typical - CYBLE-202007-01
1.55 mm typical - CYBLE-202013-11
See Figure 1 on page 5 for the mechanical reference drawing for CYBLE-2X20XX-X1.
Document Number: 002-15631 Rev. *E
Page 4 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Figure 1. Module Mechanical Drawing
Side View
Top View (View from Top)
Bottom View (Seen from Bottom)
Note
3. No metal or traces should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information
on recommended host PCB layout, see Figure 3, Figure 4, Figure 5 and Figure 6, and Table 3.
Document Number: 002-15631 Rev. *E
Page 5 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Pad Connection Interface
As shown in the bottom view of Figure 1 on page 5, the CYBLE-2X20XX-X1 connects to the host board via solder pads on the backside
of the module. Table 2 and Figure 2 detail the solder pad length, width, and pitch dimensions of the CYBLE-2X20XX-X1 module.
Table 2. Solder Pad Connection Description
Name Connections Connection Type
SP 30 Solder Pads
Pad Length Dimension
Pad Width Dimension
Pad Pitch
1.02 mm
0.71 mm
1.27 mm
Figure 2. Solder Pad Dimensions (Seen from Bottom)
To maximize RF performance, the host layout should follow these recommendations:
1. The ideal placement of the Cypress BLE module is in a corner of the host board with the trace antenna located at the far corner.
This placement minimizes the additional recommended keep out area stated in item 2. Please refer to AN96841 for module
placement best practices.
2. To maximize RF performance, the area immediately around the Cypress BLE module trace antenna should contain an additional
keep out area, where no grounding or signal trace are contained. The keep out area applies to all layers of the host board. The
recommended dimensions of the host PCB keep out area are shown in Figure 3 (dimensions are in mm).
Figure 3. Recommended Host PCB Keep Out Area Around the CYBLE-2X20XX-X1 Antenna
Host PCB Keep Out Area Around Trace Antenna
Document Number: 002-15631 Rev. *E
Page 6 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Recommended Host PCB Layout
Figure 4, Figure 5, Figure 6, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the
CYBLE-212006-01. Dimensions are in millimeters unless otherwise noted. Pad length of 1.27 mm (0.635 mm from center of the pad
on either side) shown in Figure 6 is the minimum recommended host pad length. The host PCB layout pattern can be completed using
either Figure 4, Figure 5, or Figure 6. It is not necessary to use all figures to complete the host PCB layout pattern.
Figure 4. Host Layout Pattern for CYBLE-2X20XX-X1
Figure 5. Module Pad Location from Origin
Top View (Seen on Host PCB)
Top View (Seen on Host PCB)
Document Number: 002-15631 Rev. *E
Page 7 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Table 3 provides the center location for each solder pad on the CYBLE-2X20XX-X1. All dimensions reference the to the center of the
solder pad. Refer to Figure 6 for the location of each module solder pad.
Table 3. Module Solder Pad Location
Figure 6. Solder Pad Reference Location
Solder Pad
(Center of Pad)
Location (X,Y) from
Orign (mm)
Dimension from
Orign (mils)
1
(0.38, 10.54)
(0.38, 11.81)
(0.38, 13.08)
(0.38, 14.35)
(0.38, 15.62)
(0.38, 16.89)
(0.38, 18.16)
(0.38, 19.43)
(0.38, 20.70)
(0.38, 21.97)
(2.32, 22.62)
(3.59, 22.62)
(4.86, 22.62)
(6.13, 22.62)
(7.40, 22.62)
(8.67, 22.62)
(9.94, 22.62)
(11.21, 22.62)
(12.48, 22.62)
(13.75, 22.62)
(14.62, 20.70)
(14.62, 19.43)
(14.62, 18.16)
(14.62, 16.89)
(14.62, 15.62)
(14.62, 14.35)
(14.62, 13.08)
(14.62, 11.81)
See Figure 2
See Figure 2
(14.96, 414.96)
(14.96, 464.96)
(14.96, 514.96)
(14.96, 564.96)
(14.96, 614.96)
(14.96, 664.96)
(14.96, 714.96)
(14.96, 764.96)
(14.96, 814.96)
(14.96, 864.96)
(91.34, 890.55)
(141.34, 890.55)
(191.34, 890.55)
(241.34, 890.55)
(291.34, 890.55)
(341.34, 890.55)
(391.34,8 90.55)
(441.34, 890.55)
(491.34, 890.55)
(541.34, 890.55
(575.59, 814.96)
(575.59, 764.96)
(575.59, 714.96)
(575.59, 664.96)
(575.59, 614.96)
(575.59, 564.96)
(575.59, 514.96)
(575.59, 464.96)
See Figure 2
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Top View (Seen on Host PCB)
See Figure 2
Document Number: 002-15631 Rev. *E
Page 8 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Digital and Analog Capabilities and Connections
Table 4 details the solder pad connection definitions and available functions for each connection pad. Table 4 lists the solder pads on
CYBLE-2X20XX-X1, the BLE device port-pin, and denotes whether the function shown is available for each solder pad. Each
connection is configurable for a single option shown with a ✓.
Table 4. Solder Pad Connection Definitions
SolderPad Device
Number Port Pin
Cap-
Sense
WCO ECO
Out Out
UART
SPI
I2C
TCPWM[4,5]
LCD
SWD
GPIO
1
GND
Ground Connection
2
XRES
External Reset Hardware Connection Input
✓(TCPWM0_P) ✓(CMOD
3
P4.0[6] ✓(SCB1_RTS) ✓(SCB1_MOSI)
)
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
4
P3.7 ✓(SCB1_CTS)
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
✓(Sensor)
✓
✓
5
P3.6 ✓(SCB1_RTS)
✓(Sensor)
✓(Sensor)
✓(Sensor)
6
P3.5
P3.4
VREF
P2.6
P2.4
P2.3
P2.2
P2.0
✓(SCB1_TX)
✓(SCB1_RX)
✓(SCB1_SCL)
7
✓(SCB1_SDA) ✓(TCPWM)
8
Reference Voltage Input (Optional)
9
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
✓(TCPWM)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓(Sensor)
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
✓
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
✓(SCB0_SS3)
✓(SCB0_SS1)
P1.7 ✓(SCB0_CTS) ✓(SCB0_SCLK
P1.6
P1.5
P1.4
✓(SCB0_RTS) ✓(SCB0_SS0)
✓(SCB0_TX) ✓(SCB0_MISO) ✓(SCB0_SCL)
✓(SCB0_RX) ✓(SCB0_MOSI) ✓(SCB0_SDA) ✓(TCPWM)
✓(TCPWM)
P0.7 ✓(SCB0_CTS) ✓(SCB0_SCLK
✓(TCPWM)
✓(TCPWM)
✓(SWDCLK)
✓(SWDIO)
P1.0
P0.4
✓(SCB0_RX) ✓(SCB0_MOSI) ✓(SCB0_SDA) ✓(TCPWM)
✓(SCB0_TX) ✓(SCB0_MISO) ✓(SCB0_SCL) ✓(TCPWM)
✓
P0.5
VDD
Digital Power Supply Input (1.71 to 3.6V)
✓(TCPWM) ✓(Sensor)
P0.6 ✓(SCB0_RTS) ✓(SCB0_SS0)
✓
✓
GND[7]
GND
GND
GND
VDDR
Ground Connection
Ground Connection
Ground Connection
Ground Connection
Radio Power Supply (2.0V to 3.6V)
GND
RF Ground Connection for use with CYBLE-202013-11 only; No Connect for CYBLE-212006-01 and CYBLE-202007-01
ANT RF Pin to External Antenna for use with CYBLE-202013-11 only; No Connect for CYBLE-212006-01 and CYBLE-202007-01
Notes
4. TCPWM: Timer, Counter, and Pulse Width Modulator. If supported, the pad can be configured to any of these peripheral functions.
5. TCPWM connections on ports 0, 1, 2, and 3 can be routed through the Digital Signal Interconnect (DSI) to any of the TCPWM blocks and can be either positive
or negative polarity. TCPWM connections on port 4 are direct and can only be used with the specified TCPWM block and polarity specified above.
6. When using the capacitive sensing functionality, Pad 3 (P4.0) must be connected to a C
capacitor is 2.2 nF and should be placed as close to the module as possible.
capacitor (located off of Cypress BLE Module). The value of this
MOD
7. The main board needs to connect all GND connections (Pad 24/25/26/27) on the module to the common ground of the system.
2
2
8. If the I S feature is used in the design, the I S pins shall be dynamically routed to the appropriate available GPIO by PSoC Creator.
Document Number: 002-15631 Rev. *E
Page 9 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Power Supply Connections and Recommended External Components
Power Connections
External Component Recommendation
The CYBLE-2X20XX-X1 contains two power supply connec-
tions, VDD and VDDR. The VDD connection supplies power for
both digital and analog device operation. The VDDR connection
supplies power for the device radio.
In either connection scenario, it is recommended to place an
external ferrite bead between the supply and the module
connection. The ferrite bead should be positioned as close as
possible to the module pin connection.
VDD accepts a supply range of 1.71 V to 3.6 V. VDDR accepts
a supply range of 2.0V to 3.6V. These specifications can be
found in Table 12. The maximum power supply ripple for both
power connections on the module is 100 mV, as shown in
Table 10.
Figure 7 details the recommended host schematic options for a
single supply scenario. The use of one or two ferrite beads will
depend on the specific application and configuration of the
CYBLE-2X20XX-X1.
Figure 8 details the recommended host schematic for an
independent supply scenario.
The power supply ramp rate of VDD must be equal to or greater
than that of VDDR.
The recommended ferrite bead value is 330 , 100 MHz. (Murata
BLM21PG331SN1D).
Connection Options
Two connection options are available for any application:
1. Single supply: Connect VDD and VDDR to the same supply.
2. Independent supply: Power VDD and VDDR separately.
Figure 7. Recommended Host Schematic Options for a Single Supply Option
Single Ferrite Bead Option (Seen from Bottom)
Two Ferrite Bead Option (Seen from Bottom)
Document Number: 002-15631 Rev. *E
Page 10 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Figure 8. Recommended Host Schematic for an Independent Supply Option
Independent Power Supply Option (Seen from Bottom)
Document Number: 002-15631 Rev. *E
Page 11 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Antenna Matching Network Requirements for CYBLE-202013-11
The CYBLE-202013-11 module requires ANT and GND connections to an external antenna via the RF pad connections on the module
(Pads 29 and 30). In order to optimize RF performance, an Antenna Matching Network (AMN) is required to be placed between the
ANT connection (Pad 29) and the antenna used in the final design. Figure 9 details the recommended Pi topology circuit footprint to
use for the Antenna Matching Network.
Figure 9. Recommended Antenna Matching Network for CYBLE-202013-11 Module
Module Pad Assignments Seen from Bottom View
The design guidelines that should be followed when completing the Antenna Matching Network are as follows:
■ The AMN should be placed close to the antenna on the main board.
■ Routing to the AMN from the ANT pad on the module must be controlled to an impedance of 50.
■ The final AMN circuit may contain only a single component, or all three components shown above. The final number and type of
components will be determined based on the actual design of the system, and the final values for each component can be determined
through tuning the AMN. For details on how to properly tune an AMN, please refer to Application Note AN91445.
Document Number: 002-15631 Rev. *E
Page 12 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
The CYBLE-2X20XX-X1 schematic is shown in Figure 10.
Figure 10. CYBLE-2X20XX-X1 Schematic Diagram
Document Number: 002-15631 Rev. *E
Page 13 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Critical Components List
Table 5 details the critical components used in the CYBLE-2X20XX-X1 module.
Table 5. Critical Component List
Component
Reference Designator
Description
Silicon
Crystal
Crystal
U1
Y1
Y2
56-pin QFN Programmable Radio-on-Chip (PRoC) with BLE
24.000 MHz, 12PF
32.768 kHz, 12.5PF
Antenna Design
Table 6 details trace antenna used in the CYBLE-212006-01 module. For more information, see Table 11.
Table 6. Trace Antenna Specifications
Item
Description
Frequency Range
Peak Gain
2402 – 2480 MHz
–0.5 dBi typical
10 dB minimum
Return Loss
Qualified Antenna for CYBLE-202007-01 and CYBLE-202013-11
The CYBLE-202007-01 module has been designed to work with a standard 2.2 dBi dipole antenna. Any antenna of equivalent or less
gain can be used without additional application and testing for FCC regulations. Table 7 details the approved antennas for the
CYBLE-202007-01 module for BLE operation. These antennas may also be used for the CYBLE-202013-11 module, however all FCC
and other regulatory testing will be required.
Table 7. Qualified Antenna
Manufacturer
Antenova
RFlink
Part Number
B4844-01
Gain
2.2 dBi
2.0 dBi
2.0 dBi
RF21C01228A
W1030
Pulse
Power Amplifier (PA) and Low Noise Amplifier (LNA)
Table 8 details the PA/LNA that is used on the CYBLE-2X20XX-X1 module. For more information, see Table 11.
Table 8. Power Amplifier/Low Noise Amplifier Details
Item
Description
PA/LNA Manufacturer
PA/LNA Part Number
Power Supply Range
Skyworks Inc.
RFX2401C
2.0V to 3.6V
Table 9 details the power consumption of the integrated PA/LNA used on the CYBLE-2X20XX-X1 module. Table 9 only details the
current consumption of the RFX2401C PA/LNA. VDD= 3.3 V, TA = +25°C, measured on the RFX2401C evaluation board, unless
otherwise noted.
Table 9. Power Amplifier/Low Noise Amplifier Current Consumption Specifications
Parameter
Test Condition
Pout = +20dBm
No RF applied
No RF applied
Min
Typical
Max
Unit
mA
mA
mA
Tx High Power Current
Tx Quiescent Current
Rx Quiescent Current
90
17
8
Document Number: 002-15631 Rev. *E
Page 14 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Enabling Extended Range Feature
The CYBLE-2X20XX-X1 modules come with an integrated Power Amplifier/Low Noise Amplifier to allow for extended communication
range of up to 400 meters full line-of-sight. This section describes the firmware steps required to enable extended range operation of
the CYBLE-2X20XX-X1 modules. The CYBLE-2X20XX-X1 is designed to provide extended range functionality, and the PA/LNA of
the module cannot be operated in bypass mode. The minimum output power configuration available for the CYBLE-2X20XX-X1 is
+1 dBm, which is configurable via silicon internal output power settings.
The Skyworks RFX2401C PA/LNA is controlled by PRoC BLE and uses two GPIOs:
1.One GPIO to control the PA enable (P3[2]). The PA enable GPIO is controlled directly by the BLE Link Layer.
2.One GPIO to control the LNA enable (P3[3]). The LNA enable GPIO is controlled directly by the BLE Link Layer.
Ensure that the PRoC® BLE silicon device “Adv/Scan TX Power Level (dBm)” and “Connection TX Power Level (dBm)” in the BLE
Component are both set to -12 dBm[9]
To enable the extended range functionality, follow the steps outlined below:
1.Open your project’s main.c file and write the below code to define the register at the top of the code.
/* define the test register to switch the PA/LNA hardware control pins */
#define CYREG_SRSS_TST_DDFT_CTRL 0x40030008
2.Locate/add the event “CYBLE_EVT_STACK_ON" in the application code and insert the below two lines of code to enable the
Skyworks RFX2401C.
/* Mandatory events to be handled by BLE application code */
case CYBLE_EVT_STACK_ON:
/* Configure the Link Layer to automatically switch PA control pin P3[2] and LNA control pin P3[3] */
CY_SET_XTND_REG32((void CYFAR *)(CYREG_BLE_BLESS_RF_CONFIG), 0x0331);
CY_SET_XTND_REG32((void CYFAR *)(CYREG_SRSS_TST_DDFT_CTRL), 0x80000302);
Low Power Operation
The CYBLE-2X20XX-X1 module is already optimized for low power operation when in high output power, high gain mode. The Cypress
BLE Link Layer will automatically enable TX high power operation, as well as RX high gain operation. When the radio TX or RX
operation is not in use (i.e. sleep), the PA/LNA will be set to shutdown mode by the BLE Link Layer. This will occur during sleep modes
of the Cypress PRoC BLE silicon device.
To learn more about optimize the Cypress PRoC BLE power consumption, refer to AN92584: Designing for Low Power and Estimating
Battery Life for BLE Applications.
Note
9. The CYBLE-212006-01 module is certified for FCC, IC, CE, MIC and KC regulations at an output power of +7.5 dBm. To achieve this output power, RF
O2
(PRoC BLE silicon PA level) must be set to the -12 dBm setting in firmware. Settings higher than this will result in higher output power than specified in the
CYBLE-212006-01 certifications.
Document Number: 002-15631 Rev. *E
Page 15 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Electrical Specification
Table 10 details the absolute maximum electrical characteristics for the Cypress BLE module.
Table 10. CYBLE-2X20XX-X1 Absolute Maximum Ratings
Parameter
VDDD_ABS
Description
Min
–0.5
–0.5
Typ
–
Max
3.6
Units
Details/Conditions
Analog, digital, or radio supply relative to VSS
V
V
Absolute maximum
(VSSD = VSSA
)
VCCD_ABS
Direct digital core voltage input relative to VSSD
–
1.95
Absolute maximum
3.0V supply
Maximum power supply ripple for VDD and VDDR
input voltage
VDD_RIPPLE
–
–
100
mV Ripple frequency of 100 kHz
to 750 kHz
VGPIO_ABS
IGPIO_ABS
GPIO voltage
–0.5
–25
–
–
VDD +0.5
25
V
Absolute maximum
Maximum current per GPIO
mA Absolute maximum
GPIO injection current: Maximum for VIH > VDD
and minimum for VIL < VSS
Absolute maximum current
injected per pin
IGPIO_injection
LU
–0.5
–
0.5
mA
Pin current for latch up
–200
200
mA
–
Table 11 details the RF characteristics for the Cypress BLE module.
Table 11. CYBLE-2X20XX-X1 RF Performance Characteristics
Parameter
RFO
Description
RF output power on ANT
Min
Typ
Max
Units
Details/Conditions
Configurable via silicon
1
7.5
dBm register settings
DD = 3.3 V
V
Measured value
(CYBLE-212006-01)
RXS
RF receive sensitivity on ANT
–
–93
–
dBm
FR
GP
RL
Module frequency range
Peak gain
2402
–
2480
MHz
dBi
dB
–
–
–
–
–
–0.5
–10
–
–
Return loss
Table 12 through Table 52 list the module level electrical characteristics for the CYBLE-2X20XX-X1. All specifications are valid for
–40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 3.6 V, except where noted.
Table 12. CYBLE-2X20XX-X1 DC Specifications
Parameter
VDD1
Description
Power supply input voltage
Min
Typ
Max
Units
Details/Conditions
1.8
–
3.6
V
With regulator enabled
Internally unregulated
supply
VDD2
Power supply input voltage unregulated (VDD)
1.71
1.8
1.89
V
VDDR1
VDDR2
Radio supply voltage (radio on)
Radio supply voltage (radio off)
2.0
2.0
–
–
3.6
3.6
V
V
Restricted by RFX2401C
–
Active Mode, VDD = 1.71 V to 3.6 V
T = 25 °C,
VDD = 3.3 V
IDD3
IDD4
IDD5
IDD6
IDD7
Execute from flash; CPU at 3 MHz
–
–
–
–
–
1.7
–
–
–
–
–
–
mA
Execute from flash; CPU at 3 MHz
Execute from flash; CPU at 6 MHz
Execute from flash; CPU at 6 MHz
Execute from flash; CPU at 12 MHz
mA T = –40 °C to 85 °C
T = 25 °C,
mA
2.5
–
VDD = 3.3 V
mA T = –40 °C to 85 °C
T = 25 °C,
mA
4
VDD = 3.3 V
Document Number: 002-15631 Rev. *E
Page 16 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Table 12. CYBLE-2X20XX-X1 DC Specifications (continued)
Parameter
IDD8
Description
Min
Typ
Max
Units
Details/Conditions
Execute from flash; CPU at 12 MHz
–
–
–
mA T = –40 °C to 85 °C
T = 25 °C,
mA
IDD9
Execute from flash; CPU at 24 MHz
Execute from flash; CPU at 24 MHz
Execute from flash; CPU at 48 MHz
Execute from flash; CPU at 48 MHz
–
–
–
–
7.1
–
–
–
–
–
V
DD = 3.3 V
IDD10
IDD11
IDD12
mA T = –40 °C to 85 °C
T = 25 °C,
mA
13.4
–
VDD = 3.3 V
mA T = –40 °C to 85 °C
Sleep Mode, VDD = 1.8 to 3.6 V
IDD13 IMO on
Sleep Mode, VDD and VDDR = 2.0 to 3.6 V
IDD14 ECO on
Deep-Sleep Mode, VDD = 1.8 to 3.6 V
T = 25 °C, VDD = 3.3 V,
mA
–
–
–
–
–
–
SYSCLK = 3 MHz
T = 25 °C, VDD = 3.3 V,
mA
SYSCLK = 3 MHz
T = 25 °C,
A
IDD15
IDD16
IDD17
IDD18
WDT with WCO on
WDT with WCO on
WDT with WCO on
WDT with WCO on
–
–
–
–
1.5
–
–
–
–
–
VDD = 3.3 V
A T = –40 °C to 85 °C
T = 25 °C,
–
A
VDD = 5 V
–
A T = –40 °C to 85 °C
Deep-Sleep Mode, VDD = 1.71 to 1.89 V (Regulator Bypassed)
IDD19
IDD20
WDT with WCO on
WDT with WCO on
–
–
–
–
–
–
A T = 25 °C
A T = –40 °C to 85 °C
Hibernate Mode, VDD = 1.8 to 3.6 V
T = 25 °C,
nA
IDD27
IDD28
GPIO and reset active
–
–
150
–
–
–
VDD = 3.3 V
GPIO and reset active
nA T = –40 °C to 85 °C
Stop Mode, VDD = 1.8 to 3.6 V
T = 25 °C,
nA
IDD33
Stop-mode current (VDD
)
–
20
–
VDD = 3.3 V
T = 25 °C,
nA
IDD34
IDD35
IDD36
Stop-mode current (VDDR
)
)
–
–
–
40
–
–-
–
VDDR = 3.3 V
Stop-mode current (VDD
)
nA T = –40 °C to 85 °C
T = –40 °C to 85 °C,
nA
Stop-mode current (VDDR
–
–
VDDR = 2.0 V to 3.6 V
Table 13. AC Specifications
Parameter
Description
Min
DC
–
Typ
Max
Units
Details/Conditions
FCPU
CPU frequency
–
0
48
–
MHz 1.71 V VDD 3.6 V
TSLEEP
Wakeup from Sleep mode
s
s
Guaranteed by characterization
24-MHz IMO. Guaranteed by
characterization
TDEEPSLEEP
Wakeup from Deep-Sleep mode
–
–
25
THIBERNATE
TSTOP
Wakeup from Hibernate mode
Wakeup from Stop mode
–
–
–
–
2
2
ms
ms
Guaranteed by characterization
XRES wakeup
Document Number: 002-15631 Rev. *E
Page 17 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
GPIO
Table 14. GPIO DC Specifications
Parameter
Description
Min
Typ
–
Max
Units
V
Details/Conditions
Input voltage HIGH threshold
LVTTL input, VDD < 2.7 V
LVTTL input, VDD 2.7 V
Input voltage LOW threshold
LVTTL input, VDD < 2.7 V
LVTTL input, VDD 2.7 V
Output voltage HIGH level
Output voltage HIGH level
Output voltage LOW level
Output voltage LOW level
Pull-up resistor
0.7 × VDD
–
CMOS input
[10]
VIH
0.7 × VDD
–
–
V
–
–
2.0
–
–
V
–
–
0.3× VDD
V
CMOS input
VIL
–
–
–
0.3× VDD
V
–
–
–
0.8
–
V
VDD –0.6
–
V
IOH = 4 mA at 3.3-V VDD
VOH
VOL
V
DD –0.5
–
–
V
IOH = 1 mA at 1.8-V VDD
–
–
–
0.6
0.6
8.5
8.5
2
V
IOL = 8 mA at 3.3-V VDD
–
V
IOL = 4 mA at 1.8-V VDD
RPULLUP
RPULLDOWN
IIL
3.5
3.5
–
5.6
5.6
–
k
k
nA
nA
pF
mV
1
–
Pull-down resistor
–
Input leakage current (absolute value)
Input leakage on CTBm input pins
Input capacitance
25 °C, VDD = 3.3 V
IIL_CTBM
CIN
VHYSTTL
VHYSCMOS
–
–
4
–
–
–
7
–
Input hysteresis LVTTL
25
40
–
–
VDD > 2.7 V
–
Input hysteresis CMOS
0.05 × VDD
–
Current through protection diode to
IDIODE
–
–
–
100
200
A
–
–
VDD/VSS
Maximum total source or sink chip
current
ITOT_GPIO
–
mA
Table 15. GPIO AC Specifications
Parameter Description
TRISEF
Min
2
Typ
Max
12
Units
Details/Conditions
3.3-V VDDD, CLOAD = 25 pF
3.3-V VDDD, CLOAD = 25 pF
3.3-V VDDD, CLOAD = 25 pF
3.3-V VDDD, CLOAD = 25 pF
Rise time in Fast-Strong mode
Fall time in Fast-Strong mode
Rise time in Slow-Strong mode
Fall time in Slow-Strong mode
–
–
–
–
ns
ns
ns
ns
TFALLF
TRISES
TFALLS
2
12
10
10
60
60
GPIO Fout; 3.3 V VDD 5.5 V
90/10%, 25 pF load, 60/40 duty
cycle
FGPIOUT1
FGPIOUT2
FGPIOUT3
FGPIOUT4
FGPIOIN
–
–
–
–
–
–
–
–
–
–
33
16.7
7
MHz
MHz
MHz
MHz
Fast-Strong mode
GPIO Fout; 1.7 VVDD 3.3 V
Fast-Strong mode
90/10%, 25 pF load, 60/40 duty
cycle
GPIO Fout; 3.3 V VDD 5.5 V
Slow-Strong mode
90/10%, 25 pF load, 60/40 duty
cycle
GPIO Fout; 1.7 V VDD 3.3 V
Slow-Strong mode
90/10%, 25 pF load, 60/40 duty
cycle
3.5
48
GPIO input operating frequency
1.71 V VDD 5.5 V
MHz 90/10% VIO
Note
10. V must not exceed V + 0.2 V.
IH
DD
Document Number: 002-15631 Rev. *E
Page 18 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Table 16. OVT GPIO DC Specifications (P5_0 and P5_1 Only)
Parameter
Description
Min
–
Typ
–
Max
10
Units
A
V
Details/Conditions
25°C, VDD = 0 V, VIH = 3.0 V
IOL = 20 mA, VDD > 2.9 V
Input leakage (absolute value).
VIH > VDD
IIL
VOL
Output voltage LOW level
–
–
0.4
Table 17. OVT GPIO AC Specifications (P5_0 and P5_1 Only)
Parameter
TRISE_OVFS
TFALL_OVFS
TRISESS
Description
Min
1.5
1.5
10
Typ
–
Max
12
Units
ns
Details/Conditions
Output rise time in Fast-Strong mode
Output fall time in Fast-Strong mode
Output rise time in Slow-Strong mode
Output fall time in Slow-Strong mode
25-pF load, 10%–90%, VDD = 3.3 V
25-pF load, 10%–90%, VDD = 3.3 V
25 pF load, 10%-90%, VDD = 3.3 V
25 pF load, 10%-90%, VDD = 3.3 V
–
12
ns
–
60
ns
TFALLSS
10
–
60
ns
GPIO FOUT; 3.3 V VDD 3.6 V
FGPIOUT1
FGPIOUT2
–
–
–
–
24
16
MHz 90/10%, 25 pF load, 60/40 duty cycle
MHz 90/10%, 25 pF load, 60/40 duty cycle
Fast-Strong mode
GPIO FOUT; 1.71 V VDD 3.3 V
Fast-Strong mode
XRES
Table 18. XRES DC Specifications
Parameter Description
VIH
Min
Typ
–
Max
Units
V
Details/Conditions
CMOS input
CMOS input
Input voltage HIGH threshold
Input voltage LOW threshold
Pull-up resistor
0.7 × VDDD
–
VIL
–
3.5
–
–
0.3 × VDDD
V
RPULLUP
CIN
5.6
3
8.5
–
k
pF
–
–
–
Input capacitance
VHYSXRES
Input voltage hysteresis
Current through protection diode to
–
100
–
mV
IDIODE
–
–
100
A
–
VDD/VSS
Table 19. XRES AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
TRESETWIDTH Reset pulse width
1
–
–
s
–
Temperature Sensor
Table 20. Temperature Sensor Specifications
Parameter
TSENSACC
Description
Min
–5
Typ
Max
Units
°C
Details/Conditions
–40 °C to +85 °C
Temperature-sensor accuracy
±1
5
Document Number: 002-15631 Rev. *E
Page 19 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
SAR ADC
Table 21. SAR ADC DC Specifications
Parameter
A_RES
A_CHNIS_S
Description
Min
–
Typ
–
Max
12
6
Units
Details/Conditions
Resolution
bits
Number of channels - single-ended
–
–
6 full-speed[11]
Diff inputs use
A-CHNKS_D Number of channels - differential
A-MONO Monotonicity
A_GAINERR Gain error
–
–
3
neighboring I/O[11]
–
–
–
–
–
Yes
±0.1
%
With external reference
Measured with 1-V
VREF
A_OFFSET
Input offset voltage
–
–
2
mV
A_ISAR
A_VINS
A_VIND
A_INRES
A_INCAP
Current consumption
–
VSS
VSS
–
–
–
–
–
–
1
mA
V
–
–
–
–
–
Input voltage range - single-ended
Input voltage range - differential
Input resistance
VDDA
VDDA
2.2
V
k
pF
Input capacitance
–
10
Percentage of Vbg
(1.024 V)
VREFSAR
Trimmed internal reference to SAR
–1
–
1
%
Table 22. SAR ADC AC Specifications
Parameter
A_PSRR
Description
Min
70
66
–
Typ
–
Max
Units
Details/Conditions
Power-supply rejection ratio
Common-mode rejection ratio
Sample rate
–
–
1
dB
dB
Measured at 1-V reference
A_CMRR
A_SAMP
–
–
–
–
Msps
SAR operating speed without external ref.
bypass
Fsarintref
–
–
100
Ksps 12-bit resolution
A_SNR
A_BW
Signal-to-noise ratio (SNR)
Input bandwidth without aliasing
Integral nonlinearity.
65
–
–
–
–
dB
FIN = 10 kHz
A_SAMP/2
kHz
–
A_INL
A_INL
A_INL
A_dnl
–1.7
–1.5
–1.5
–1
–
–
–
–
–
2
LSB VREF = 1 V to VDD
LSB VREF = 1.71 V to VDD
LSB VREF = 1 V to VDD
LSB VREF = 1 V to VDD
LSB VREF = 1.71 V to VDD
LSB VREF = 1 V to VDD
V
DD = 1.71 V to 5.5 V, 1 Msps
Integral nonlinearity.
DDD = 1.71 V to 3.6 V, 1 Msps
Integral nonlinearity.
DD = 1.71 V to 5.5 V, 500 Ksps
Differential nonlinearity.
DD = 1.71 V to 5.5 V, 1 Msps
Differential nonlinearity.
DD = 1.71 V to 3.6 V, 1 Msps
Differential nonlinearity.
DD = 1.71 V to 5.5 V, 500 Ksps
Total harmonic distortion
1.7
1.7
2.2
2
V
V
V
A_DNL
–1
V
A_DNL
A_THD
–1
–
–
–
2.2
V
–65
dB
FIN = 10 kHz
Note
11. A maximum of six single-ended ADC Channels can be accomplished only if the AMUX Buses are not being used for other funcitonality (e.g. CapSense). If the
AMUX Buses are being used for other functions, then the maximum number of single-ended ADC channels is four. Similarly, if the AMUX Buses are being
used for other functionality, then the maximum number of differential ADC channels is two.
Document Number: 002-15631 Rev. *E
Page 20 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
CSD
Table 23. CSD Block Specifications
Parameter
Description
Min
Typ Max
Units
Details/Conditions
VCSD
Voltage range of operation
DNL for 8-bit resolution
INL for 8-bit resolution
DNL for 7-bit resolution
INL for 7-bit resolution
1.71
–1
–
–
–
–
–
3.6
1
V
–
–
–
–
–
IDAC1
IDAC1
IDAC2
IDAC2
LSB
LSB
LSB
LSB
–3
3
–1
1
–3
3
Capacitance range of 9 pF to
35 pF, 0.1-pF sensitivity. Radio is
not operating during the scan
SNR
Ratio of counts of finger to noise
5
–
–
Ratio
IDAC1_CRT1
IDAC1_CRT2
IDAC2_CRT1
IDAC2_CRT2
Output current of IDAC1 (8 bits) in High range
Output current of IDAC1 (8 bits) in Low range
Output current of IDAC2 (7 bits) in High range
Output current of IDAC2 (7 bits) in Low range
–
–
–
–
612
306
305
153
–
–
–
–
–
–
–
–
A
A
A
A
Digital Peripherals
Timer
Table 24. Timer DC Specifications
Parameter
ITIM1
ITIM2
ITIM3
Description
Min
Typ
Max
42
Units
A
A
Details/Conditions
16-bit timer
Block current consumption at 3 MHz
Block current consumption at 12 MHz
Block current consumption at 48 MHz
–
–
–
–
–
–
130
535
16-bit timer
16-bit timer
A
Table 25. Timer AC Specifications
Parameter Description
TTIMFREQ
Min
FCLK
Typ
–
Max
48
Units
MHz
Details/Conditions
Operating frequency
–
–
–
–
–
–
–
–
TCAPWINT
Capture pulse width (internal)
Capture pulse width (external)
Timer resolution
2 × TCLK
2 × TCLK
TCLK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
TCAPWEXT
TTIMRES
TTENWIDINT
TTENWIDEXT
TTIMRESWINT
TTIMRESEXT
Enable pulse width (internal)
Enable pulse width (external)
Reset pulse width (internal)
Reset pulse width (external)
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
Document Number: 002-15631 Rev. *E
Page 21 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Counter
Table 26. Counter DC Specifications
Parameter
ICTR1
ICTR2
ICTR3
Description
Min
–
Typ
–
Max
42
Units
Details/Conditions
16-bit counter
Block current consumption at 3 MHz
Block current consumption at 12 MHz
Block current consumption at 48 MHz
A
A
A
–
–
130
535
16-bit counter
–
–
16-bit counter
Table 27. Counter AC Specifications
Parameter
TCTRFREQ
Description
Min
Typ
–
Max
48
–
Units
MHz
ns
Details/Conditions
Operating frequency
FCLK
–
–
–
–
–
–
–
–
TCTRPWINT
TCTRPWEXT
TCTRES
Capture pulse width (internal)
Capture pulse width (external)
Counter Resolution
2 × TCLK
2 × TCLK
TCLK
–
–
–
ns
–
–
ns
TCENWIDINT
TCENWIDEXT
TCTRRESWINT
Enable pulse width (internal)
Enable pulse width (external)
Reset pulse width (internal)
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
–
–
ns
–
–
ns
–
–
ns
TCTRRESWEXT Reset pulse width (external)
–
–
ns
Pulse Width Modulation (PWM)
Table 28. PWM DC Specifications
Parameter
IPWM1
IPWM2
IPWM3
Description
Min
–
Typ
–
Max
42
Units
A
A
Details/Conditions
16-bit PWM
Block current consumption at 3 MHz
Block current consumption at 12 MHz
Block current consumption at 48 MHz
–
–
130
535
16-bit PWM
–
–
A
16-bit PWM
Table 29. PWM AC Specifications
Parameter Description
TPWMFREQ
TPWMPWINT
TPWMEXT
Min
Typ
–
Max
48
–
Units
MHz
ns
Details/Conditions
Operating frequency
FCLK
–
–
–
–
–
–
–
–
–
Pulse width (internal)
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
2 × TCLK
–
Pulse width (external)
–
–
ns
TPWMKILLINT
TPWMKILLEXT
TPWMEINT
Kill pulse width (internal)
Kill pulse width (external)
Enable pulse width (internal)
Enable pulse width (external)
Reset pulse width (internal)
Reset pulse width (external)
–
–
ns
–
–
ns
–
–
ns
TPWMENEXT
TPWMRESWINT
TPWMRESWEXT
–
–
ns
–
–
ns
–
–
ns
Document Number: 002-15631 Rev. *E
Page 22 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
LCD Direct Drive
Table 30. LCD Direct Drive DC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
16 × 4 small segment display at
50 Hz
ILCDLOW
Operating current in low-power mode
–
17.5
–
A
LCD capacitance per segment/common
driver
CLCDCAP
–
500
5000
pF
–
LCDOFFSET
ILCDOP1
Long-term segment offset
–
–
–
20
2
–
–
–
mV
–
LCD system operating current, VBIAS = 5 V
LCD system operating current, VBIAS = 3.3 V
mA 32 × 4 segments. 50 Hz at 25 °C
mA 32 × 4 segments. 50 Hz at 25 °C
ILCDOP2
2
Table 31. LCD Direct Drive AC Specifications
Parameter Description
FLCD
Min
Typ
50
Max
Units
Details/Conditions
LCD frame rate
10
150
Hz
–
Serial Communication
Table 32. Fixed I2C DC Specifications
Parameter
II2C1
Description
Min
Typ
Max
Units
A
A
A
A
Details/Conditions
Block current consumption at 100 kHz
Block current consumption at 400 kHz
Block current consumption at 1 Mbps
I2C enabled in Deep-Sleep mode
–
–
–
–
–
–
–
–
50
–
–
–
–
II2C2
II2C3
II2C4
155
390
1.4
Table 33. Fixed I2C AC Specifications
Parameter Description
FI2C1
Min
Typ
Max
Units
Details/Conditions
Bit rate
–
–
400
kHz
Table 34. Fixed UART DC Specifications
Parameter
IUART1
IUART2
Description
Min
–
Typ
–
Max
55
Units
A
A
Details/Conditions
Block current consumption at 100 kbps
Block current consumption at 1000 kbps
–
–
–
–
312
Table 35. Fixed UART AC Specifications
Parameter Description
FUART
Min
Typ
Max
Units
Details/Conditions
Bit rate
–
–
1
Mbps
–
Table 36. Fixed SPI DC Specifications
Parameter
ISPI1
ISPI2
ISPI3
Description
Min
–
Typ
–
Max
360
560
600
Units
A
A
Details/Conditions
Block current consumption at 1 Mbps
Block current consumption at 4 Mbps
Block current consumption at 8 Mbps
–
–
–
–
–
–
–
A
Document Number: 002-15631 Rev. *E
Page 23 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Table 37. Fixed SPI AC Specifications
Parameter
Description
SPI operating frequency (master; 6x over sampling)
Min
Typ
Max
Units
Details/Conditions
FSPI
–
–
8
MHz
–
Table 38. Fixed SPI Master Mode AC Specifications
Parameter
TDMO
Description
Min
Typ Max Units
Details/Conditions
MOSI valid after SCLK driving edge
–
–
–
–
18
ns
ns
ns
–
MISO valid before SCLK capturing edge
Full clock, late MISO sampling used
TDSI
20
0
–
Full clock, late MISO sampling
Referred to Slave capturing edge
THMO
Previous MOSI data hold time
–
Table 39. Fixed SPI Slave Mode AC Specifications
Parameter Description
Min
40
–
Typ
–
Max
–
Units
ns
TDMI
MOSI valid before SCLK capturing edge
MISO valid after SCLK driving edge
TDSO
–
42 + 3 × TCPU
ns
MISO Valid after SCLK driving edge in
external clock mode. VDD < 3.0 V
TDSO_ext
–
–
50
ns
THSO
Previous MISO data hold time
0
–
–
–
–
ns
ns
TSSELSCK
SSEL valid to first SCK valid edge
100
Memory
Table 40. Flash DC Specifications
Parameter Description
VPE
Min
Typ
–
Max
5.5
–
Units
Details/Conditions
Erase and program voltage
1.71
V
–
TWS48
TWS32
TWS16
Number of Wait states at 32–48 MHz
Number of Wait states at 16–32 MHz
Number of Wait states for 0–16 MHz
2
1
0
–
CPU execution from flash
CPU execution from flash
CPU execution from flash
–
–
–
–
Table 41. Flash AC Specifications
Parameter
Description
Min
Typ
–
Max
20
13
7
Units
Details/Conditions
[12]
TROWWRITE
Row (block) write time (erase and program)
–
–
ms Row (block) = 256 bytes
[12]
TROWERASE
Row erase time
–
ms
ms
–
–
–
–
–
–
–
TROWPROGRAM[12] Row program time after erase
–
–
[12]
TBULKERASE
Bulk erase time (256 KB)
–
–
35
25
–
ms
[12]
TDEVPROG
FEND
Total device program time
–
–
seconds
cycles
years
years
Flash endurance
100 K
20
10
–
FRET
Flash retention. TA 55 °C, 100 K P/E cycles
Flash retention. TA 85 °C, 10 K P/E cycles
–
–
FRET2
–
–
Note
12. It can take as much as 20 ms to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied on to have
completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make
certain that these are not inadvertently activated.
Document Number: 002-15631 Rev. *E
Page 24 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
System Resources
Power-on-Reset (POR)
Table 42. POR DC Specifications
Parameter
Description
Min
0.80
0.75
15
Typ
–
Max
1.45
1.40
200
Units
V
Details/Conditions
VRISEIPOR
VFALLIPOR
VIPORHYST
Rising trip voltage
–
–
–
Falling trip voltage
Hysteresis
–
V
–
mV
Table 43. POR AC Specifications
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Precision power-on reset (PPOR) response
time in Active and Sleep modes
TPPOR_TR
–
–
1
s
–
Table 44. Brown-Out Detect
Parameter
Description
Min
1.64
1.4
Typ
–
Max
–
Units
Details/Conditions
VFALLPPOR
VFALLDPSLP
BOD trip voltage in Active and Sleep modes
BOD trip voltage in Deep Sleep
V
V
–
–
–
–
Table 45. Hibernate Reset
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
VHBRTRIP
BOD trip voltage in Hibernate
1.1
–
–
V
–
Voltage Monitors (LVD)
Table 46. Voltage Monitor DC Specifications
Parameter
VLVI1
Description
Min
1.71
1.76
1.85
1.95
2.05
2.15
2.24
2.34
2.44
2.54
2.63
2.73
2.83
2.93
3.12
4.39
–
Typ
1.75
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.20
4.50
–
Max
1.79
1.85
1.95
2.05
2.15
2.26
2.36
2.46
2.56
2.67
2.77
2.87
2.97
3.08
3.28
4.61
100
Units
V
Details/Conditions
LVI_A/D_SEL[3:0] = 0000b
LVI_A/D_SEL[3:0] = 0001b
LVI_A/D_SEL[3:0] = 0010b
LVI_A/D_SEL[3:0] = 0011b
LVI_A/D_SEL[3:0] = 0100b
LVI_A/D_SEL[3:0] = 0101b
LVI_A/D_SEL[3:0] = 0110b
LVI_A/D_SEL[3:0] = 0111b
LVI_A/D_SEL[3:0] = 1000b
LVI_A/D_SEL[3:0] = 1001b
LVI_A/D_SEL[3:0] = 1010b
LVI_A/D_SEL[3:0] = 1011b
LVI_A/D_SEL[3:0] = 1100b
LVI_A/D_SEL[3:0] = 1101b
LVI_A/D_SEL[3:0] = 1110b
LVI_A/D_SEL[3:0] = 1111b
Block current
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
VLVI2
V
VLVI3
V
VLVI4
V
VLVI5
V
VLVI6
V
VLVI7
V
VLVI8
V
VLVI9
V
VLVI10
VLVI11
VLVI12
VLVI13
VLVI14
VLVI15
VLVI16
LVI_IDD
V
V
V
V
V
V
V
A
Document Number: 002-15631 Rev. *E
Page 25 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Table 47. Voltage Monitor AC Specifications
Parameter
TMONTRIP
Description
Min
Typ
Max
Units
Details/Conditions
Voltage monitor trip time
–
–
1
s
–
SWD Interface
Table 48. SWD Interface Specifications
Parameter
F_SWDCLK1
F_SWDCLK2
Description
3.3 V VDD 5.5 V
1.71 V VDD 3.3 V
Min
Typ
–
Max
Units
MHz
MHz
ns
Details/Conditions
–
14
SWDCLK 1/3 CPU clock frequency
–
–
7
SWDCLK 1/3 CPU clock frequency
T_SWDI_SETUP T = 1/f SWDCLK
T_SWDI_HOLD T = 1/f SWDCLK
0.25 × T
–
–
–
–
–
–
0.25 × T
–
–
0.5 × T
–
ns
T_SWDO_VALID T = 1/f SWDCLK
T_SWDO_HOLD T = 1/f SWDCLK
–
1
–
ns
–
ns
Internal Main Oscillator
Table 49. IMO DC Specifications
Parameter
IIMO1
Description
Min
Typ
Max
Units
Details/Conditions
IMO operating current at 48 MHz
IMO operating current at 24 MHz
IMO operating current at 12 MHz
IMO operating current at 6 MHz
IMO operating current at 3 MHz
–
–
–
–
–
–
–
–
–
–
1000
325
225
180
150
A
A
A
A
A
–
–
–
–
–
IIMO2
IIMO3
IIMO4
IIMO5
Table 50. IMO AC Specifications
Parameter Description
FIMOTOL3
FIMOTOL3
Min
–
Typ
–
Max
±2
–
Units
%
Details/Conditions
Frequency variation from 3 to 48 MHz
IMO startup time
With API-called calibration
–
–
12
s
Internal Low-Speed Oscillator
Table 51. ILO DC Specifications
Parameter
IILO2
Description
ILO operating current at 32 kHz
Min
Typ
Max
Units
Details/Conditions
–
0.3
1.05
A
–
Table 52. ILO AC Specifications
Parameter Description
TSTARTILO1
FILOTRIM1
Min
–
Typ
–
Max
2
Units
ms
Details/Conditions
ILO startup time
–
–
32-kHz trimmed frequency
15
32
50
kHz
Table 53. ECO Trim Value Specification
Parameter Description
24-MHz trim value
Value
0x0000D0D0
Details/Conditions
Optimum trim value that needs to be loaded to register
CY_SYS_XTAL_BLERD_BB_XO_CAPTRIM_REG
ECOTRIM
(firmware configuration)
Document Number: 002-15631 Rev. *E
Page 26 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
BLE Subsystem
Table 54. BLE Subsystem
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
RF Receiver Specification
RX sensitivity with idle transmitter
–
–
–89
–91
–
–
dBm
dBm
Silicon only
Silicon only
Guaranteed by design
simulation
RXS, IDLE
RX sensitivity with idle transmitter
excluding Balun loss
Silicon only
RF-PHY Specification
(RCV-LE/CA/01/C)
RXS, DIRTY
RX sensitivity with dirty transmitter
–
–87
–70
dBm
RX sensitivity in high-gain mode with idle
transmitter
RXS, HIGHGAIN
RXS, IDLE, MOD
PRXMAX
–
–
–91
–93
–1
–
–
–
dBm
dBm
dBm
Silicon only
RX sensitivity for full module with idle
transmitter
Full module, LNA active
RF-PHY Specification
(RCV-LE/CA/06/C)
Maximum input power
–10
Cochannel interference,
Wanted signal at –67 dBm and Interferer
at FRX
RF-PHY Specification
(RCV-LE/CA/03/C)
CI1
–
–
9
21
15
–
dB
dB
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±1 MHz
RF-PHY Specification
(RCV-LE/CA/03/C)
CI2
3
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±2 MHz
RF-PHY Specification
(RCV-LE/CA/03/C)
CI3
–
–29
–39
–29
–30
–27
–27
–27
–27
–
dB
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at FRX ±3 MHz
RF-PHY Specification
(RCV-LE/CA/03/C)
CI4
–
–
dB
Adjacent channel interference
Wanted Signal at –67 dBm and Interferer
RF-PHY Specification
(RCV-LE/CA/03/C)
CI5
–
–
dB
at Image frequency (FIMAGE
)
Adjacent channel interference
Wanted signal at –67 dBm and Interferer
at Image frequency (FIMAGE ± 1 MHz)
RF-PHY Specification
(RCV-LE/CA/03/C)
CI6
–
–
dB
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 30–2000 MHz
RF-PHY Specification
(RCV-LE/CA/04/C)
OBB1
OBB2
OBB3
OBB4
IMD
–30
–35
–35
–30
–50
–
dBm
dBm
dBm
dBm
dBm
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2003–2399 MHz
RF-PHY Specification
(RCV-LE/CA/04/C)
–
Out-of-band blocking,
Wanted signal at –67 dBm and Interferer
at F = 2484–2997 MHz
RF-PHY Specification
(RCV-LE/CA/04/C)
–
Out-of-band blocking,
Wanted signal a –67 dBm and Interferer
at F = 3000–12750 MHz
RF-PHY Specification
(RCV-LE/CA/04/C)
–
Inter modulation performance
Wanted signal at –64 dBm and 1-Mbps
BLE, third, fourth, and fifth offset channel
RF-PHY Specification
(RCV-LE/CA/05/C)
–
Document Number: 002-15631 Rev. *E
Page 27 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Table 54. BLE Subsystem (continued)
Parameter Description
Min
Typ
Max
Units
Details/Conditions
100-kHz measurement
bandwidth
ETSI EN300 328 V2.1.1
Receiver spurious emission
30 MHz to 1.0 GHz
RXSE1
–
–
–57
dBm
1-MHz measurement
bandwidth
ETSI EN300 328 V2.1.1
Receiver spurious emission
1.0 GHz to 12.75 GHz
RXSE2
–
–
–47
dBm
RF Transmitter Specifications
TXP, ACC
RF power accuracy
–
–
±1
6
–
dB
dB
–
Usable range to comply to
certifications.
TXP, RANGE
RF power control range
21
This is the required power
level to comply to certifica-
tions and qualificatons for
this module
Output power, –12-dB (PA2) Gain setting
for silicon
TXP, TYP
TXP, MAX
–
–
7.5
–
–
dBm
dBm
Output power above +7.5
dBmwillvoidcertifications
and qualifications of this
module.
Output power, maximum power setting
Output power, minimum power setting
22.5
TXP, MIN
F2AVG
–
1.5
–
–
–
dBm
kHz
–
Average frequency deviation for
10101010 pattern
RF-PHY Specification
(TRM-LE/CA/05/C)
185
Average frequency deviation for
11110000 pattern
RF-PHY Specification
(TRM-LE/CA/05/C)
F1AVG
225
0.8
–150
–50
–20
–20
–
250
–
275
–
kHz
RF-PHY Specification
(TRM-LE/CA/05/C)
EO
Eye opening = F2AVG/F1AVG
Frequency accuracy
RF-PHY Specification
(TRM-LE/CA/06/C)
FTX, ACC
FTX, MAXDR
FTX, INITDR
FTX, DR
IBSE1
–
150
50
kHz
kHz
kHz
RF-PHY Specification
(TRM-LE/CA/06/C)
Maximum frequency drift
Initial frequency drift
–
RF-PHY Specification
(TRM-LE/CA/06/C)
–
20
kHz/
50 s
RF-PHY Specification
(TRM-LE/CA/06/C)
Maximum drift rate
–
20
In-band spurious emission at 2-MHz
offset
RF-PHY Specification
(TRM-LE/CA/03/C)
–
–20
-30
-55.5
-41.5
dBm
dBm
dBm
dBm
In-band spurious emission at 3-MHz
offset
RF-PHY Specification
(TRM-LE/CA/03/C)
IBSE2
–
–
Transmitter spurious emissions
(average), <1.0 GHz
TXSE1
–
–
FCC-15.247
FCC-15.247
Transmitter spurious emissions
(average), >1.0 GHz
TXSE2
–
–
RF Current Specifications
IRX
Receive current in normal mode
–
–
–
18.7
16.4
21.5
–
–
–
mA
mA
mA
Silicon only
Silicon only
Measured at VDDR
IRX_RF
Radio receive current in normal mode
Receive current in high-gain mode
IRX, HIGHGAIN
Silicon only
Document Number: 002-15631 Rev. *E
Page 28 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Table 54. BLE Subsystem (continued)
Parameter Description
IRX, LNA
Min
–
Typ
8.0
Max
Units
mA
Details/Conditions
LNA only
Receive current, LNA
–
–
–
ITX, 3dBm
ITX, 0dBm
TX current at 3-dBm setting (PA10)
TX current at 0-dBm setting (PA7)
–
20
mA
Silicon only
–
16.5
mA
Silicon only
Silicon only.
Measured at VDDR
ITX_RF, 0dBm
ITX_RF, 0dBm
Radio TX current at 0 dBm setting (PA7)
–
–
15.6
14.2
–
–
mA
mA
Silicon only.
Guaranteed by design
simulation
Radio TX current at 0 dBm excluding
Balun loss
ITX,-3dBm
ITX,-6dBm
ITX,-12dBm
ITX,-18dBm
TX current at –3-dBm setting (PA4)
TX current at –6-dBm setting (PA3)
TX current at –12-dBm setting (PA2)
TX current at –18-dBm setting (PA1)
–
–
–
–
15.5
14.5
13.2
12.5
–
–
–
–
mA
mA
mA
mA
Silicon only
Silicon only
Silicon only
Silicon only
PA only average current
Packet length of 0x01
Continuous Transmit
–
8.0
–
mA
PA TX Current at +7.5 dBm module TXP
Silicon TXP set to –12-dBm setting (PA2)
ITX, +7.5dBm
PA only average current
Packet length of 0xFF
Continuous Transmit
–
–
27.0
1.0
–
–
mA
ITXRX, PA/LNA
PA/LNA set to shutdown mode
A
PA/LNA only current
Module TXP: +7.5 dBm;
±20-ppm master and
slave clock accuracy.
Average current at 1-second BLE
connection interval
Iavg_1sec, 7.5dBm
–
–
30
13
–
–
A
A
For empty PDU exchange
Module TXP: +7.5 dBm;
±20-ppm master and
slave clock accuracy.
Average current at 4-second BLE
connection interval
Iavg_4sec, 7.5dBm
For empty PDU exchange
General RF Specifications
FREQ
RF operating frequency
2400
–
2
2482
–
MHz
MHz
kbps
s
–
–
–
–
–
CHBW
Channel spacing
–
–
–
–
DR
On-air data rate
1000
120
75
–
IDLE2TX
IDLE2RX
RSSI Specifications
RSSI, ACC
RSSI, RES
RSSI, PER
BLE.IDLE to BLE. TX transition time
BLE.IDLE to BLE. RX transition time
140
120
s
RSSI accuracy
–
–
–
±5
1
–
–
–
dB
dB
s
–
–
–
RSSI resolution
RSSI sample period
6
Document Number: 002-15631 Rev. *E
Page 29 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Environmental Specifications
Environmental Compliance
This Cypress BLE module is built in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen Free (HF)
directives. The Cypress module and components used to produce this module are RoHS and HF compliant.
RF Certification
The CYBLE-212006-01 and CYBLE-202007-01 modules will be certified under the following RF certification standards at production
release.
■ FCC: WAP2006
■ CE
■ IC: 7922A-2006
■ MIC: 203-JN0599
■ KC: MSIP-CRM-Cyp-2006
Safety Certification
The CYBLE-212006-01 and CYBLE-202007-01 modules comply with the following regulations:
■ Underwriters Laboratories, Inc. (UL) - Filing E331901
■ CSA
■ TUV
Environmental Conditions
Table 55 describes the operating and storage conditions for the Cypress BLE module.
Table 55. Environmental Conditions for CYBLE-2X20XX-X1
Description
Minimum Specification
Maximum Specification
85 °C
Operating temperature
–40 °C
Operating humidity (relative, non-condensation)
Thermal ramp rate
5%
85%
–
–40 °C
–
3 °C/minute
85 °C
Storage temperature
Storage temperature and humidity
85 ° C at 85%
15 kV Air
2.2 kV Contact
ESD: Module integrated into system Components[13]
–
ESD and EMI Protection
Exposed components require special attention to ESD and electromagnetic interference (EMI).
A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure
near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground.
Device Handling: Proper ESD protocol must be followed in manufacturing to ensure component reliability.
Note
13. This does not apply to the RF pins (ANT, XTALI, and XTALO). RF pins (ANT, XTALI, and XTALO) are tested for 500-V HBM.
Document Number: 002-15631 Rev. *E
Page 30 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Regulatory Information
FCC
FCC NOTICE:
The devices CYBLE-212006-01 and CYBLE-202007-01 comply with Part 15 of the FCC Rules. The device meet the requirements for
modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two condi-
tions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including
interference that may cause undesired operation.
CAUTION:
The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by
Cypress Semiconductor may void the user's authority to operate the equipment.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, ê may cause
harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation.
If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment
off and on, the user is encouraged to try to correct the interference by one or more of the following measures:
■ Reorient or relocate the receiving antenna.
■ Increase the separation between the equipment and receiver.
■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
■ Consult the dealer or an experienced radio/TV technician for help
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible
label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well
as the FCC Notice above. The FCC identifier is FCC ID: WAP2006.
In any case the end product must be labeled exterior with “Contains FCC ID: WAP2006”.
ANTENNA WARNING:
This device is tested with a standard SMA connector and with antennas meeting the characteristics shown in Table 7 on page 14.
When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with
non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna
connectors and Section 15.247 for emissions.
RF EXPOSURE:
To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved
antenna in the previous.
The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antennas
in Table 6 and Table 7 on page 14, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or
removal instructions about the integrated radio module is not allowed.
The radiated output power of CYBLE-212006-01 and CYBLE-202007-01 with the specified antennas are far below the FCC radio
frequency exposure limits. Nevertheless, use CYBLE-212006-01 and CYBLE-202007-01 in such a manner that minimizes the
potential for human contact during normal operation.
End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with
transmitter operating conditions for satisfying RF exposure compliance.
Document Number: 002-15631 Rev. *E
Page 31 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Innovation, Science and Economic Development (ISED) Canada Certification
CYBLE-212006-01 and CYBLE-202007-01 are licensed to meet the regulatory requirements of Innovation, Science and Economic
Development (ISED) Canada,
License: IC: 7922A-2006
Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure
compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from
www.ic.gc.ca.
This device has been designed to operate with the antennas listed in Table 6 and Table 7 on page 14, having a maximum gain of 2.2
dBi. Antennas not included in this list or having a gain greater than 2.2 dBi are strictly prohibited for use with this device. The required
antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any
other antenna or transmitter.
ISED NOTICE:
The devices CYBLE-212006-01 and CYBLE-202007-01, including the specified antennas comply with Canada RSS-GEN Rules. The
device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two
conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including
interference that may cause undesired operation.
Les dispositifs CYBLE-212006-01 et CYBLE-202007-01, y compris les antennes spécifiées, sont conformes aux Règles RSS-GEN
de Canada. L'appareil répond aux exigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est
soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter
toute interférence reçue, y compris les interférences pouvant entraîner un fonctionnement indésirable.
ISED INTERFERENCE STATEMENT FOR CANADA
These modules comply with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s).
Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any
interference, including interference that may cause undesired operation of the device.
Ces modules sont conformes à la norme (s) RSS soumise (s) à la licence de l'innovation, de la science et du développement
économique (ISED). Le fonctionnement est soumis aux deux conditions suivantes: (1) cet appareil ne doit pas provoquer d'inter-
férence, et (2) cet appareil doit accepter toute interférence, y compris les interférences susceptibles de provoquer un fonctionnement
indésirable de l'appareil.
ISED RADIATION EXPOSURE STATEMENT FOR CANADA
This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment.
Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé.
LABELING REQUIREMENTS:
The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible
label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as
the ISED Notice above. The IC identifier is 7922A-2006. In any case, the end product must be labeled in its exterior with "Contains
IC: 7922A-2006".
Document Number: 002-15631 Rev. *E
Page 32 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
European Declaration of Conformity
Hereby, Cypress Semiconductor declares that Bluetooth modules CYBLE-212006-01 and CYBLE-202007-01 comply with the
essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described
in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows:
All versions of the CYBLE-212006-01 and CYBLE-202007-01 in the specified reference design can be used in the following countries:
Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia,
Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom,
Switzerland, and Norway.
MIC Japan
CYBLE-212006-01 and CYBLE-202007-01 are certified as a module with type certification number 203-JN0599. End products that
integrate CYBLE-212006-01 and CYBLE-202007-01 do not need additional MIC Japan certification for the end product.
End product can display the certification label of the embedded module.
KC Korea
CYBLE-212006-01 and CYBLE-202007-01 are certified for use in Korea with certificate number MSIP-CRM-Cyp-2006.
Document Number: 002-15631 Rev. *E
Page 33 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Packaging
Table 56. Solder Reflow Peak Temperature
Module Part Number
Package
Maximum Peak Temperature Maximum Time at Peak Temperature No. of Cycles
260 °C 30 seconds
CYBLE-2X20XX-X1
30-pad SMT
2
Table 57. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Module Part Number
Package
MSL
CYBLE-2X20XX-X1
30-pad SMT
MSL 3
The CYBLE-2X20XX-X1 is offered in tape and reel packaging. Figure 11 details the tape dimensions used for the CYBLE-2X20XX-X1.
Figure 11. CYBLE-2X20XX-X1 Tape Dimensions
Figure 12 details the orientation of the CYBLE-2X20XX-X1 in the tape as well as the direction for unreeling.
Figure 12. Component Orientation in Tape and Unreeling Direction (Illustration Only)
Document Number: 002-15631 Rev. *E
Page 34 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Figure 13 details reel dimensions used for the CYBLE-2X20XX-X1.
Figure 13. Reel Dimensions
The CYBLE-2X20XX-X1 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The
center-of-mass for the CYBLE-2X20XX-X1 is detailed in Figure 14.
Figure 14. CYBLE-2X20XX-X1 Center of Mass (Seen from Top)
CYBLE-212006-01 Center of Mass
CYBLE-202007-01 Center of Mass
CYBLE-202013-11 Center of Mass
Document Number: 002-15631 Rev. *E
Page 35 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Ordering Information
Table 58 lists the CYBLE-2X20XX-X1 part numbers and features.
Table 58. Ordering Information
CPU Flash
Speed Size CapSense SCB TCPWM
(MHz) (KB)
12-Bit
SAR
ADC
Part Number
I2S LCD Package
Packing
Certified
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
48
48
48
256
256
256
Yes
Yes
Yes
2
2
2
4
4
4
1 Msps Yes Yes 30-SMT Tape and Reel
1 Msps Yes Yes 30-SMT Tape and Reel
1 Msps Yes Yes 30-SMT Tape and Reel
Yes
Yes
No
Table 59. Tape and Reel Package Quantity and Minimum Order Amount
Description
Minimum Reel Quantity Maximum Reel Quantity
Comments
Ships in 500 unit reel quantities.
Reel Quantity
500
500
500
500
–
Minimum Order Quantity (MOQ)
Order Increment (OI)
–
The CYBLE-2X20XX-X1 is offered in tape and reel packaging. The CYBLE-2X20XX-X1 ships with a maximum of 500 units/reel.
Part Numbering Convention
The part numbers are of the form CYBLE-ABCDEF-GH where the fields are defined as follows.
For additional information and a complete list of Cypress Semiconductor BLE products, contact your local Cypress sales
representative. To locate the nearest Cypress office, visit our website.
U.S. Cypress Headquarters Address
U.S. Cypress Headquarter Contact Info
Cypress website address
198 Champion Court, San Jose, CA 95134
(408) 943-2600
http://www.cypress.com
Document Number: 002-15631 Rev. *E
Page 36 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Acronyms
Document Conventions
Table 60. Acronyms Used in this Document
Units of Measure
Acronym
Description
Bluetooth Low Energy
Table 61. Units of Measure
BLE
Symbol
Unit of Measure
degree Celsius
kilovolt
Bluetooth
SIG
°C
Bluetooth Special Interest Group
kV
CE
European Conformity
mA
mm
mV
A
m
MHz
GHz
V
milliamperes
millimeters
millivolt
CSA
EMI
ESD
FCC
GPIO
IC
Canadian Standards Association
electromagnetic interference
electrostatic discharge
microamperes
micrometers
megahertz
gigahertz
Federal Communications Commission
general-purpose input/output
Industry Canada
IDE
KC
integrated design environment
Korea Certification
volt
Ministry of Internal Affairs and Communications
(Japan)
MIC
PCB
RX
printed circuit board
receive
QDID
qualification design ID
surface-mount technology; a method for producing
electronic circuitry in which the components are
placed directly onto the surface of PCBs
SMT
TCPWM
TUV
timer, counter, pulse width modulator (PWM)
Germany: Technischer Überwachungs-Verein
(Technical Inspection Association)
TX
transmit
Document Number: 002-15631 Rev. *E
Page 37 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Document History Page
Document Title: CYBLE-212006-01, CYBLE-202007-01, CYBLE-202013-11 EZ-BLE™ PRoC™ XR Module
Document Number: 002-15631
Orig. of
Change
Submission
Date
Revision
ECN
Description of Change
**
5446955
DSO
10/07/2016 Preliminary datasheet for CYBLE-2X20XX-X1 modules.
Updated More Information:
Added EZ-Serial™ BLE Firmware Platform section.
Updated Overview:
Added Bluetooth Declaration ID and QDID under “Bluetooth 4.2 qualified
single-mode module”
Updated Recommended Host PCB Layout:
Updated Figure 4, Figure 5, and Figure 6 captions to specify that these as “Seen
on Host PCB”.
*A
5536076
DSO
11/29/2016
Updated Power Supply Connections and Recommended External Components:
Updated Figure 7 and Figure 8 to specify that these are “Seen from Bottom”.
Updated Digital and Analog Capabilities and Connections:
Updated Table 4:
Updated TCPWM column to add TCPWM capability on Port 2 pins.
Added Footnote 5.
Updated More Information:
Added hyperlinks for Evaluation Board listed under Development Kits
Updated Enabling Extended Range Feature:
Updated SAR ADC:
Updated Table 21 to add Note 10 to specify under what conditions the maximum
number of ADC channels can be achieved.
*B
5554670
DSO
DSO
12/15/2016
Changed status from “Preliminary” to “Final”.
Added Antenna Matching Network Requirements for CYBLE-202013-11
section.
Updated Table 54 to update specifications for RX, TX, and module power
consumption.
Updated Figure 14 to add Center of Mass for CYBLE-212006-01.
*C
*D
5667227
03/21/2017
5705684 AESATMP7 04/21/2017 Updated Cypress Logo and Copyright.
Updated More Information.
Updated Enabling Extended Range Feature to specifically state that there is no
bypass mode of operation for this module.
Updated Table 53, specifications RSXE1 and RSXE2 comment to latest CE
specification - ETSI EN300 V2.1.1.
Updated power supply upper voltage range for VDD signal throughout document
to 3.6 V due to PA/LNA digital interface power level requirement:
Updated Power Supply Connections and Recommended External Components.
Updated Figure 8.
*E
5782926
DSO
06/22/2017
Updated Table 4, Table 10 through Table 14, Table 15, Table 17, Table 22, and
Table 23.
Updated Innovation, Science and Economic Development (ISED) Canada
Certification on page 32 to latest ISED documentation requirements.
Updated European Declaration of Conformity on page 32 to latest European
regulatory requirements.
Updated Sales page.
Document Number: 002-15631 Rev. *E
Page 38 of 39
CYBLE-212006-01
CYBLE-202007-01
CYBLE-202013-11
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Forums | WICED IOT Forums | Projects | Video | Blogs |
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© Cypress Semiconductor Corporation, 2016-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-15631 Rev. *E
Revised June 22, 2017
Page 39 of 39
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