MB15F72ULPV [CYPRESS]
PLL Frequency Synthesizer, BICMOS, PBCC20, PLASTIC, BCC-20;
| 型号： | MB15F72ULPV |
| 厂家： | 
CYPRESS |
| 描述： | PLL Frequency Synthesizer, BICMOS, PBCC20, PLASTIC, BCC-20 信息通信管理 |
| 文件： | 总18页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dec. 2000
Edition 2.0
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F72UL
n
DESCRIPTION
The Fujitsu MB15F72UL is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300MHz and a
350MHz prescalers. A 64/65 or a 128/129 for the 1300MHz prescaler, and a 8/9 or a 16/17 for the 350MHz prescaler
can be selected for the prescaler that enables pulse swallow operation.
The latest BiCMOS process is used, as a result a supply current is typically 2.5mA typ. at 2.7V. The supply voltage
range is from 2.4V to 3.6V. A refined charge pump supplies well-balanced output current with 1.5mA and 6mA
selectable by serial data. The data format is same as the previous one MB15F02SL, MB15F72SP. Fast locking is
acheived for adopting the new circuit in the RF PLL section.
The new package(BCC20) decreases a mount area of MB15F72UL more than 30% comparing with the former
BCC16(for dual PLL).
MB15F72UL is ideally suited for wireless mobile communications, such as PDC.
n
FEATURES
• High frequency operation: RF synthesizer : 1300MHz max
IF synthesizer :: 350MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
°
• Ultra Low power supply current : ICC = 2.5 mA typ. (VCC = Vp=2.7V, Ta=25 C, SW=0 in RF, IF locking state)
• Direct power saving function : Power supply current in power saving mode
m
°
m
Typ. 0.1 A(Vcc=Vp=2.7V, Ta=25 C), Max. 10 A(Vcc=Vp=2.7V)
• Dual modulus prescaler : 1300MHz prescaler(64/65 or 128/129) / 350MHz prescaler(8/9 or 16/17)
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• On-chip phase comparator for fast lock and low noise
• On-chip phase control for phase comparator
°
• Operating temperature: Ta = –40 to 85 C
• Sireal data format compatible with MB15F02SL
20-pin, Plastic TSSOP
20-pad, Plastic BCC
(LCC-20P-M05)
(FPT-20P-M06)
1
Dec. 2000
Edition 2.0
MB15F72UL
n
PIN ASSIGNMENT
Clock
Data
LE
20
19
1
2
3
OSCIN
GND
Data
OSCIN
Clock
GND
20
18 17
18
19
finIF
1
finIF
XfinIF
16
LE
finRF
XfinIF
17
16
15
14
2
15
14
finRF
4
5
6
7
8
3
XfinRF
GNDIF
TOP
VIEW
TOP
VIEW
XfinRF
GNDIF
VccIF
13
12
11
GNDRF
VCCRF
PSRF
VccIF
PSIF
VpIF
4
5
6
GNDRF
VccRF
PSIF
10
9
7
8
13
PSRF
VpRF
DoRF
VpIF
DoIF
DoIF
LD/fout
RFVpRF
Do
12
11
9
10
LD/fout
LCC-20P-M05
FPT-20P-M06
2
Dec. 2000
Edition 2.0
MB15F72UL
n
PIN DESCRIPTIONS
Pin No.
Pin
I/O
Descriptions
name
TSSOP
BCC
The programmable reference divider input. TCXO should be connected
with a AC coupling capacitor.
1
2
3
19
OSCIN
GND
finIF
I
-
I
20
Ground for OSC input buffer and the shift registor circuit.
Prescaler input pin for the IF-PLL section.
Connection to an external VCO should be AC coupling.
1
Prescaler complimentary input for the IF-PLL section.
This pin should be grounded via a capacitor.
4
5
2
3
XfinIF
I
GNDIF
-
Ground for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section(except for the
charge pump circuit), the shift register and the oscillator input buffer.
When power is OFF, latched data of IF-PLL is lost.
6
7
4
5
VccIF
PSIF
-
I
Power saving mode control for the IF-PLL section. This pin must be set
at ”L” Power-ON. (Open is prohibited.)
PSIF = ”H” ; Normal mode PSIF = ”L” ; Power saving mode
8
9
6
7
VpIF
DoIF
-
Power supply voltage input pin for the IF-PLL charge pump.
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FC-bit.
O
Lock detect signal output(LD)/ phase comparator monitoring outut
(fout). The output signal is selected by a LDS bit in a serial data.
LDS bit = "1" ; outputs fout signal LDS bit = "0" ; outputs LD sihnal
10
8
LD/fout
O
Charge pump output for the RF-PLL section.
11
12
9
DoRF
VpRF
O
-
Phase characteristics of the phase detector can be reversed by FC-bit.
10
Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control for the RF-PLL section. This pin must be
set at ”L” Power-ON. (Open is prohibited.)
PSRF = ”H” ; Normal mode PSRF = ”L” ; Power saving mode
13
11
PSRF
I
Power supply voltage input pin for the RF-PLL section(except for the
charge pump circuit).
14
15
16
12
13
14
VccRF
GNDRF
XfinRF
-
-
I
Ground for the RF-PLL section.
Prescaler complimentary input for the RF-PLL section.
This pin should be grounded via a capacitor.
Prescaler input pin for the RF-PLL.
17
18
15
16
finRF
I
I
Connction to an external VCO should be AC coupling.
Load enable signal input (with the schmitt trigger circuit.)
When LE is set "H", data in the shift register is transferred to the corre-
sponding latch according to the control bit in a serial data.
LE
Serial data input (with the schmitt trigger circuit.)
A data is transferred to the corresponding latch (IF-ref counter, IF-prog.
counter, RF-ref. counter, RF-prog. counter) according to the control bit
in a serial data.
19
20
17
18
Data
I
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit.)
One bit data is shifted into the shift register on a rising edge of the
clock.
Clock
3
Dec. 2000
Edition 2.0
MB15F72UL
n
BLOCK DIAGRAM
VpIF
GNDIF
VCCIF
6
(3)
5
(6)
(4)
8
7-bit latch
3-bit latch
11-bit latch
Intermittent
PSIF
mode
control
(IF–PLL)
7
(5)
IF
fp
Binary 11-bit
programmable
counter(IF–PLL)
Binary 7-bit
Phase
comp.
(IF–PLL)
Charge
Current
Switch
SWIF FCIF
LDS
swallow counter
pump
DoIF
9
(IF–PLL)
(IF–PLL)
(7)
(1)
3
Prescaler
(IF–PLL)
finIF
8/9,16/17
XfinIF
4
(2)
Lock
Det.
2-bit latch
14-bit latch
1-bit latch
(IF–PLL)
C/P
setting
current
IF
LD
Binary 14–bit pro-
grammable ref.
counter(IF–PLL)
T1
T2
IF
fr
1
OSCin
Fast
lock
tuning
(19)
AND
Selector
LD
OR
frIF
frRF
LD/fout
10
(8)
C/P
setting
current
Binary 14-bit pro-
grammable ref.
counter(RF–PLL)
fpIF
T1
T2
fpRF
2-bit latch
14-bit latch
1-bit latch
Lock
Det.
(15)
17
Prescaler
RF
fr
(RF–PLL)
finRF
(RF–PLL)
64/65,
128/129
XfinRF
16
(14)
Binary 7-bit
Binary 11-bit
programmable
counter(RF–PLL)
Phase
comp.
Fast
lock
tuning
Charge
Current
Switch
LDS SWRF FCRF
3-bit latch
swallow counter
DoRF
11
(9)
pump
(RF–PLL)
Intermittent
mode
(RF–PLL)
(RF–PLL)
RF
fp
PSRF 13
(11)
control
7-bit latch
11-bit latch
(RF–PLL)
Schmitt
circuit
LE
18
(16)
Latch selector
Schmitt
circuit
Data
19
(17)
C
N
C
N
23-bit shift
register
1
2
Schmitt
circuit
Clock
20
(18)
12
(12)
14
15
(13)
(10)
2
(20)
VccRF
VpRF
GND
GNDRF
O -- TSSOP 20
( ) -- BCC 20
4
Dec. 2000
Edition 2.0
MB15F72UL
n
ABSOLUTE MAXIMUM RATINGS
Parameter
Power supply voltage
Input voltage
Symbol
Rating
–0.5 to +4.0
Vcc to +4.0
Unit
Remark
VCC
V
V
V
V
V
p
V
VI
VO
–0.5 to VCC +0.5
GND to Vcc
GND to Vp
LD/fout
Do
Output voltage
VDO
stg
°
C
Storage temperature
T
–55 to +125
Note: Permanent device damage may occur if the above Absolute Maximum Ratingsare exceeded. Functional
operation should be restricted to the conditions as detailed in the operational sections of this data sheet.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
n
RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
2.4
Typ.
2.7
2.7
–
Max.
3.6
VCC
Vp
VI
V
V
V
VCCRF = VCCIF
Power supply voltage
Vcc
3.6
Input voltage
GND
–40
VCC
+85
°
C
Operating temperature
Ta
–
Handling Precautions
(1) VccRF,VpRF,VccIF and VpIF must supply equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VccRF,VpRF,VccIF and VpIF to keep them
equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
5
Dec. 2000
Edition 2.0
MB15F72UL
n
ELECTRICAL CHARACTERISTICS
°
(VCC = 2.4 to 3.6 V, Ta = –40 to +85 C)
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
finIF=270MHz
ICCIF
–
1.0
1.7
mA
mA
VccIF=VpIF=2.7V
Power supply current*1
finRF=910MHz
VccRF=VpRF=2.7V
ICCRF
–
1.5
2.5
m
A
IPSIF
IPSRF
finIF
PSIF=PSRF= ”L”
PSIF=PSRF= ”L”
IF PLL
–
–
0.1*2
10
10
Power saving current*9
Operating frequency
0.1*2
–
m
A
*3
*3
finIF
50
100
3
350
1300
40
MHz
MHz
MHz
dBm
dBm
Vp-p
finRF
OSCIN
finIF
finRF
fosc
RF PLL
–
–
–
W
PfinIF IF PLL, 50 system
-15
-15
0.5
–
+2
W
Input sensitivity
finRF
PfinRF RF PLL, 50 system
–
+2
OSCIN
VOSC
–
–
VCC
´
Vcc
"H" level Input voltage
"L" level Input voltage
"H" level Input voltage
"L" level Input voltage
VIH
Schmitt trigger input
–
–
–
–
–
Data,
Clock,
LE
0.7+0.4
V
V
´
Vcc
0.3-0.4
VIL
VIH
VIL
Schmitt trigger input
–
´
Vcc
–
–
–
0.7
PS
´
Vcc
0.3
–
*4
"H" level Input current
"L" level Input current
Data,
Clock,
LE, PS
IIH
–
–
–1.0
–1.0
–
–
+1.0
m
A
*4
IIL
+1.0
"H" level Input current
"L" level Input current
IIH
–
–
0
–
–
+100
0
m
A
OSCIN
*4
IIL
–100
Vcc –
0.4
p
"H" level output voltage
"L" level output voltage
"H" level output voltage
"L" level output voltage
VOH
VOL
VCC=V =2.7V, IOH=–1mA
–
–
–
–
–
–
LD/fout
V
p
VCC=V =2.7V, IOL=1mA
–
0.4
–
Vp –
0.4
p
VDOH
VDOL
IOFF
VCC=V =2.7V, IDOH=-0.5mA
DoIF
DoRF
V
p
VCC=V =2.7V, IDOL=0.5mA
–
–
0.4
2.5
High impedance
cutoff current
DoIF
DoRF
VCC=2.7V,
VOFF=0.5V to V –0.5V
nA
p
*4
"H"level Output current
"L" level Output current
IOH
VCC = Vp = 2.7V
VCC = Vp = 2.7V
–
–
–
-1.0
–
LD/fout
mA
IDOL
1.0
(Continued)
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Dec. 2000
Edition 2.0
MB15F72UL
(Continued)
°
Ta =(VCC = 2.4 to 3.6 V, Ta = –40 to +85 C)
Value
Unit
Parameter
Symbol
Condition
Min.
Typ.
Max.
p
VCC=V
CS bit ="1"
CS bit ="0"
CS bit ="1"
CS bit ="0"
-8.2
-6.0
-4.1
=2.7 V
*4
"H"level Output current
"L" level Output current
IDOH
p
VDOH=V /2
-2.2
4.1
0.8
-1.5
6.0
1.5
-0.8
8.2
2.2
°
Ta= 25 C
*8
DoTX
mA
DoRX
p
VCC=V
=2.7 V
IDOL
p
VDOL=V /2
°
Ta= 25 C
*5
p
IDOL/IDOH
vs VDO
IDOMT
VDO=V /2
–
–
3
–
–
%
%
*6
p
Charge pump
current rate
IDOVD
0.5V < VDO < V -0.5V
10
°
°
-40 C < Ta < 85 C,
*7
vs Ta
IDOTA
–
5
–
%
p
VDO=V /2
°
*1: Conditions; fosc=12.8MHz, Ta = 25 C, SW="L" in locking state.
°
*2: VccIF=VpIF=VccRF=VpRF=2.7V, fosc=12.8MHz, Ta = 25 C, in power saving mode.
*3: AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency.
*4: The symbol "-"(minus) means direction of current flow.
°
*5: Vcc=Vp=2.7V, Ta=25 C ( ||I3| - |I4|| ) / [( |I3| + |I4| )/2] x 100(%)
°
*6: Vcc=Vp=2.7V, Ta=25 C [( ||I2| - |I1|| ) /2 ] / [( |I1| + |I2| )/2] x 100(%) (Applied to each IDOL, IDOH)
*7: Vcc=Vp=2.7V, [(||IDO(85C)| - |IDO(-40C)||) /2] / [(|IDO(85C)| + |IDO(-40C)|) /2] x 100(%) (Applied to each IDOL, IDOH)
*8: When Charge pump current is measured, set LDS="0", T1="0" and T2="1".
IF
RF
*9: PS =PS =GND (VIL=GND and VIH=Vcc for Clock, Data, LE)
I2
I3
I1
I1
I4
I2
0.5
VP/2
VP-0.5
VP
Output voltage(V)
7
Dec. 2000
Edition 2.0
MB15F72UL
n
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
¸
fVCO = {(P x N) + A} x fOSC
R
fVCO:
P:
N:
Output frequency of external voltage controlled oscillator (VCO)
Preset divide ratio of dual modulus prescaler (8 or 9 for IF-PLL, 64 or 128 for RF-PLL)
Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
£
£
A:
Preset divide ratio of binary 7-bit swallow counter (0 A 127, condition;A < N)
fOSC:
R:
Reference oscillation frequency
Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL
sections, programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On a rising edge of clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable
signal , the data stored in the shift register is transferred to one of latch of them depending upon the control bit data
setting.
Table1. Control Bit
Control bit
Destination of serial data
CN1
L
CN2
L
The programmable reference counter for the IF-PLL.
H
L
The programmable reference counter for the RF-PLL.
L
H
The programmable counter and the swallow counter for the IF-PLL
The programmable counter and the swallow counter for the RF-PLL
H
H
Shift Register Configuration
Programmable Reference Counter
MSB
LSB
Data Flow
2
6
23
X
7
9
12 13 14 15
19
21
X
1
3
8
11
17 18
22
X
4
5
10
16
R
20
X
C
C
N
1
R
2
R
T
1
R
3
R
4
R
6
R
7
R
9
T
2
R
1
R
5
R
8
R
R
R
C
S
N
2
10
11 12 13 14
CN1, 2
: Control bit
[Table. 1]
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383) [Table. 2]
T1, 2
CS
X
: LD/fout output setting bit
[Table. 3]
[Table. 8]
: Charge pump current select bit
: Dummy bits(Set "0" or "1")
NOTE: Data input with MSB first.
8
Dec. 2000
Edition 2.0
MB15F72UL
Programmable Counter
MSB
LSB
1
Data Flow
19 20 21 22 23
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
C
N
1
C
N
2
L
S
F
C
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
N
D
S
W
IF/RF
10 11
IF/RF
CN1, 2
: Control bit
[Table. 1]
[Table. 4]
[Table. 5]
[Table. 6]
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
A1 to A7
: Divide ratio setting bits for the swallow counter (0 to 127)
SWIF/RF
: Divide ratio setting bit for the prescaler
(8/9 or 16/17 for the SWIF, 64/65 or 128/129 for the SWRF)
FCIF/RF
: Phase control bit for the phase detector(IF : FCIF, RF : FCRF)
: LD/fout signal select bit
[Table. 7]
[Table. 3]
LDS
NOTE: Data input with MSB first.
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
R
R
R
R
R
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
ratio
(R)
14
13
12
11
10
3
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
0
1
1
0
×
1
1
0
×
1
4
×
×
×
16383
1
1
·
Note: Divide ratio less than 3 is prohibited.
Table.3 LD/fout output Selectable Bit Setting
LD/fout pin state
LDS
T1
0
T2
0
0
0
0
1
1
1
1
LD output
1
0
1
1
IF
fr
0
0
RF
fr
1
0
fout
output
IF
fp
0
1
RF
fp
1
1
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Dec. 2000
Edition 2.0
MB15F72UL
Table.4 Binary 11-bit Programmable Counter Data Setting
Divide
N
N
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
ratio
(N)
11
10
3
4
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
1
×
1
1
0
×
1
1
0
×
1
×
2047
·
Note: Divide ratio less than 3 is prohibited.
Table.5 Binary 7-bit Swallow Counter Data Setting
Divide
A
7
A
6
A
5
A
4
A
3
A
2
A
1
ratio
(N)
0
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
0
×
1
0
1
×
1
×
127
·
Note: Divide ratio (A) range = 0 to 127
Table. 6 Prescaler Data Setting
SW = ”H”
SW = ”L”
16/17
IF-PLL
8/9
Prescaler
divide ratio
RF-PLL
64/65
128/129
Table. 7 Phase Comparator Phase Switching Data Setting
IF,RF
IF,RF
FC
= H
Do
FC
= L
1
IF,RF
fr > fp
fr = fp
H
Z
L
1
L
Z
H
2
VCO Output
Frequency
fr < fp
VCO polarity
·
·
Note:
Z = High–impedance
Depending upon the VCO and LPF polarity,
FC bit should be set.
2
VCO Input Voltage
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Dec. 2000
Edition 2.0
MB15F72UL
Table. 8 Charge Pump Current Setting
CS
H
Current value
+ 6.0 mA
L
+ 1.5 mA
4. Power Saving Mode (Intermittent Mode Control Circuit)
Table 9. PS Pin Setting
PS pin
Status
H
L
Normal mode
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pin low, the device enters into the power saving mode, reducing the current consumption. See
the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the single PLL, the lock detector, LD, remains high, indicating a locked condition.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pin high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is because
of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr) which can
cause a major change in the comparator output, resulting in a VCO frequency jump and an increase in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error signal
from the phase detector when it returns to normal operation.
m
Note: When power (VCC) is first applied, the device must be in standby mode, PS=Low, for at least 1 s.
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·
Note:
PS pin must be set at “L” for Power ON.
OFF
ON
tv > 1ms
Vcc
Clock
Data
LE
tps > 100ns
PS
(3)
(1)
(2)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1ms later after power supply remains stable(Vcc > 2.2V).
(3) Relase power saving mode (PS: L ® H) 100nS later after setting serial data.
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SERIAL DATA INPUT TIMING
1st data
2nd data
Control bit
LSB
Invalid data
MSB
Data
Clock
LE
t4
t2
t1
t3
t5
t7
t6
On the rising edge of the clock, one bit of data is transferred into the shift register.
Parameter
Min.
Typ. Max.
Unit
Parameter
Min.
Typ. Max.
Unit
20
20
30
30
–
–
–
–
–
–
–
–
100
20
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
t1
t2
t3
t4
t5
t6
t7
100
Note: LE should be "L" when the data is transferred into the shift register.
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PHASE DETECTOR OUTPUT WAVEFORM
frIF/RF
fpIF/RF
tWU
tWL
LD
(FC bit = High)
H
DoIF/RF
Z
L
(FC bit = Low)
DoIF/RF
Z
LD Output Logic Table
IF–PLL section
LD output
RF–PLL section
Locking state / Power saving state
Unlocking state
Locking state / Power saving state
H
L
Locking state / Power saving state
Unlocking state
Locking state / Power saving state
Unlocking state
L
L
Unlocking state
·
·
·
·
·
- p
p
Note:
Phase error detection range = 2 to +2
IF/RF
Pulses on Do
signals are output to prevent dead zone.
LD output becomes low when phase error is tWU or more.
LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
tWU and tWL depend on OSCin input frequency as follows.
tWU > 2/fosc: i.e. tWU > 156.3ns when foscin = 12.8 MHz
tWL < 4/fosc: i.e. tWL < 312.5ns when foscin = 12.8 MHz
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TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
fout
Oscilloscope
VpIF
VccIF
0.1mF
0.1mF
1000pF
P.G
1000pF
1000pF
P.G
50W
IF
IF
IF
IF
IF
IF
fin
LD/fout Do
PS
7
Vcc GND Xfin
GND OSCin
IF
Vp
8
50W
10
6
5
4
9
1
3
2
MB15F72UL
11 12 13
14 15
17
18 19
20
16
XfinRF
VccRF GNDRF
finRF
DoRF VpRF PSRF
Data Clock
LE
1000pF
P.G
1000pF
Controller (divide
ratio setting)
VpRF
VccRF
50W
0.1mF
0.1mF
Note : TSSOP-20
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APPLICATION EXAMPLE
LPF
OUTPUT
VCO
from controller
1000 pF
2.7 V
0.1mF
2.7 V
0.1mF
1000 pF
Clock DATA
LE
finRF
XfinRF GNDRF VccRF
PSRF
VpRF
DoRF
20
19
18
17
16
15
14
13
12
11
MB15F72UL
8
1
2
3
4
7
9
10
5
6
OSCin
GND
finIF
XfinIF
GNDIF VccIF
PSIF
VpIF
DoIF
LD/fout
Lock Det.
2.7 V
2.7 V
1000 pF
1000 pF
1000 pF
0.1mF
0.1mF
TCXO
LPF
VCO
OUTPUT
Clock, Data, LE: Schmitt trigger circuit is provided (insert a pull-down or pull-up resistor to prevent oscillation
when open-circuited in the input).
Note :TSSOP-20
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PACKAGE DIMENSION
* : These dimensions do not include resin protrusion.
20 pin, Plastic SSOP
(FPT-20P-M06)
(Continued)
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Dec. 2000
Edition 2.0
MB15F72UL
(Continued)
20 pad, Plastic BCC
(LCC-20P-M05)
18
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