W212HT [CYPRESS]
Processor Specific Clock Generator, 146MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48;
| 型号： | W212HT |
| 厂家： | 
CYPRESS |
| 描述： | Processor Specific Clock Generator, 146MHz, CMOS, PDSO48, 0.300 INCH, SSOP-48 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总15页 (文件大小：153K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
W212
Frequency Timing Generator for ALI 1641
CPU to PCI Offset: ........................ 1.0 to 3.0 ns (CPU leads)
Features
AGP Outputs Skew:.....................................................250 ps
• Maximized EMI Suppression using Cypress’s Spread
Spectrum technology
• I C™ interface
• Two copies of CPU Output
• One copy of IOAPIC Output
SDRAM Outputs Skew: ...............................................250 ps
PCI Outputs Skew: ......................................................500 ps
AGP to PCI Skew: .......................................................... TBD
2
Table 1. Pin Selectable Frequency (Center Spread)
• Six copies of PCI Output
• Two copies of AGP Output
Input Address
CPU
(MHz)
SDRAM
(MHz)
AGP
(MHz)
PCI
(MHz)
APIC
(MHz)
FS3 FS2 FS1 FS0
• One copy of selectable 48-MHz or 24-MHz Output
• Thirteen copies of SDRAM Output
• Two buffered copy of 14.318-MHz reference clock
• Mode input pin selects optional power management in-
put control pins (reconfigures pins 19, 20, 21 and 22)
• Smooth frequency transition upon frequency
reselection
• Available in 48-pin SSOP (300 mils)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.8
100.2
66.8
100.2
100.2
66.8
66.8
66.8
66.8
66.8
66.8
66.8
66.8
66.6
63.3
63.3
70.0
73.3
61.0
61.0
70.0
73.0
33.4
33.4
33.4
33.4
33.4
33.4
33.4
33.4
31.6
31.6
35.0
36.6
30.5
30.5
35.0
36.5
16.7
16.7
16.7
16.7
16.7
16.7
16.7
16.7
15.8
15.8
17.5
18.3
15.3
15.3
17.5
18.3
133.6
66.8
100.2
133.6
133.6
66.8
100.2
100.2
133.6
95.0
133.6
95.0
Key Specifications
95.0
126.6
140.0
110.0
122.0
91.5
Supply Voltages: ....................................... V
V
= 3.3V±5%
= 2.5V±5%
DDQ3
DDQ2
105.0
110.0
122.0
122.0
140.0
146.0
CPU Cycle to Cycle Jitter: .......................................... 250 ps
CPU Outputs Skew:.................................................... 175 ps
CPU to AGP Offset: .................................................. <500 ps
CPU to SDRAM Offset:............................................. <500 ps
105.0
146.0
Pin Configuration[1]
Block Diagram
VDDQ3
PLL REF
REF0/FS2
REF1/FS1
X1
X2
PWD
XTAL
PLL1
REF0/FS2*
VDDQ2
IOAPIC
VDDQ2
CPU_F
CPU
*FS1/REF1
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ3
2
X1
X2
GND
GND
3
VDDQ2
CPU_F
4
5
PWD
6
7
8
9
CPU
DIV
^FS3/AGP0
GND
STOP/
PWD
CPU
AGP1
GND
VDDQ3
SDRAM0
SDRAM1
SDRAM2
VDDQ3
SDRAM3
SDRAM4
SDRAM5
GND
VDDQ3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDQ3
*FS0/PCI_F
PCI1
9
(AGP_STOP#)
(CPU_STOP#)
(PCI_STOP#)
(PWR_DWN#)
SDR
DIV
SDRAM(_0:8)
PCI2
GND
PWD
Control
Unit
PCI3
PCI4
PCI5
SDRAM9 (AGP_STOP#)
SDRAM10(PWR_DWN#)
SDRAM11 (PCI_STOP#)
SDRAM12 (CPU_STOP#)
SDRAM6
SDRAM7
SDRAM8
VDDQ3
GND
48_24MHz/Mode*
VDDQ3
SDATA
(FS0:3)
Mode
VDDQ3
*(CPU_STOP#)SDRAM12
*(PCI_STOP#)SDRAM11
*(PWR_DWN#)SDRAM10
*(AGP_STOP#))SDRAM9
GND
VDDQ3
AGP1
SDATA
SCLK
AGP
DIV
2
STOP/
PWD
I C
SCLOCK
AGP0/FS3
÷2
PCI_F/FS0
PCI(1:5)
PWD
5
Note:
STOP
PWD
1. Signal names with (*) denotes pins have internal 140K pull-up resis-
tor, though not relied upon for pulling to VDDQ3. Signal names with
parentheses denotes function is selectable by MODE pin strapping.
2. Signal names with (^) denotes pins have internal 55K pull-down re-
sistor, though not relied upon for pulling to VDDQ3. Signal names with
VDDQ2
IOAPIC
VDDQ3
÷2
parentheses denotes function is selectable by MODE pin strapping.
PWD
÷1/÷2
PLL2
48_24MHz/Mode
I2C is a trademark of Philips Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
April 5, 2000 rev. **
PRELIMINARY
W212
Pin Definitions
Pin
No.
Pin
Type
Pin Name
Pin Description
CPU_F
44
43
11
O
Free Running CPU Clock: This clock output is not affected by the CPU_STOP#
control pin. Output voltage swing is controlled by voltage applied to VDDQ2.
CPU
O
CPU Clock Output: This output is controlled by the CPU_STOP# control pin. Out-
put voltage swing is controlled by voltage applied to VDDQ2.
PCI_F/FS0
I/O
Free-running PCI Clock Output and Frequency Selection Bit 0: As an output,
this pin works in conjunction with PCI1:5. Output voltage swing is controlled by
voltage applied to VDDQ3.
When an input, this pin functions as part of the frequency selection address. The
value of FS0:3 determines the power-up default frequency of device output clocks
as per Table 1 on page 1.
PCI1:5
12, 13, 15, 16,
17
O
O
PCI Clock Outputs 1 through 5: Output voltage swing is controlled by voltage
applied to VDDQ3. Outputs are held LOW if PCI_STOP# is set LOW.
SDRAM0:8
30, 31,32, 34,
35, 36,38, 39,
40
SDRAM Clock Outputs: These nine SDRAM clock outputs run synchronous to the
CPU clock outputs or AGP clock output.
SDRAM9/
AGP_STOP#
22
I/O
I/O
SDRAM Clock Output and AGP Stop: The SDRAM clock outputs run synchronous
to the CPU clock outputs or AGP clock output. If programmed as inputs (refer to
MODE pin description), this pin is used for AGP stop control. When input is LOW,
pin will be at logic zero.
SDRAM10/
PWR_DWN#
21
SDRAM Clock Output and Power Down: The SDRAM clock outputs run synchro-
nous to the CPU clock outputs or AGP clock output. If programmed as inputs (refer
to MODE pin description), this pin is used for power-down control. The asynchro-
nous active LOW input pin disables the internal clocks with the VCO and crystal
stopped.
SDRAM11/
PCI_STOP#
20
19
27
I/O
I/O
I/O
SDRAM Clock Output and PCI Stop: The SDRAM clock outputs run synchronous
to the CPU clock outputs or AGP clock output. If programmed as inputs (refer to
MODE pin description), this pin is used for PCI stop control. All PCI pins except for
PCI_F will be at logic zero.
SDRAM12/
CPU_STOP#
SDRAM Clock Output and CPU Stop: The SDRAM clock outputs run synchronous
to the CPU clock outputs or AGP clock output. If programmed as inputs (refer to
MODE pin description), this pin is used to stop all CPU clocks except for the CPU_F
clock. When input is LOW, pin will be at logic zero.
48_24MHz/
MODE
48-MHz or 24-MHz Output, and MODE Control: Selectable clock output that de-
faults to 48 MHz following device power-up. When an input, this pin functions as a
select pin for either Desktop Mode (1) or Mobile Mode (0).
REF0/FS2
REF1/FS1
48
1
I/O
I/O
O
Reference Clock Output and Frequency Select Input: 14.318-MHz Reference
Clock. When configured as an input, this pin is a frequency select pin.
Reference Clock Output and Frequency Select Input: 14.318-MHz Reference
Clock. When configured as an input, this pin is a frequency select pin.
AGP0/FS3,
AGP1
7, 8
46
3
AGP Output: This output is controlled by the AGP_STOP# pin.
IOAPIC
O
I/O APIC Clock Output: The output voltage swing is set by the power connection
to VDDQ2.
X1
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
4
I
I
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
SDATA
SCLOCK
25
24
Serial Data Input: Data input for Serial Data Interface. Refer to Serial Data Interface
section that follows.
Serial Clock Input: Clock input for Serial Data Interface. Refer to Serial Data In-
terface section that follows.
2
PRELIMINARY
W212
Pin Definitions (continued)
Pin
Pin
Pin Name
VDDQ3
No.
Type
Pin Description
2, 9, 10, 18,
26, 29, 37
P
Power Connection: Connected to 3.3V supply.
VDDQ2
GND
45, 47
P
Power Connection: Connected to 2.5V supply.
5, 6, 14, 23,
G
Ground Connection: Connect all ground pins to the common system ground plane.
28, 33, 41, 42
W212 Pin Selection Tables
Table 2. Mode Function
Pin Function
MODE
Pin 19
Pin 20
Pin 21
Pin 22
SDRAM9
1
0
SDRAM12
SDRAM11
PCI_STOP#
SDRAM10
PWR_DWN#
CPU_STOP#
AGP_STOP#
Table 3. Power Management Pin Function
Signal
= 0
= 1
CPU_STOP#
PCI_STOP#
AGP_STOP#
PWR_DWN#
CPU = LOW
PCI1:5 = LOW
AGP0:1 = LOW
Active
Active
Active
Active
All Clock Outputs LOW
the established logic 0 or 1 condition of each l/O is pin is
latched. Next the output buffers are enabled, converting all l/O
pins into operating clock outputs. The 2-ms timer starts when
Overview
The W212 was designed specifically to provide all clock sig-
nals required for a motherboard designed with the ALI 1641
PII/PIII style chipset.
V
reaches 2.0V. The input bits can only be reset by turn-
DDQ3
ing V
off and then back on again.
DDQ3
Thirteen SDRAM outputs are provided for support of up to 3
SDRAM DIMM modules. Unused clock outputs can be dis-
abled through the I C interface to reduce system power con-
It should be noted that the strapping resistors have no signifi-
cant effect on clock output signal integrity. The drive imped-
ance of the clock output is 40Ω (nominal) which is minimally
2
sumption and more importantly reduce EMI emissions.
affected by the 10-kΩ strap to ground or V
. As with the
DDQ3
series termination resistor, the output strapping resistor should
be placed as close to the l/O pin as possible in order to keep
the interconnecting trace short. The trace from the resistor to
Functional Description
I/O Pin Operation
ground or V
should be kept less than two inches in length
DDQ3
to prevent system noise coupling during input logic sampling.
Pins 1, 7, 11, 19, 20, 21, 22, 27, and 48 are dual-purpose l/O
pins. Upon power-up these pins act as logic inputs, allowing
the determination of assigned device functions. A short time
after power-up, the logic state of each pin is latched and the
pins then become clock outputs. This feature reduces device
pin count by combining clock outputs with input select pins.
When the clock outputs are enabled following the 2-ms input
period, target (normal) output frequency is delivered, assum-
ing that V
has stabilized. If V
has not yet reached full
DDQ3
DDQ3
value, output frequency initially may be below target but will
increase to target once V voltage has stabilized. In either
DDQ3
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
An external 10-kΩ “strapping” resistor is connected between
each l/O pin and ground or V
. Connection to ground sets
DDQ3
a latch to “0,” connection to V
and Figure 2 show two suggested methods for strapping resis-
sets a latch to “1.” Figure 1
DDQ3
CPU/ SDRAM/ AGP/ PCI Frequency Selection
tor connection.
CPU output frequency is selected with I/O pins 1, 7, 11, and
48. Refer to Table 2 for CPU/PCI frequency programming in-
formation. Alternatively, frequency selections are available
through the serial data interface. Refer to Table 7, “Additional
Frequency Selections through Serial Data Interface Data
Bytes (Down Spread),” on page 8.
Upon W212 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the 48_24MHz, REF1,
PCI_F, AGP0 and SDRAM9:12 clock output buffers are three-
stated, allowing the output strapping resistor on each l/O pin
to pull the pin and its associated capacitive clock load to either
a logic HIGH or logic LOW state. At the end of the 2-ms period,
3
PRELIMINARY
W212
V
DDQ3
Output Strapping Resistor
Series Termination Resistor
10 kΩ
(Load Option 1)
Clock Load
W212
R
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
10 kΩ
(Load Option 0)
Q
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
Output Strapping Resistor
Series Termination Resistor
V
DDQ3
10 kΩ
Clock Load
W212
R
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
Q
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
Output Buffer Configuration
The internal crystal oscillator is used in conjunction with a
quartz crystal connected to device pins X1 and X2. This forms
a parallel resonant crystal oscillator circuit. The W212 incor-
porates the necessary feedback resistor and crystal load ca-
pacitors. Including typical stray circuit capacitance, the total
load presented to the crystal is approximately 20 pF. For opti-
mum frequency accuracy without the addition of external ca-
pacitors, a parallel-resonant mode crystal specifying a load of
20 pF should be used. This will typically yield reference fre-
quency accuracies within ±100 ppm. To achieve similar accu-
racies with a crystal calling for a greater load, external capac-
itors must be added such that the total load (internal, external,
and parasitic capacitors) equals that called for by the crystal.
Clock Outputs
All clock outputs are designed to drive serially terminated clock
lines. The W212 outputs are CMOS-type which provide rail-to-
rail output swing.
Crystal Oscillator
The W212 requires one input reference clock to synthesize all
output frequencies. The reference clock can be either an ex-
ternally generated clock signal or the clock generated by the
internal crystal oscillator. When using an external clock signal,
pin X1 is used as the clock input and pin X2 is left open. The
input threshold voltage of pin X1 is (V
)/2.
DDQ3
4
PRELIMINARY
W212
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions. Table 4 summarizes the control functions of
the serial data interface.
Serial Data Interface
The W212 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W212 initializes with
default register settings, therefore the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chip) and is the dedicated function of device pins SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the
Operation
Data is written to the W212 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 5.
Table 4. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI and
abled outputs are actively held LOW.
system power. Examples are clock outputs to un-
used SDRAM DIMM socket or PCI slot.
CPU Clock Frequency Provides CPU/PCI frequency selections through
For alternate CPU devices, and power manage-
ment options. Smooth frequency transition al-
lows CPU frequency change under normal sys-
tem operation.
Selection
software. Frequency is changed in a smooth and
controlled fashion.
Output Three-state
(Reserved)
Puts clock output into a high-impedance state.
Production PCB testing.
Reserved function for future device revision or pro- No user application. Register bit must be written
duction device testing. as 0.
Table 5. Byte Writing Sequence
Byte Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address 11010010
Commands the W212 to accept the bits in Data Bytes 0–6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W212 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
3
Command
Code
Don’t Care
Don’t Care
Unused by the W212, therefore bit values are ignored (“Don’t Care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Byte Count
Unused by the W212, therefore bit values are ignored (“Don’t Care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocoland may be used when writing to anotheraddressed
slave receiver on the serial data bus.
4
5
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Refer to Table 6 The data bits in Data Bytes 0–7 set internal W212 registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 6, Data Byte Serial Configuration Map.
6
7
8
9
10
5
PRELIMINARY
W212
Writing Data Bytes
7. Table 6 gives the bit formats for registers located in Data
Bytes 0–6.
Each bit in the data bytes controls a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
Table 7 details additional frequency selections that are avail-
able through the serial data interface.
Table 6. Data Bytes 0–6 Serial Configuration Map
Affected Pin
Bit Control
Bit(s)
Pin No.
Pin Name
Control Function
0
1
Default
Data Byte 0
7
6
5
4
--
--
--
--
--
--
SEL_3
Refer to Table 7
0
0
0
0
0
SEL_2
--
SEL_1
--
SEL_0
3
11, 1,48,
7
FS0:3
BYT0 /FS#
Frequency Controlled Frequency Controlled
by external pins FS 0:2 by SEL _0:3, above
2-1
--
--
Bit 2 Bit 1 Function
00
0
0
1
1
0
1
0
1
±0.5% Center Spread
–0.5% Down Spread
(Reserved)
All Outputs Three-stated
0
27
48_24#MHz 1 = 48 MHz
0 = 24 MHz
1
Data Byte 1
7
27
--
48_24#MHz Clock Output Disable
Low
--
Active
1
1
1
1
1
1
1
1
6
--
(Reserved)
--
--
5
--
--
--
(Reserved)
--
4
--
(Reserved)
--
--
3
--
--
(Reserved)
--
--
2
--
--
(Reserved)
--
--
1
43
44
CPU
CPU_F
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
0
Data Byte 2
7
11
--
PCI_F
--
Clock Output Disable
(Reserved)
Low
--
Active
--
1
1
1
1
1
1
1
1
6
5
17
16
15
13
12
--
PCI5
PCI4
PCI3
PCI2
PCI1
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
4
3
2
1
0
Data Byte 3
7
6
5
4
3
2
31
32
34
35
36
38
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
1
1
1
1
1
1
6
PRELIMINARY
W212
Table 6. Data Bytes 0–6 Serial Configuration Map (continued)
Affected Pin
Bit Control
Bit(s)
Pin No.
39
Pin Name
SDRAM1
SDRAM0
Control Function
Clock Output Disable
Clock Output Disable
0
1
Default
1
0
Low
Low
Active
Active
1
1
40
Data Byte 4
7
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
--
--
0
1
1
1
1
1
1
1
6
--
--
5
--
--
4
19
20
21
22
30
SDRAM12 Clock Output Disable
SDRAM11 Clock Output Disable
SDRAM10 Clock Output Disable
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
3
2
1
SDRAM9
SDRAM8
Clock Output Disable
Clock Output Disable
0
Data Byte 5
7
5
5
4
3
2
1
0
--
--
(Reserved)
--
--
0
0
0
1
1
1
1
1
(Reserved)
--
--
--
(Reserved)
--
--
48
1
REF0
REF1
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
7
AGP0
AGP1
IOAPIC
8
46
Data Byte 6
7
6
5
4
3
2
1
0
7
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
SEL_3
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
1
1
0
0
Refer to Table 7
7
PRELIMINARY
W212
Table 7. Additional Frequency Selections through Serial Data Interface Data Bytes (Down Spread)
Input Conditions
Data Byte 0
Output Frequency
CPU
Clocks
(MHz)
SDRAM
(MHz)
AGP
PCI Clocks
APCI Clocks
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
(MHz)
(MHz)
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
31.6
31.6
35.0
36.6
30.5
30.5
35.0
36.5
(MHz)
16.7
16.7
16.7
16.7
16.7
16.7
16.7
16.7
15.8
15.8
17.5
18.3
15.3
15.3
17.5
18.3
66.6
100.0
66.6
100.0
100.0
66.6
66.6
66.6
66.6
66.6
66.6
66.6
66.6
66.6
63.3
63.3
70.0
73.3
61.0
61.0
70.0
73.0
0
0
0
1
0
0
1
0
0
0
1
1
133.3
66.6
100.0
133.3
133.3
66.6
0
1
0
0
0
1
0
1
100.0
100.0
133.3
95.0
0
1
1
0
0
1
1
1
133.3
95.0
1
0
0
0
1
0
0
1
95.0
126.6
140.0
110.0
122.0
91.5
1
0
1
0
105.0
110.0
122.0
122.0
140.0
146.0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
105.0
146.0
1
1
1
1
8
PRELIMINARY
W212
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
Unit
V
V
, V
IN
DDQ3
STG
B
T
T
°C
°C
°C
kV
Ambient Temperature under Bias
Operating Temperature
T
A
ESD
Input ESD Protection
2 (min.)
PROT
3.3V DC Electrical Characteristics: T = 0°C to +70°C, V
= 3.3V±5%, V
= 2.5V±5%
DDQ2
A
DDQ3
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
I
3.3V Supply Current
CPU, CPU_F=133.3 MHz
Outputs Loaded
TBD
TBD
mA
mA
DD
[3]
I
2.5V Supply Current
CPU, CPU_F=133.3 MHz
DD
[3]
Outputs Loaded
Logic Inputs
V
V
Input Low Voltage
Input High Voltage
0.8
V
V
IL
2.0
IH
[4]
I
I
Input Low Current
20
5
µA
µA
IL
IH
[4]
Input High Current
Clock Outputs
V
Output Low Voltage
I
I
I
= 1 mA
50
mV
V
OL
OL
OH
OH
V
Output High Voltage
= –1 mA
= –1 mA
3.1
2.2
55
80
55
60
55
55
80
55
60
55
OH
V
Output High Voltage CPU,CPU_F
Output Low Current CPU; CPU_F
V
OH
I
V
= 1.5V
75
110
75
105
155
105
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
OL
OL
SDRAM0:12, AGP0:1
PCI_F, PCI1:5
REF0:1
75
48/24 MHZ
75
105
125
175
125
110
125
I
Output High Current CPU; CPU_F
V
= 1.5V
85
OH
OH
SDRAM0:12, AGP0:1
120
85
PCI_F, PCI1:5
REF0:1
85
48/24 MHZ
85
Notes:
3. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
4. W212 logic inputs have internal pull-up devices (not full CMOS level).
9
PRELIMINARY
W212
3.3V DC Electrical Characteristics: T = 0°C to +70°C, V
= 3.3V±5%, V
= 2.5V±5% (continued)
DDQ2
A
DDQ3
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
[5]
V
X1 Input Threshold Voltage
V
= 3.3V
DDQ3
1.65
20
V
TH
C
Load Capacitance, Imposed on
pF
LOAD
[6]
External Crystal
[7]
C
X1 Input Capacitance
Pin X2 unconnected
Except X1 and X2
30
pF
IN,X1
Pin Capacitance/Inductance
C
C
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
5
6
7
pF
pF
nH
IN
OUT
IN
L
Serial Input Port
V
V
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
V
V
= 3.3V
= 3.3V
0.3V
DDQ3
V
V
IL
DDQ3
DDQ3
0.7V
IH
DDQ3
I
I
I
10
10
µA
µA
mA
IL
IH
Sink Current into SDATA or SCLOCK,
Open Drain N-Channel Device On
I
= 0.3(V )
DDQ3
6
OL
OL
C
C
C
Input Capacitance of SDATA and SCLOCK
Total Capacitance of SDATA Bus
10
pF
pF
pF
IN
400
400
SDATA
SCLOCK
Total Capacitance of SCLOCK Bus
AC Electrical Characteristics
T = 0°C to +70°C, V
= 3.3V±5%,V
= 2.5V± 5% f
= 14.31818 MHz
A
DDQ3
DDQ2
XTL
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
AGP Clock Outputs, AGP0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Min.
Typ.
Max. Unit
t
f
t
t
t
t
t
t
15
ns
MHz
ns
P
Frequency, Actual
High Time
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
TBD
5.2
5
H
L
Low Time
ns
Output Rise Edge Rate Measured from 0.4V to 2.4V
Output Fall Edge Rate Measured from 2.4V to 0.4V
1
4
4
V/ns
V/ns
%
R
F
1
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
250
D
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum difference
of cycle time between two adjacent cycles.
ps
t
f
Output Skew
Measured on rising edge at 1.5V
175
3
ps
SK
FrequencyStabilization Assumes full supply voltage reached within 1 ms from
from Power-up (cold
start)
ms
ST
power-up. Short cycles exist prior to frequency stabili-
zation.
Z
AC Output Impedance Average value during switching transition. Used for de-
termining series termination value.
15
20
30
Ω
o
Notes:
5. X1 input threshold voltage (typical) is VDDQ3/2.
6. The W212 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 20 pF;
this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
10
PRELIMINARY
W212
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz CPU = 100 MHz CPU = 133 MHz
Test Condition/
Comments
Parameter
Description
Period
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
t
Measured on rising edge at
1.5V
15
10
7.5
ns
MHz
ns
P
f
t
t
t
t
t
t
Frequency,
Actual
Determined by PLL divider
ratio
TBD
TBD
TBD
High Time
Duration of clock cycle
above 2.4V
5.2
5
3.0
2.8
1
1.87
1.67
1
H
L
Low Time
Duration of clock cycle be-
low 0.4V
ns
Output Rise
Edge Rate
Measured from 0.4V to 2.4V
1
4
4
4
4
4
4
V/ns
V/ns
%
R
F
Output Fall Edge Measured from 2.4V to 0.4V
Rate
1
1
1
Duty Cycle
Measured on rising and fall- 45
ing edge at 1.5V
55
250
45
55
250
45
55
250
D
JC
Jitter, Cycle-to-
Cycle
Measured on rising edge at
1.5V. Maximumdifferenceof
cycle time between two ad-
jacent cycles.
ps
t
f
Output Skew
Frequency
Measured on rising edge at
1.5V
175
3
175
3
175
3
ps
SK
Assumes full supply voltage
ms
ST
Stabilizationfrom reached within 1 ms from
Power-up (cold
start)
power-up. Short cycles exist
prior to frequency stabiliza-
tion.
Z
AC Output
Impedance
Average value during
switching transition. Used
for determining series termi-
nation value.
15
20
30
15
20
30
15
20
30
Ω
o
11
PRELIMINARY
W212
SDRAM Clock Outputs, SDRAM0:12 (Lump Capacitance Test Load = 30 pF)
SDRAM =
SDRAM =
100 MHz
SDRAM =
133 MHz
66.6 MHz
Test Condition/
Parameter
Description
Period
Comments
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
t
f
t
t
t
t
Measured on rising edge at
1.5V
15
10
7.5
ns
MHz
V/ns
V/ns
%
P
Frequency,
Actual
Determined by PLL divider
ratio
TBD
TBD
TBD
Output Rise Edge Measured from 0.4V to 2.4V
Rate
1
1
4
4
1
1
4
4
1
1
4
4
R
Output Fall Edge Measured from 2.4V to 0.4V
Rate
F
Duty Cycle
Measured on rising and fall- 45
ing edge at 1.5V
55
250
45
55
250
45
55
250
D
Jitter, Cycle-to-
Cycle
Measured on rising edge at
1.5V. Maximum differenceof
cycle time between two ad-
jacent cycles.
ps
JC
t
t
Output Skew
Measured on rising edge at
1.5V
100
100
100
ps
ps
SK
CPU to SDRAM
Clock Skew
Covers all CPU/SDRAM
outputs. Measured on rising
edge at 1.5V.
500
3
500
3
500
3
SK
f
Frequency Stabi- Assumes full supply voltage
lization from Pow- reached within 1 ms from
er-up (cold start) power-up. Short cycles exist
prior to frequency stabiliza-
ms
ST
tion.
Z
AC Output
Impedance
Average value during
switching transition. Used
for determining series termi-
nation value.
10
15
20
10
15
20
10
15
20
Ω
o
12
PRELIMINARY
W212
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF
PCI = 33.3 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Min.
Typ.
Max.
Unit
ns
t
f
t
t
t
t
t
t
30
P
Frequency, Actual
High Time
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
TBD
MHz
ns
12
12
1
H
L
Low Time
ns
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
R
F
Measured from 2.4V to 0.4V
1
Measured on rising and falling edge at 1.5V
45
55
250
D
JC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
ps
difference of cycle time between two adjacent cycles.
t
t
Output Skew
Measured on rising edge at 1.5V
250
3
ps
ns
SK
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1
O
f
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
ST
Z
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
20
Ω
o
REF Clock Output (Lump Capacitance Test Load = 45 pF)
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
Max. Unit
f
14.31818
MHz
t
t
t
f
0.5
0.5
40
2
2
V/ns
V/ns
%
R
Measured from 2.4V to 0.4V
F
Measured on rising and falling edge at 1.5V
60
1.5
D
FrequencyStabilizationfrom Assumes full supply voltage reached within
ms
ST
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Z
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
30
Ω
o
13
PRELIMINARY
W212
48-/24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Deviation from 48 MHz
PLL Ratio
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
Min.
Typ.
Max. Unit
f
48.008/24.004
+167
MHz
ppm
f
D
m/n
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
57/17, 54/34
t
t
t
f
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
R
Measured from 2.4V to 0.4V
F
Measured on rising and falling edge at 1.5V
55
3
D
Frequency Stabilization
Assumes full supply voltage reached within 1 ms
ms
ST
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Z
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
30
Ω
o
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
SCLOCK Frequency
Start Hold Time
Test Condition/Comments
Normal Mode
Min.
0
Typ.
Max. Unit
f
100
kHz
µs
SCLOCK
STHD
LOW
t
t
t
t
t
4.0
4.7
4.0
250
0
µs
SCLOCK Low Time
SCLOCK High Time
Data Set-up Time
Data Hold Time
µs
HIGH
DSU
ns
(Transmitter should provide a 300-ns hold time to
ensure proper timing at the receiver.)
ns
DHD
t
t
Rise Time, SDATA and
SCLOCK
From 0.3V
to 0.7V
1000
300
ns
ns
R
F
DDQ3
DDQ3
Fall Time, SDATA and
SCLOCK
From 0.7V
to 0.3V
DDQ3
DDQ3
µs
µs
t
t
Stop Setup Time
4.0
4.7
STSU
Bus Free Time between
Stop and Start Condition
SPF
ns
t
Allowable Noise Spike
Pulse Width
50
SP
Ordering Information
Package
Name
Ordering Code
Package Type
W212
H
48-pin SSOP (300 mils)
Document #: 38-00915-**
14
PRELIMINARY
W212
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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