W215B [CYPRESS]
Notebook PC System Frequency Generator for K6 Processors; 笔记本电脑系统的频率发生器的K6处理器
| 型号： | W215B |
| 厂家： | 
CYPRESS |
| 描述： | Notebook PC System Frequency Generator for K6 Processors |
| 文件： | 总14页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
W215B
Notebook PC System Frequency Generator for K6 Processors
Features
Table 1. Pin Selectable Frequency
CPU, SDRAM
Clocks (MHz)
95.0
• Generates system clocks for CPU, IOAPIC, SDRAM,
PCI, USB plus 14.318 MHz (REF0:1)
• MODE input pin selects optional power management
input control pins (reconfigures pins 26 and 27)
• Two fixed outputs separately selectable as 24-MHz or
48-MHz (default = 48-MHz)
95/100_SEL
PCI Clocks
CPU/3
0
1
100.0
CPU/3
• VDDQ3 = 3.3V±5%, VDDQ2 = 3.3V±5%
• Uses external 14.318-MHz crystal
• Available in 48-pin TSSOP (6.1-mm)
• 10Ω CPU output impedance
Block Diagram
Pin Configuration
VDDQ3
REF1
REF0
GND
X1
X2
MODE
VDDQ3
PCI_F
PCI0
GND
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
GND
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDQ3
CPU_2.5#
VDDQ2
IOAPIC
PWR_DWN#
GND
CPU0
CPU1
VDDQ2
CPU2
CPU3
GND
SDRAM0
SDRAM1
VDDQ3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDQ3
SDRAM6/CPU_STOP#
SDRAM7/PCI_STOP#
VDDQ3
REF0
REF1
X1
X2
XTAL
OSC
PLL Ref Freq
VDDQ2
IOAPIC
VDDQ2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
CPU0
CPU1
CPU2
CPU3
CPU_2.5#
MODE
www.DataSheet4U.com
Stop
Output
Control
I/O
Control
VDDQ3
95/100_SEL
Reserved
Reserved
VDDQ3
48/24MHZ
48/24MHZ
GND
SDRAM0
SDRAM1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
PLL 1
95/100_SEL
SDRAM6/CPUSTOP#
SDRAM7/PCISTOP#
PCI_F
PCI0
PCI1
PCI2
PCI3
PCI4
PCI5
Stop
Output
Control
Power
Down
Control
PWR_DWN#
PLL2
48/24MHZ
48/24MHZ
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07222 Rev. *A*
Revised December 15, 2002
PRELIMINARY
W215B
Pin Definitions
Pin
No.
Pin
Pin Name
Type
Pin Description
CPU Outputs 0 through 3: These four CPU outputs are controlled by the
CPU_STOP# control pin. Output voltage swing is controlled by voltage applied to
CPU0:3
PCI0:5
42, 41, 39,
38
O
VDDQ2.
9,11,12,13,
14, 16
O
PCI Bus Outputs 0 through 5: These six PCI outputs are controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
PCI_F
8
O
Free Running PCI Output: Unlike PCI0:5 outputs, this output is not controlled by the
PCI_STOP# control pin. Output voltage swing is controlled by voltage applied to
VDDQ3.
SDRAM0:5
36, 35, 33,
32, 30, 29
O
SDRAM Clock Outputs 0 through 5: These six SDRAM clock outputs run synchro-
nous to the CPU clock outputs. Output voltage swing is controlled by voltage applied
to VDDQ3.
SDRAM6/
CPU_STOP#
27
I/O
SDRAM Clock Output 6 or CPU Clock Output Stop Control: This pin has dual
functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the
CPU_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 6.
Regarding use as a CPU_STOP# input: When brought LOW, clock outputs CPU0:3
are stopped LOW after completing a full clock cycle (2–3 CPU clock latency). When
brought HIGH, clock outputs CPU0:3 are started beginning with a full clock cycle (2–3
CPU clock latency).
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
SDRAM7/
PCI_STOP#
26
I/O
SDRAM Clock Output 7 or PCI Clock Output Stop Control: This pin has dual
functions, selectable by the MODE input pin. When MODE = 0, this pin becomes the
PCI_STOP# input. When MODE = 1, this pin becomes SDRAM clock output 7.
www.DataSheet4U.com
PCI_STOP# input: When brought LOW, clock outputs PCI0:5 are stopped LOW after
completing a full clock cycle. When brought HIGH, clock outputs PCI0:5 are started
beginning with a full clock cycle. Clock latency provides one PCI_F rising edge of PCI
clock following PCI_STOP# state change.
Regarding use as a SDRAM clock: Output voltage swing is controlled by voltage
applied to VDDQ3.
IOAPIC
45
O
O
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is controlled by VDDQ2.
48/24MHz
22, 23
48-MHz / 24-MHz Output: Fixed clock outputs that default to 48 MHz following device
power-up. Either or both can be changed to 24 MHz through use of the serial data
interface (Byte 0, bits 2 and 3). Output voltage swing is controlled by voltage applied
to VDDQ3
REF0:1
2, 1
O
Fixed 14.318-MHz Outputs 0 through 1: Used for various system applications. Out-
put voltage swing is controlled by voltage applied to VDDQ3. REF0 is stronger than
REF1 and should be used for driving ISA slots.
CPU_2.5#
47
18
I
I
Set to logic 1 for 3.3V CPU I/O.
95/100_SEL
95- or 100-MHz Input Selection: Selects power-up default CPU clock frequency as
shown in Table 1 on page 1 (also determines SDRAM and PCI clock frequency selec-
tions).
X1
X2
4
5
I
I
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using
an external reference, this pin must be left unconnected.
Document #: 38-07222 Rev. *A*
Page 2 of 14
PRELIMINARY
W215B
Pin Definitions
Pin
No.
Pin
Type
Pin Name
Pin Description
PWR_DWN#
44
I
Power-Down Control: When this input is LOW, device goes into a low-power standby
condition. All outputs are actively held LOW while in power-down. CPU, SDRAM, and
PCI clock outputs are stopped LOW after completing a full clock cycle (2–4 CPU clock
cycle latency). When brought HIGH, CPU, SDRAM, and PCI outputs start with a full
clock cycle at full operating frequency (3 ms maximum latency).
MODE
6
I
ModeControl: Thisinputselectsthefunctionofdevicepin26(SDRAM7/PCI_STOP#)
and pin 27 (SDRAM6/CPU_STOP#). Refer to description for those pins.
VDDQ3
VDDQ2
GND
7, 15, 21, 25
28, 34, 48
P
P
G
Power Connection: Power supply for PCI0:5, REF0:1, and 48-/24-MHz output buff-
ers. Connected to 3.3V supply.
46, 40
Power Connection: Power supply for IOAPIC0, CPU0:3 output buffer. Connected to
3.3V supply.
3, 10, 17,
24, 31, 37,
43
Ground Connection: Connect all ground pins to the common system ground plane.
Reserved
19, 20
I
Reserved Pins: Connect to Logic 1.
www.DataSheet4U.com
Document #: 38-07222 Rev. *A*
Page 3 of 14
PRELIMINARY
W215B
Absolute Maximum Ratings[1]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
Parameter
VDD, VIN
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
Unit
V
TSTG
TB
°C
°C
°C
kV
Ambient Temperature under Bias
Operating Temperature
TA
ESDPROT
Input ESD Protection
2 (min.)
DC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V), fXTL = 14.31818 MHz, VDDQ2 = 3.3V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDDQ3
Supply Current (3.3V)
CPU0:3 = 100 MHz
Outputs Loaded[2]
150
80
mA
mA
IDDQ2
Supply Current (3.3V)
CPU0:3 = 100 MHz
Outputs Loaded[2]
Logic Inputs
VIL
VIH
IIL
Input Low Voltage
Input High Voltage
Input Low Current[3]
Input High Current[3]
0.8
V
V
2.0
3.1
www.DataSheet4U.com
10
10
µA
µA
IIH
Clock Outputs
VOL
VOH
IOL
Output Low Voltage
IOL = 2 mA
IOH = –1 mA
VOL = 1.5V
50
mV
V
Output High Voltage
Output Low Current
CPU0:3
140
110
110
95
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
SDRAM0:7
PCI_F, PCI0:5
IOAPIC
V
OL = 1.5V
VOL = 1.5V
OL = 1.5V
V
REF0
VOL = 1.5V
VOL = 1.5V
75
REF1
70
48/24MHZ
CPU0:3
V
OL = 1.5V
70
IOH
Output High Current
VOL = 1.5V
VOL = 1.5V
120
95
SDRAM0:7
PCI_F, PCI0:5
IOAPIC
VOL = 1.5V
95
VOL = 1.5V
VOL = 1.5V
95
REF0
80
REF1
VOL = 1.5V
62
48/24MHZ
VOL = 1.5V
60
Notes:
1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. All clock outputs loaded with maximum lump capacitance test load specified in AC Electrical Characteristics section.
3. W215B logic inputs have internal pull-up devices (not CMOS level).
Document #: 38-07222 Rev. *A*
Page 4 of 14
PRELIMINARY
W215B
DC Electrical Characteristics (continued)
TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V), fXTL = 14.31818 MHz, VDDQ2 = 3.3V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input Threshold Voltage[4]
VDDQ3 = 3.3V
1.65
14
V
CLOAD
Load Capacitance, Imposed on External
Crystal[5]
pF
CIN,X1
X1 Input Capacitance[6]
Pin X2 unconnected
Except X1 and X2
28
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
5
6
7
pF
pF
nH
COUT
Output Pin Capacitance
Input Pin Inductance
LIN
Notes:
4. X1 input threshold voltage (typical) is VDDQ3/2.
5. The W215B contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
AC Electrical Characteristics (Lump Load Model)
TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V) fXTL = 14.31818 MHz, VDDQ2 = 3.3V±5%
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.
Test Point
www.DataSheet4U.com
*20pF for CPU, REF1, IOAPIC,
24MHz & 48MHz
FTG
*30pF for SDRAM & PCI
CPU Clock Outputs, CPU0:3 (Lump Capacitance Test Load = 20 pF)
CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Min. Typ. Max. Unit
tP
f
Period
10
100
5
ns
MHz
ns
Frequency, Actual
High Time
tH
tL
Low Time
5
ns
tR
tF
tD
tJC
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
1
1
4
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
45
50
10
55
500
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
ps
tSK
fST
Output Skew
Measured on rising edge at 1.5V
250
3
ps
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
Power-up (cold start)
ms
from power-up. Short cycles exist prior to frequency
stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
Ω
Document #: 38-07222 Rev. *A*
Page 5 of 14
PRELIMINARY
W215B
SDRAM Clock Outputs, SDRAM0:7 (Lump Capacitance Test Load = 30 pF)
CPU = 100 MHz
Min. Typ. Max. Unit
Parameter
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Measured from 0.4V to 2.4V
tP
f
Period
10
ns
MHz
V/ns
V/ns
%
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
100
tR
tF
tD
tJC
1
1
4
4
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
45
50
55
500
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
ps
tSK
tSK
Output Skew
Measured on rising edge at 1.5V
100
ps
ns
CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on
rising edge at 1.5V.
1.5
3
fST
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
ms
Power-up (cold start)
from power-up. Short cycles exist prior to frequency
stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
16
Ω
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)
CPU = 100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Min.
Typ.
30
Max.
Unit
ns
tP
f
www.DataSheet4U.com
Frequency, Actual
High Time
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
33.3
MHz
ns
tH
tL
12
12
1
Low Time
ns
tR
tF
tD
tJC
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
1
Measured on rising and falling edge at 1.5V
45
50
55
500
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
ps
difference of cycle time between two adjacent cycles.
tSK
tO
Output Skew
Measured on rising edge at 1.5V
250
4
ps
ns
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
15
Ω
Document #: 38-07222 Rev. *A*
Page 6 of 14
PRELIMINARY
W215B
I/O APIC Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
%
f
Frequency generated by crystal oscillator
14.31818
tR
tF
tD
fST
1
1
4
4
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
45
50
15
55
1.5
Frequency Stabilization
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
Ω
REF0 Clock Output (Lump Capacitance Test Load = 45 pF)
CPU = 100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Min.
Typ. Max. Unit
f
Frequency generated by crystal oscillator
14.318
MHz
V/ns
V/ns
%
tR
1
1
4
4
tF
tD
Measured on rising and falling edge at 1.5V
45
50
55
1.5
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within 1 ms
ms
Power-up (cold start)
from power-up. Short cycles exist prior to
frequency stabilization.
www.DataSheet4U.com
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
16
Ω
REF1 Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Min.
Typ. Max. Unit
f
Frequency generated by crystal oscillator
14.318
MHz
V/ns
V/ns
%
tR
0.5
0.5
45
2
2
tF
tD
Measured on rising and falling edge at 1.5V
55
1.5
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within 1 ms
ms
Power-up (cold start)
from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
25
Ω
Document #: 38-07222 Rev. *A*
Page 7 of 14
PRELIMINARY
W215B
48-/24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 100 MHz
Parameter
Description
PLL Ratio
Test Condition/Comments
Min.
Typ.
Max. Unit
m/n
tR
57/17
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
tD
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
50
25
55
3
fST
Frequency Stabilization
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
ms
quency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Ω
AC Electrical Characteristics (Transmission Line Model)
TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (3.135–3.465V), fXTL = 14.31818 MHz, VDDQ2 = 3.3±5%
AC clock parameters are tested and guaranteed over stated operating conditions using the stated transmission line load at the
clock output.
22 Ohm
6 inches 60 Ohm trace
www.DataSheet4U.com
FTG
CPU Clock Outputs, CPU0:3 (Test Load: R = 33Ω; C = 22 pF)
CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Min. Typ. Max. Unit
tP
f
Period
10
100
5
ns
MHz
ns
Frequency, Actual
High Time
tH
tL
Low Time
5
ns
tR
tF
tD
tJC
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
1
1
4
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
45
50
10
55
250
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
ps
tSK
fST
Output Skew
Measured on rising edge at 1.5V
250
3
ps
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
Power-up (cold start)
ms
from power-up. Short cycles exist prior to frequency
stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
Ω
Document #: 38-07222 Rev. *A*
Page 8 of 14
PRELIMINARY
W215B
SDRAM Clock Outputs, SDRAM0:7 (Test Load: R = 22Ω; C = 22 pF)
CPU = 100 MHz
Min. Typ. Max. Unit
Parameter
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Determined by PLL divider ratio
Measured from 0.4V to 2.4V
tP
f
Period
10
ns
MHz
V/ns
V/ns
%
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
100
tR
tF
tD
tJC
1
1
4
4
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
45
50
55
250
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum differ-
ence of cycle time between two adjacent cycles.
ps
tSK
tSK
Output Skew
Measured on rising edge at 1.5V
100
ps
ps
CPU to SDRAM Clock Skew Covers all CPU/SDRAM outputs. Measured on
rising edge at 1.5V.
850
3
fST
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
ms
Power-up (cold start)
from power-up. Short cycles exist prior to frequency
stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
16
Ω
PCI Clock Outputs, PCI0:5 (Test Load: R = 22Ω; C = 22 pF)
CPU = 100 MHz
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Min.
Typ.
30
Max.
Unit
ns
tP
f
www.DataSheet4U.com
Frequency, Actual
High Time
Determined by PLL divider ratio
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
33.3
MHz
ns
tH
tL
12
12
1
Low Time
ns
tR
tF
tD
tJC
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
1
Measured on rising and falling edge at 1.5V
45
50
55
250
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
ps
difference of cycle time between two adjacent cycles.
tSK
tO
Output Skew
Measured on rising edge at 1.5V
250
4
ps
ns
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
15
Ω
Document #: 38-07222 Rev. *A*
Page 9 of 14
PRELIMINARY
W215B
I/O APIC Clock Output (Test Load: R = 33Ω; C = 22 pF)
CPU = 100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Min.
Typ.
Max.
Unit
MHz
V/ns
V/ns
%
f
Frequency generated by crystal oscillator
14.31818
tR
tF
tD
fST
1
1
4
4
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within
45
50
15
55
1.5
Frequency Stabilization
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination value.
Ω
REF0 Clock Output (Test Load: R = 33Ω; C = 22 pF)
CPU = 100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ. Max. Unit
f
14.318
MHz
V/ns
V/ns
%
tR
1
1
4
4
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
45
50
55
1.5
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within 1 ms
ms
Power-up (cold start)
from power-up. Short cycles exist prior to
frequency stabilization.
www.DataSheet4U.com
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
16
Ω
REF1 Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 100 MHz
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Min.
Typ. Max. Unit
f
Frequency generated by crystal oscillator
14.318
MHz
V/ns
V/ns
%
tR
0.5
0.5
45
2
2
tF
tD
Measured on rising and falling edge at 1.5V
55
1.5
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within 1 ms
ms
Power-up (cold start)
from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
25
Ω
Document #: 38-07222 Rev. *A*
Page 10 of 14
PRELIMINARY
W215B
48-/24-MHz Clock Output (Test Load: R = 33Ω; C = 22 pF)
CPU = 100 MHz
Parameter
Description
PLL Ratio
Test Condition/Comments
Min.
Typ.
Max. Unit
m/n
tR
57/17
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
tD
Measured on rising and falling edge at 1.5V
Assumes full supply voltage reached within 1 ms
50
25
55
3
fST
Frequency Stabilization
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
ms
quency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Ω
Ordering Information
Package
Name
Ordering Code
Package Type
W215B
X
48-pin TSSOP (6.1 mm)
www.DataSheet4U.com
Document #: 38-07222 Rev. *A*
Page 11 of 14
PRELIMINARY
W215B
Layout Example
+2.5V Supply
FB
+3.3V Supply
FB
VDDQ2
VDDQ3
10 µF
0.005 µF
10 µF
C4 0.005 µF
G
C1
C2
C3
G
G
G
G
G
1
2
3
4
G
48
47
46
V
G
G
G
G 45
44
5
43
6
7
8
9
G
V
42
G
G
41
V
40
10 G
11
G
39
38
37
36
12
www.DataSheet4U.com
13
G
G
14
35
VDDQ3
V
G
V
15
34
Core
16G
17
33
G
32
G 31
30
18
19
VDDQ3
G
20
G
29
28
5Ω
V
G
G
21
22
23
G 27
26
C6
G
C5
G
V
24
G
25
G
FB = Dale ILB1206 - 300 (300Ω @ 100 MHz)
µF
C6 = 0.1
V =VIA to respective supply plane layer
Note: Each supply plane or strip should have a ferrite bead and capacitors
µF
µF
C2 & C4 = 0.005
C5 = 47 µF
C1 & C3 = 10–22
= VIA to GND plane layer
G
Document #: 38-07222 Rev. *A*
Page 12 of 14
PRELIMINARY
W215B
Package Diagram
48-Pin Small Shrink Outline Package (TSSOP, 6.1 mm)
www.DataSheet4U.com
Document #: 38-07222 Rev. *A*
Page 13 of 14
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
PRELIMINARY
W215B
Document Title: W215B Notebook PC System Frequency Generator for K6 Processors
Document Number: 38-07222
Issue
Orig. of
Change
REV.
**
ECN NO. Date
Description of Change
110487
122839
10/21/01
12/15/02
SZV
RBI
Change from Spec number: 38-00886 to 38-07222
Added power-up requirements to maximum ratings information.
*A
www.DataSheet4U.com
Document #: 38-07222 Rev. *A*
Page 14 of 14
相关型号：
©2020 ICPDF网 联系我们和版权申明