MTE2D0N04E3-0-UB-X [CYSTEKEC]
N-Channel Enhancement Mode Power MOSFET;
| 型号： | MTE2D0N04E3-0-UB-X |
| 厂家： | 
CYSTECH ELECTONICS CORP. |
| 描述： | N-Channel Enhancement Mode Power MOSFET |
| 文件： | 总8页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Spec. No. : C072E3
Issued Date : 2016.03.04
Revised Date :
CYStech Electronics Corp.
Page No. : 1/ 8
N-Channel Enhancement Mode Power MOSFET
MTE2D0N04E3
BVDSS
ID@VGS=10V, TC=25°C
40V
84A
17.3A
Features
ID@VGS=10V, TA=25°C
RDS(ON)@VGS=10V, ID=20A
• Low On Resistance
• Simple Drive Requirement
• Low Gate Charge
2.0 mΩ(typ)
• Fast Switching Characteristic
• RoHS compliant package
Symbol
Outline
TO-220
MTE2D0N04E3
G D S
G：Gate D：Drain S：Source
Ordering Information
Shipping
Device
Package
TO-220
(RoHS compliant)
MTE2D0N04E3-0-UB-X
50 pcs/tube, 20 tubes/box, 4 boxes / carton
Environment friendly grade : S for RoHS compliant products, G for RoHS compliant
and green compound products
Packing spec, UB : 50 pcs / tube, 20 tubes/box
Product rank, zero for no rank products
Product name
MTE2D0N04E3
CYStek Product Specification
Spec. No. : C072E3
Issued Date : 2016.03.04
Revised Date :
CYStech Electronics Corp.
Page No. : 2/ 8
Absolute Maximum Ratings (TC=25°C)
Parameter
Symbol
Limits
Unit
Drain-Source Voltage (Note 1)
Gate-Source Voltage
Continuous Drain Current @TC=25°C, VGS=10V (silicon limit) (Note 5)
Continuous Drain Current @TC=100°C, VGS=10V(silicon limit) (Note 5)
Continuous Drain Current @TC=25°C, VGS=10V (package limit) (Note 1)
VDS
VGS
40
±30
165
117
84
V
ID
A
17.3
13.8
584
50
Continuous Drain Current @TA=25°C, VGS=10V
Continuous Drain Current @TA=70°C, VGS=10V
Pulsed Drain Current
(Note 2)
IDSM
(Note 2)
IDM
IAS
Single Pulse Avalanche Current
Single Pulse Avalanche Energy @ L=1mH, ID=50 Amps, VDD=30V
EAS
EAR
1250
(Note 4)
mJ
W
Repetitive Avalanche Energy
(Note 3)
(Note 1)
(Note 1)
(Note 2)
(Note 2)
16
166
83
2.1
1.3
TC=25°C
TC=100°C
TA=25°C
TA=70°C
PD
Power Dissipation
PDSM
Maximum Temperature for Soldering @ Lead at 0.063 in(1.6mm)
from case for 10 seconds
Maximum Temperature for Soldering @ Package Body for 10 seconds
TL
300
260
°C
TPKG
Operating Junction and Storage Temperature
Tj, Tstg -55~+175
*Drain current limited by maximum junction temperature
Thermal Data
Parameter
Thermal Resistance, Junction-to-case, max
Thermal Resistance, Junction-to-ambient, max (Note 2)
Symbol
RθJC
RθJA
Value
0.9
60
Unit
°C/W
°
.
Note : 1 The power dissipation PD is based on TJ(MAX)=175 C, using junction-to-case thermal resistance, and is more useful
in setting the upper dissipation limit for cases where additional heatsinking is used.
.
2 The value of RθJA is measured with the device mounted on 1 in²FR-4 board with 2 oz. copper, in a still air
°
environment with TA=25 C. The power dissipation PDSM is based on RθJA and the maximum allowed junction
temperature of 150°C. The value in any given application depends on the user’s specific board design, and the
maximum temperature of 175°C may be used if the PCB allows it.
3. Pulse width limited by junction temperature TJ(MAX)=175°C.
°
4. Ratings are based on low frequency and low duty cycles to keep initial TJ=25 C. 100% tested by conditions of VDD=30V,
ID=20A, L=1mH, VGS=10V.
5. Calculated continuous drain current based on maximum allowable junction temperature.
6. The static characteristics are obtained using <300μs pulses, duty cycle 0.5% maximum.
7. The RθJA is the sum of thermal resistance from junction to case RθJC and case to ambient.
MTE2D0N04E3
CYStek Product Specification
Spec. No. : C072E3
Issued Date : 2016.03.04
Revised Date :
CYStech Electronics Corp.
Page No. : 3/ 8
Characteristics (Tj=25°C, unless otherwise specified)
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Static
BVDSS
40
-
2
-
-
-
-
32
-
31.5
-
-
-
2.0
-
-
4
-
100
1
5
V
VGS=0V, ID=250μA
∆BVDSS/∆Tj
VGS(th)
*GFS
mV/°C Reference to 25°C, ID=250μA
V
S
nA
VDS = VGS, ID=250μA
VDS =10V, ID=20A
±
±
IGSS
VGS= 30V
VDS =40V, VGS =0V
VDS =32V, VGS =0V, Tj=55°C
VGS =10V, ID=20A
IDSS
μA
-
-
Ω
m
*RDS(ON)
2.6
Dynamic
*Qg
*Qgs
*Qgd
*td(ON)
*tr
*td(OFF)
*tf
Ciss
-
-
-
-
-
-
-
-
-
-
-
114
33
37
-
-
-
-
-
-
-
-
-
-
-
nC
VDS=20V, VGS=10V, ID=84A
41.8
30.4
71.8
24
5867
862
398
0.6
VDS=20V, ID=20A, VGS=10V,
ns
Ω
RGS=2.7
pF
VGS=0V, VDS=25V, f=1MHz
f=1MHz
Coss
Crss
Rg
Ω
Source-Drain Diode
*IS
*ISM
*VSD
*trr
-
-
-
-
-
-
-
84
584
1
-
-
A
0.69
18
36
V
ns
nC
IS=1A, VGS=0V
VGS=0V, IF=20A, dIF/dt=100A/μs
*Qrr
*Pulse Test : Pulse Width ≤300μs, Duty Cycle≤2%
MTE2D0N04E3
CYStek Product Specification
Spec. No. : C072E3
Issued Date : 2016.03.04
Revised Date :
CYStech Electronics Corp.
Page No. : 4/ 8
Typical Characteristics
Brekdown Voltage vs Ambient Temperature
Typical Output Characteristics
1.4
1.2
1
160
10V, 9V, 8V, 7V
140
120
100
80
0.8
0.6
0.4
60
6
V
40
I =250 A,
μ
GS=0V
D
V
20
VGS=5.5V
4
0
0
0.1
0
1
2
3
5
-75 -50 -25
0
25 50 75 100 125 150 175 200
Tj, Junction Temperature(°C)
VDS, Drain-Source Voltage(V)
Static Drain-Source On-State resistance vs Drain Current
Reverse Drain Current vs Source-Drain Voltage
100
10
1
1.2
1
0.8
0.6
0.4
0.2
Tj=25°C
VGS=4.5V
Tj=150°C
VGS=10V
1
10
100
0
4
8
12
16
20
ID, Drain Current(A)
IDR, Reverse Drain Current(A)
Drain-Source On-State Resistance vs Junction Tempearture
Static Drain-Source On-State Resistance vs Gate-Source
Voltage
50
40
30
20
10
0
2.4
2
VGS=10V, ID=20A
ID=20A
1.6
1.2
0.8
0.4
0
RDS(ON)@Tj=25°C :2mΩ typ.
-75 -50 -25
0
25 50 75 100 125 150 175 200
2
4
6
8
10
VGS, Gate-Source Voltage(V)
Tj, Junction Temperature(°C)
MTE2D0N04E3
CYStek Product Specification
Spec. No. : C072E3
Issued Date : 2016.03.04
Revised Date :
CYStech Electronics Corp.
Page No. : 5/ 8
Typical Characteristics(Cont.)
Threshold Voltage vs Junction Tempearture
Capacitance vs Drain-to-Source Voltage
10000
1.4
1.2
1
Ciss
ID=1mA
C
oss
0.8
0.6
0.4
0.2
1000
ID=250μA
Crss
100
-75 -50 -25
0
25 50 75 100 125 150 175 200
0
5
10
15
20
25
30
VDS, Drain-Source Voltage(V)
Tj, Junction Temperature(°C)
Forward Transfer Admittance vs Drain Current
Gate Charge Characteristics
100
10
VDS=20V
8
6
4
2
0
10
1
VDS=32V
VDS=10V
Pulsed
0.1
0.01
Ta=25°C
ID=84A
0
20
40
60
80
100
120
140
0.001
0.01
0.1
1
10
100
ID, Drain Current(A)
Total Gate Charge---Qg(nC)
Maximum Drain Current vs Case Temperature
Silicon Limit
Maximum Safe Operating Area
200
180
160
140
120
100
80
1000
RDS(ON)
Limited
10 s
μ
100 s
μ
100
10
1
1ms
10ms
100ms
DC
Package Limit
60
TC=25°C, Tj=175°C,
JC
40
VGS=10V, R =0.9°C/W
θ
JC
VGS=10V, Rθ =0.9°C/W
Single Pulse
20
0
0.1
25
50
75
100 125 150 175 200
0.1
1
10
100
V
DS, Drain-Source Voltage(V)
TC, Case Temperature(°C)
MTE2D0N04E3
CYStek Product Specification
Spec. No. : C072E3
Issued Date : 2016.03.04
Revised Date :
CYStech Electronics Corp.
Page No. : 6/ 8
Typical Characteristics(Cont.)
Typical Transfer Characteristics
Single Pulse Maximum Power Dissipation
160
140
120
100
80
3000
2500
2000
1500
1000
500
VDS=10V
TJ(MAX)=175°C
TC=25°C
R
JC=0.9°C/W
θ
60
40
20
0
0
1E-05 0.0001 0.001 0.01
0.1
1
10
0
2
4
6
GS, Gate-Source Voltage(V)
8
10
V
Pulse Width(s)
Transient Thermal Response Curves
1
D=0.5
JC
JC
1.Rθ (t)=r(t)*Rθ
0.2
1
2
2.Duty Factor, D=t /t
JM
C
DM
JC
3.T -T =P *Rθ (t)
JC
4.Rθ =0.9 °C/W
0.1
0.1
0.05
0.02
0.01
Single Pulse
0.01
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
t1, Square Wave Pulse Duration(s)
MTE2D0N04E3
CYStek Product Specification
Spec. No. : C072E3
Issued Date : 2016.03.04
Revised Date :
CYStech Electronics Corp.
Page No. : 7/ 8
Recommended wave soldering condition
Product
Peak Temperature
Soldering Time
5 +1/-1 seconds
Pb-free devices
260 +0/-5 °C
Recommended temperature profile for IR reflow
Profile feature
Average ramp-up rate
(Tsmax to Tp)
Sn-Pb eutectic Assembly
Pb-free Assembly
3°C/second max.
3°C/second max.
Preheat
−Temperature Min(TS min)
−Temperature Max(TS max)
−Time(ts min to ts max)
100°C
150°C
60-120 seconds
150°C
200°C
60-180 seconds
Time maintained above:
−Temperature (TL)
− Time (tL)
183°C
60-150 seconds
217°C
60-150 seconds
Peak Temperature(TP)
240 +0/-5 °C
260 +0/-5 °C
Time within 5°C of actual peak
temperature(tp)
10-30 seconds
20-40 seconds
Ramp down rate
6°C/second max.
6°C/second max.
6 minutes max.
8 minutes max.
Time 25 °C to peak temperature
Note : All temperatures refer to topside of the package, measured on the package body surface.
MTE2D0N04E3
CYStek Product Specification
Spec. No. : C072E3
Issued Date : 2016.03.04
Revised Date :
CYStech Electronics Corp.
Page No. : 8/ 8
TO-220 Dimension
Marking:
4
E2D0
N04
□□□□
Device Name
Date Code
1 2 3
3-Lead TO-220 Plastic Package
Style: Pin 1.Gate 2.Drain 3.Source
4.Drain
CYStek Package Code: E3
*: Typical
Millimeters
Inches
Min.
Millimeters
Min. Max.
2.540*
4.980
2.650
7.900
0.000
Inches
DIM
DIM
Min.
Max.
4.600
2.550
0.910
1.370
0.650
1.400
10.250
9.750
Max.
0.181
0.100
0.036
0.054
0.026
0.055
0.404
0.384
Min.
Max.
A
A1
b
b1
c
c1
D
E
4.400
2.250
0.710
1.170
0.330
1.200
9.910
8.950
0.173
0.089
0.028
0.046
0.013
0.047
0.390
0.352
e
e1
F
H
h
L
L1
V
0.100*
5.180
2.950
8.100
0.300
0.196
0.104
0.311
0.000
0.508
0.112
0.204
0.116
0.319
0.012
0.528
0.128
12.900 13.400
2.850
3.250
7/500 REF
0.295 REF
Φ
12.950
0.510
E1
12.650
0.498
3.400
3.800
0.134
0.150
Notes: 1.Controlling dimension: millimeters.
2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material.
3.If there is any question with packing specification or packing method, please contact your local CYStek sales office.
Material:
• Lead: Pure tin plated.
• Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0.
Important Notice:
• All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
• CYStek reserves the right to make changes to its products without notice.
• CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
• CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.
MTE2D0N04E3
CYStek Product Specification
相关型号：
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