PI6CV847L [DIODES]
Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 0.173 INCH, TSSOP-24;
| 型号： | PI6CV847L |
| 厂家： | 
DIODES INCORPORATED |
| 描述： | Clock Driver, 6C Series, 5 True Output(s), 0 Inverted Output(s), PDSO24, 0.173 INCH, TSSOP-24 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总9页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PI6CV847
200MHz PLL Clock Driver
Features
Description
• PLLclockdistributionoptimizedforSSTL_2
ThePI6CV847PLLClockBufferisdesignedfor2.5V
and2.5V
DDQ
• Distributes one differential clock input pair to five differential
clock output pairs.
AV operation and differential data input and output levels. The
DD
deviceisazerodelaybufferthatdistributesadifferentialclockinput
pair (CLK, CLK) to five differential pairs of clock outputs (Y[0:4],
Y[0:4]) and one differential pair feedback clock outputs (FBOUT,
FBOUT).Theclockoutputsarecontrolledbytheinputclocks(CLK,
CLK),thefeedbackclocks(FBIN,FBIN),andtheAnalogPowerinput
• Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2
• Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2
• Externalfeedbackpins(FBIN,FBIN)areusedto
synchronize the outputs to the input clocks.
(AV ). WhentheAV isstrappedlow, thePLListurnedoffand
DD
DD
• Operates at AV = 2.5V for core circuit and internal PLL,
DD
bypassed for test purposes.
and V = 2.5V for differential output drivers
DD
ThePI6CV847isabletotrackSpreadSpectrumClockingtoreduce
EMI.
• Packaging(Pb-free&Greenavailable):
-24-pinTSSOP(L24)
PinConfiguration
BlockDiagram
GND
Y0
1
24
23
22
21
20
19
18
17
16
15
14
13
Y4
Y0
2
Y4
Y0
Y1
Y0
3
Y3
CLK
CLK
GND
VDD
CLKIN
CLKIN
AVDD
AGND
Y1
4
Y3
Y1
Y2
5
VDD
FBIN
FBIN
FBOUT
FBOUT
Y2
PLL
FBIN
24-Pin
L
Y2
Y3
6
FBIN
7
Y3
Y4
8
9
Y4
Logic
and
Test Ciruit
10
11
12
FBOUT
FBOUT
Y1
Y2
AV
DD
VDD
GND
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PI6CV847
2.5V 200MHz PLL Clock Driver
PinoutTable
Pin
Name
I/O
Type
Pin No.
Description
CLK
CLK
6
7
I
Reference Clock, and Complement Reference Clock input.
Y[0:4]
Y[0:4]
3,11,15,21,24
2,10,14,22,23
Clock outputs.
Complement Clock outputs.
O
FBOUT
FBOUT
16
17
Feedback output, and Complement Feedback Output
FBIN
FBIN
19
18
I
Feedback input, and Complement Feedback input
Power Supply for I/O pins.
VDD
5,12,20
8
Power
Analog/core power supply. AVDD can be used to bypass the PLL for testing purposes. When
AVDD is strapped to ground, PLL is bypassed & CLK is buffered directly to the device outputs.
AVDD
AGND
GND
9
Analog/core ground. Provides the ground reference for the analog/core circuitry
Ground for I/O pins.
Ground
1,14,13
FunctionTable
Inputs
Outputs
FBOUT
PLL State
AV
CLK
L
CLK
H
Y[0:4]
Y[0:4]
FBOUT
DD
GND
GND
L
H
L
H
L
H
L
L
H
L
H
L
H
L
Bypassed/Off
Bypassed/Off
On
H
L
2.5V(nom)
2.5V(nom)
L
H
H
L
H
H
On
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PI6CV847
2.5V 200MHz PLL Clock Driver
Absolute Maximum Ratings(Over operating free-air temperature range)
Symbol
, AV
Parameter
I/O supply voltage range and analog/core supply voltage range
Input voltage range
Min.
– 0.5
– 0.5
– 0.5
– 65
0
Max.
Units
V
DDQ
4.6
DD
V
I
V
V
+0.5
DDQ
V
O
Output voltage range
Tstg
Ta
Storage temperature
150
85
o
C
Ambient Operating Temperature
Note: Stress beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
o
TimingRequirements(Ta=0-85 C)
AVDD, VDDQ= 2.5V ±0.2V
Symbol
Description
Units
Min.
95
Max.
200
60
o
fCK
tDC
Operating clock frequency , 25 C
MHz
%
Input clock duty cycle
40
tSTAB
PLL stabilization time after powerup
15
μs
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PI6CV847
2.5V 200MHz PLL Clock Driver
DCSpecifications
Recommended Operating Conditions (please refer to note 1)
Symbol
Parameter
Analog core supply voltage
Min.
2.3
Nom.
2.5
Max.
2.7
Units
AV
DD
V
DD
Output supply voltage
2.3
2.5
2.7
V
Input differential-pair crossing voltage (note 4)
Output differential-pair crossing voltage (note 4)
DC Input voltage level (note 2)
DC Input differential voltage
(V /2) – 0.2
(V /2) + 0.2
DD
IX
DD
V
OX
(V /2) – 0.15
DD
(V /2) + 0.15
DD
V
V
IN
–0.3
0.36
0.7
0.7
0
V
DD
V
DD
V
DD
V
DD
+0.3
+0.6
+0.6
+0.6
V
ID
(note 3)
AC Input differential voltage
V
OD
Output differential voltage
T
Operating free air temperature
85
°C
A
Notes:
1. Unused inputs must be held high or low, do not leave them floating.
2. DC input voltage specifies the DC component of the differential inputs.
3. Vid specifies the differential amplitude (Vtrue-Vcomplement) needed for switching.
4. Vox is expected to track Vdd variations. It is the xepected crossing voltage required by the input.
o
Electrical Characteristics (Ta = 0 - 85 C, Vdd = 2.5V +/- 0.2V)
Parameter
All inputs
Test Conditions
II = –18mA
Min.
Typ.
Max.
–1.2
±10
Units
VIK
II
V
CLK, FBIN
VI = VDDQ or GND
CL = 0pF, 200MHz
μA
mA
IDD2.5
200
Operating Supply Current
IDDPD
IOZ
CL = 0pF
100
±10
0.1
uA
High Impedance Output Current
Low Output Voltage
VDD = 2.7V, VOUT = VDD or GND
IOL = 1mA
mA
VOL
V
V
I
OL = 12mA
IOH = -1mA
OH = -12mA
0.6
VDD -0.1
1.7
VOH
High Output Voltage
I
CLK and CLK
FBIN and FBIN
(1)
CI
VI = VDD or GND
2.5
3.5
pF
Notes:
1. Guaranteed by design @ 233MHz, not production tested
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PI6CV847
2.5V 200MHz PLL Clock Driver
AC Specifications (see Note 3)
Switching characteristics over recommended operating free-air temperature range, fCLK > 100 MHz (unless otherwise noted).
(See Figure 1 and 2)
Notes:
1. Transition of non-inverting output in PLL bypass mode
2. Pulse skew is constant over the application frequency range, but duty cycle error increases with frequency.
[duty cycle = twH/tc (high pulse width / cycle period); tc decreases as frequency increases]
3. Switching characteristics is guaranteed over application frequency range
4. Static phase offset shifted by design
5. Spread spectrum off
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PI6CV847
2.5V 200MHz PLL Clock Driver
V
DD
Yx
R = 60-Ohm
R = 60-Ohm
V
/2
DD
Yx
Figure1.IBISModelOutputLoad
V
/2
DDQ
Z = 60Ω
Z = 50Ω
Z = 50Ω
R =10Ω
C=14pF
R = 50Ω
R = 50Ω
–V
/2
DDQ
Z = 60Ω
R =10Ω
C=14pF
–V
/2
DDQ
SCOPE
–V
/2
DDQ
Figure2.OutputLoadTestCircuit
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PI6CV847
2.5V 200MHz PLL Clock Driver
Yx,FBOUT
Yx,FBOUT
tcycle n
tjit(cc) tcycle n
tcycle n+1
=
-
tcycle n+1
Figure3.Cycle-to-CycleJitter
CLK
CLK
FBIN
FBIN
t(
t(
)
n
)
n+1
n=N
1
t(
∑
) n
t
=
(N is a large number of samples)
N
Figure 4. Static Phase Offset
Yx
Yx
Yx, FBOUT
Yx, FBOUT
tsk(o)
Figure5.OutputSkew
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PI6CV847
2.5V 200MHz PLL Clock Driver
Yx, FBOUT
Yx, FBOUT
tcycle n
Yx, FBOUT
Yx, FBOUT
1
fO
1
fO
t jit(per)
=
tcycle n
Figure 6. Period Jitter
Yx, FBOUT
Yx, FBOUT
t n+1
thalf period n
half period
1
fO
1
2*fO
tjit(hper)
=
thalf period n
Figure7.Half-PeriodJitter
VDDQ
80%
80%
20%
20%
Clock Inputs
and Outputs
0V
tsl(i), sl(o)
t
tsl(i), tsl(o)
Figure8.InputandOutputSlewRates
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PI6CV847
2.5V 200MHz PLL Clock Driver
PackagingMechanical:24-PinTSSOP(L24)
24
.169
.177
4.3
4.5
0.09
0.20
.004
.008
1
.303
.311
0.45 .018
0.75 .030
7.7
7.9
.047
1.20
Max
.252
BSC
6.4
SEATING
PLANE
.002
.006
0.05
0.15
.007
.012
0.19
0.30
.0256
BSC
0.65
OrderingInformation
OrderingCode
PI6CV847L
PackageCode
PackageType
L
L
24-pin173-milwideTSSOP
PI6CV847LE
Pb-free&Green,24-pin173-milwideTSSOP
Notes:
1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/
Pericom Semiconductor Corporation • 1-800-435-2336 • www.pericom.com
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