IE-703107-MC-EM1_技术文档

User’s Manual

IE-703107-MC-EM1

In-Circuit Emulator Option Board

Target Devices

V850E/MA1

V850E/MA2

Document No. U14481EJ2V0UM00 (2nd edition)

Date Published September 2003 N CP(K)

©

Printed in Japan

[MEMO]

User’s Manual U14481EJ2V0UM

2

Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States

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The information in this document is current as of February, 2003. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

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M8E 02. 11-1

User’s Manual U14481EJ2V0UM

3

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

Electronics product in your application, pIease contact the NEC Electronics office in your country to

obtain a list of authorized representatives and distributors. They will verify:

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Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

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Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

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J03.4

User’s Manual U14481EJ2V0UM

4

Major Revisions in This Edition (1/2)

Page

Throughout

p.14

Description

Addition of V850E/MA2 to target devices

1.1 Hardware Configuration

• Addition of SWEX-xxxSD-1 to extension probes

• Addition of conversion socket for V850E/MA1 (161-pin FBGA)

• Addition of conversion socket for V850E/MA2 (100-pin LQFP)

p.15

Change of 1.2 Features (When Connected to IE-V850E-MC-A) to 1.2 Hardware Specifications (When

Connected to IE-V850E-MC-A)

p.16

Change of 1.3 Function Specifications (When Connected to IE-V850E-MC-A) to 1.3 System

Specifications of IE-703107-MC-EM1 (When Connected to IE-V850E-MC-A)

pp.17 to 19

1.4 System Configuration

• Change of Figure 1-1 System Configuration to Figure 1-1 System Configuration (V850E/MA1, 144-

Pin LQFP)

• Addition of Figure 1-2 System Configuration (V850E/MA1, 161-Pin FBGA)

• Addition of Figure 1-3 System Configuration (V850E/MA2, 100-Pin LQFP)

p.20

1.5 Contents in Carton

• Addition and modification of description

• Modification of Figure 1-4 Contents in Carton

p.21

Modification of Figure 1-5 Connection Between IE-V850E-MC-A and IE-703107-MC-EM1

pp.24, 25

2.1 Names and Functions of IE-703107-MC-EM1 Components

• Modification of Figure 2-1 IE-703107-MC-EM1

• Addition and modification of description in (6) to (10)

pp.26 to 30

2.2 Clock Settings

• Addition and modification of description

• Addition of Figure 2-2 Outline of Clock Settings

• Change of Table 2-1 Clock Setting (When the Emulator is Used as a Stand-Alone Unit) to Table 2-1

List of Hardware Settings for Each Clock Setting

• Change of Table 2-2 Clock Setting (When the Emulator is Used in Target System Connection) to

Table 2-2 Settings When Using Mounted Internal Clock

• Addition of Figure 2-3 Outline When Using Mounted Internal Clock

• Addition of Table 2-3 Settings When Changing Mounted Internal Clock

• Addition of Figure 2-4 Outline When Changing Mounted Crystal Oscillator and Using It as Internal

Clock

• Addition of Table 2-4 Settings When Using External Clock

• Addition of Figure 2-5 Outline When Using Crystal Oscillator on Target System as External Clock

p.31

Change of 2.3 MODE Pin Setting to 2.3 Operation Mode Settings

Addition and modification of description in 2.4 Power Supply Settings

Addition of 2.5 Emulation Memory

p.32

pp.33, 34

p.35

Addition and modification of description in CHAPTER 3 FACTORY SETTINGS

Addition and modification of description in CHAPTER 4 CAUTIONS

pp.36, 37

pp.38 to 50

Addition of CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE

CIRCUITS

pp.51 to 68

pp.69 to 71

A.1 Corresponding Package Dimensions

• Modification of (1)

• Addition of (3) to (5) and (9) to (18)

A.2 Conditions for Connecting of In-Circuit Emulator Option Board and Conversion Connector

• Addition of (1) to (3)

User’s Manual U14481EJ2V0UM

5

Major Revisions in This Edition (2/2)

Page

Description

p.72

APPENDIX B EXAMPLE OF USE OF CONNECTOR FOR TARGET CONNECTION

• Change of (3) Connection between emulator and target system to (2) When connecting device

using connector for target connection (b) FBGA package

pp.73 to 81

APPENDIX C CONNECTORS FOR TARGET CONNECTION

• Addition and modification of description in C.1 Usage (LQFP Package)

• Addition and modification of description in C.2 Cautions on Handling Connectors (LQFP Package)

• Addition of C.3 Notes on Board Design (FBGA Package)

• Addition of C.4 Soldering CSSOCKET (Main Enclosure Connector) to Target Board (FGBA Package)

• Addition of C.5 Using LSPACK to Mount IC (FBGA Package)

• Addition of C.6 Connecting In-Circuit Emulator (FBGA Package)

• Addition of C.7 Notes on Handling LSPACK/CSSOCKET (FBGA Package)

p.82

p.83

Modification of Figure D-1 Method of Inserting Plastic Spacer

Addition of APPENDIX E REVISION HISTORY

The mark shows major revised points.

User’s Manual U14481EJ2V0UM

6

INTRODUCTION

Target Readers

Purpose

This manual is intended for users who design and develop application systems

using the V850E/MA1 and V850E/MA2.

The purpose of this manual is to describe the proper operation of the IE-703107-MC-

EM1, and its basic specifications.

Organization

This manual is broadly divided into the following parts.

• Overview

• Names and functions of components

• Factory settings

• Cautions

• Differences between target devices and target interface circuits

How to Read This Manual

It is assumed that the reader of this manual has general knowledge of electrical

engineering, logic circuits, and microcontrollers.

The IE-703107-MC-EM1 is used connected to the IE-V850E-MC-A in-circuit

emulator. This manual explains the basic setup procedure and switch settings

of the IE-703107-MC-EM1. For the names and functions, and the connection of

parts, refer to the IE-V850E-MC, IE-V850E-MC-A User’s Manual (U14487E),

which is a separate volume.

To understand the basic specifications and operation methods broadly

→ Read this manual in the order listed in CONTENTS.

To know the operation methods and command functions of the IE-V850E-MC-A and

IE-703107-MC-EM1

→ Read the user’s manual of the debugger (separate volume) that is used.

Conventions

Note:

Footnote for item marked with Note in the text

Caution:

Information requiring particular attention

Remark:

Supplementary information

…

Numeral representations:

Binary

×××× or ××××B

…

Decimal

××××

…

Hexadecimal

××××H

Prefixes representing the power of 2 (address space, memory capacity):

K (kilo): 2¹⁰= 1024

M (mega): 2²⁰= 1024²

User’s Manual U14481EJ2V0UM

7

Terminology

The meanings of terms used in this manual are listed below.

This is the device to be emulated.

Target device

Target system

The system (user-built system) to be debugged. This includes the target program and

hardware configured by the user.

Related Documents

When using this manual, refer to the following manuals.

The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

{

Documents related to development tools (user’s manuals)

Product Name

Document Number

U14487E

IE-V850E-MC, IE-V850E-MC-A (In-Circuit Emulator)

IE-703107-MC-EM1 (In-Circuit Emulator Option Board)

V850E/MA1 Hardware

This manual

U14359E

U14980E

U16544E

V850E/MA2 Hardware

V850 Series Development Tools (Supporting 32-Bit OS) Windows^TM

Based (Application Note)

Tutorial Guide

CA850 (C Compiler Package) Ver.2.50

Operation

C Language

PM plus

U16053E

U16054E

U16055E

U16042E

U16217E

U16218E

U13430E

U13410E

U13773E

U13774E

U13737E

U13916E

U14410E

U15260E

Assembly Language

Operation

Basics

ID850 (Ver.2.50 or later) (Integrated Debugger)

SM850 (Ver.2.50 or later) (System Simulator)

RX850 (Real-Time OS)

Installation

Basics

RX850 Pro (Real-Time OS)

Installation

RD850 (Ver. 3.0) (Task Debugger)

RD850 Pro (Ver. 3.0) (Task Debugger)

AZ850 (System Performance Analyzer)

PG-FP4 (Flash Memory Programmer)

User’s Manual U14481EJ2V0UM

8

CONTENTS

CHAPTER 1 OVERVIEW..........................................................................................................................13

1.1 Hardware Configuration.............................................................................................................14

1.2 Hardware Specifications (When Connected to IE-V850E-MC-A) ...........................................15

1.3 System Specifications of IE-703107-MC-EM1 (When Connected to IE-V850E-MC-A) .........16

1.4 System Configuration.................................................................................................................17

1.5 Contents in Carton......................................................................................................................20

1.6 Connection Between IE-V850E-MC-A and IE-703107-MC-EM1 ..............................................21

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS............................................................23

2.1 Names and Functions of IE-703107-MC-EM1 Components....................................................24

2.2 Clock Settings.............................................................................................................................26

2.2.1

2.2.2

Outline of clock settings ................................................................................................................. 26

Clock setting methods.................................................................................................................... 27

2.3 Operation Mode Settings ...........................................................................................................31

2.4 Power Supply Settings...............................................................................................................32

2.4.1

JP2 setting when emulator operates as stand-alone unit............................................................... 32

2.5 Emulation Memory......................................................................................................................33

2.5.1

2.5.2

Wait setting for emulation memory................................................................................................. 33

Cautions related to emulation memory........................................................................................... 34

CHAPTER 3 FACTORY SETTINGS .......................................................................................................35

CHAPTER 4 CAUTIONS ..........................................................................................................................36

4.1 Cautions on Terminating Pins...................................................................................................36

4.2 Notes on Internal RAM ...............................................................................................................37

CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE

CIRCUITS............................................................................................................................38

APPENDIX A DIMENSIONS.....................................................................................................................51

A.1 Corresponding Package Dimensions.......................................................................................51

A.2 Conditions for Connecting of In-Circuit Emulator Option Board and

Conversion Connector ...............................................................................................................69

APPENDIX B EXAMPLE OF USE OF CONNECTOR FOR TARGET CONNECTION....................72

APPENDIX C CONNECTORS FOR TARGET CONNECTION.............................................................73

C.1 Usage (LQFP Package)...............................................................................................................73

C.2 Cautions on Handling Connectors (LQFP Package)...............................................................75

C.3 Notes on Board Design (FBGA Package).................................................................................76

C.4 Soldering CSSOCKET (Main Enclosure Connector) to Target Board (FBGA Package) .....77

C.5 Using LSPACK to Mount IC (FBGA Package)..........................................................................79

User’s Manual U14481EJ2V0UM

9

C.6 Connecting In-Circuit Emulator (FBGA Package) ...................................................................80

C.7 Notes on Handling LSPACK/CSSOCKET (FBGA Package)....................................................81

APPENDIX D INSERTING PLASTIC SPACER .....................................................................................82

APPENDIX E REVISION HISTORY.........................................................................................................83

User’s Manual U14481EJ2V0UM

10

LIST OF FIGURES

Figure No.

Title

Page

1-1

1-2

1-3

1-4

1-5

System Configuration (V850E/MA1, 144-Pin LQFP) ........................................................................................17

System Configuration (V850E/MA1, 161-Pin FBGA)........................................................................................18

System Configuration (V850E/MA2, 100-Pin LQFP) ........................................................................................19

Contents in Carton............................................................................................................................................20

Connection Between IE-V850E-MC-A and IE-703107-MC-EM1 ......................................................................21

2-1

2-2

2-3

2-4

2-5

2-6

2-7

IE-703107-MC-EM1..........................................................................................................................................24

Outline of Clock Settings .................................................................................................................................26

Outline When Using Mounted Internal Clock ....................................................................................................28

Outline When Changing Mounted Crystal Oscillator and Using It as Internal Clock .........................................29

Outline When Using Crystal Oscillator on Target System as External Clock....................................................30

Setting of JP2 (for Automatic Selection of Power) ............................................................................................32

Setting of JP2 (to Use Power from Target System) ..........................................................................................32

4-1

Schematic Diagram of Power Supply Flow.......................................................................................................37

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

Pin Equivalent Circuit 1.....................................................................................................................................38

Pin Equivalent Circuit 2.....................................................................................................................................38

Pin Equivalent Circuit 3.....................................................................................................................................44

Pin Equivalent Circuit 4.....................................................................................................................................44

Pin Equivalent Circuit 5.....................................................................................................................................45

Pin Equivalent Circuit 6.....................................................................................................................................45

Pin Equivalent Circuit 7.....................................................................................................................................49

Pin Equivalent Circuit 8.....................................................................................................................................49

Pin Equivalent Circuit 9.....................................................................................................................................50

5-10 Pin Equivalent Circuit 10...................................................................................................................................50

C-1

C-2

C-3

C-4

C-5

C-6

C-7

C-8

Mounting of NQPACK144SD or NQPACK100SD.............................................................................................73

Mounting of Device...........................................................................................................................................74

NQPACK144SD or NQPACK100SD and Device Pin .......................................................................................74

Application of Resist .........................................................................................................................................76

Mounting of CSSOCKET on Target Board .......................................................................................................77

Example of Mounting Profile of CSSOCKET ....................................................................................................78

Mounting of IC ..................................................................................................................................................79

CSICE Connection............................................................................................................................................80

D-1

Method of Inserting Plastic Spacer ...................................................................................................................82

User’s Manual U14481EJ2V0UM

11

LIST OF TABLES

Table No.

Title

Page

1-1

1-2

Hardware Specifications ...................................................................................................................................15

System Specifications of IE-703107-MC-EM1 (When Connected to IE-V850E-MC-A).....................................16

2-1

2-2

2-3

2-4

List of Hardware Settings for Each Clock Setting..............................................................................................27

Settings When Using Mounted Internal Clock...................................................................................................28

Settings When Changing Mounted Internal Clock.............................................................................................29

Settings When Using External Clock ................................................................................................................30

4-1

Pins That Cannot Be Emulated.........................................................................................................................36

5-1

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

Corresponding Pin List (Pin Equivalent Circuit 1)..............................................................................................38

Corresponding Pin List (Pin Equivalent Circuit 2)..............................................................................................39

Corresponding Pin List (Pin Equivalent Circuit 3)..............................................................................................44

Corresponding Pin List (Pin Equivalent Circuit 4)..............................................................................................44

Corresponding Pin List (Pin Equivalent Circuit 5)..............................................................................................45

Corresponding Pin List (Pin Equivalent Circuit 6)..............................................................................................45

Corresponding Pin List (Pin Equivalent Circuit 7)..............................................................................................49

Corresponding Pin List (Pin Equivalent Circuit 8)..............................................................................................49

Corresponding Pin List (Pin Equivalent Circuit 9)..............................................................................................50

5-10 Corresponding Pin List (Pin Equivalent Circuit 10)............................................................................................50

C-1

Recommended Reflow Conditions....................................................................................................................77

User’s Manual U14481EJ2V0UM

12

CHAPTER 1 OVERVIEW

The IE-703107-MC-EM1 is an option board for the in-circuit emulator IE-V850E-MC-A. By connecting the IE-

703107-MC-EM1 to IE-V850E-MC-A, hardware and software can be debugged efficiently in system development

using the V850E/MA1 and V850E/MA2.

In this manual, the basic setup sequences and switch settings of the IE-703107-MC-EM1 when connecting it to the

IE-V850E-MC-A are described. For the names and functions of the parts of the IE-V850E-MC-A, and for the

connection of elements, refer to the IE-V850E-MC, IE-V850E-MC-A User’s Manual (U14487E) which is a separate

volume.

User’s Manual U14481EJ2V0UM

13

CHAPTER 1 OVERVIEW

1.1 Hardware Configuration

Separately-sold hardware

In-circuit emulator (IE-V850E-MC-A)

Option board

(IE-703107-MC-EM1)

IE-V850E-MC-A can be used as in-circuit emulator for

V850E/MA1 and V850E/MA2 by adding this board.

Separately-sold hardware

Extension probes

General-purpose extension probes made by TOKYO

ELETECH CORPORATION.

SC: Flexible probe

SC-xxxSDN^{Note 1}

SWEX-xxxSD-1^{Note 1}

SWEX: Coaxial probe

These boards are used to connect the

IE-V850E-MC-A to a personal computer.

These boards are inserted in the expansion slot of

the personal computer.

PC interface boards

IE-70000-PCI-IF (-A)

IE-70000-CD-IF-A

IE-70000-PCI-IF (-A): For PCI bus

IE-70000-CD-IF-A: For PCMCIA socket

Power adapter

AC adapter dedicated to NEC Electronics in-circuit

emulators.

(IE-70000-MC-PS-B)

Conversion socket for V850E/MA1

(161-pin FBGA)

Socket for conversion into foot pattern of FBGA when

the 161-pin FBGA package is used.

CSSOCKET161A1413N01N^{Note 1}

CSSOCKET161A1413N01S1^{Note 1}

LSPACK161A1413N01^{Note 1}

CSICE161A1413N02^{Note 1}

YQGUIDE^{Note 1}

Conversion socket for V850E/MA2

(100-pin LQFP)

Socket for conversion into foot pattern of 100-pin

LQFP when the V850E/MA2 is used.

VP-V850E/MA1-MA2^{Note 2}

NQPACK100SD^{Note 1}

YQPACK100SD^{Note 1}

HQPACK100SD^{Note 1}

YQGUIDE^{Note 1}

Notes 1. For further information, contact Daimaru Kogyo Co., Ltd.

Tokyo Electronics Department (TEL +81-3-3820-7112)

Osaka Electronics Department (TEL +81-6-6244-6672)

2. For further information, contact Naito Densei Machida Mfg. Co., Ltd. (TEL +81-45-475-4191)

User’s Manual U14481EJ2V0UM

14

CHAPTER 1 OVERVIEW

1.2 Hardware Specifications (When Connected to IE-V850E-MC-A)

Table 1-1. Hardware Specifications

Parameter

Value

Target device

V850E/MA1

µPD703103AGJ-UEN

µPD703105AGJ-xxx-UEN

µPD703106AGJ-xxx-UEN

µPD703107AGJ-xxx-UEN

µPD70F3107AGJ-UEN

µPD703106AF1-xxx-EN4

µPD703107AF1-xxx-EN4

µPD70F3107AF1-EN4

µPD703106AGJ(A)-xxx-UEN

µPD703107AGJ(A)-xxx-UEN

µPD70F3107AGJ(A)-xxx-UEN

V850E/MA2

µPD703108GC-8EU

Target board interface voltage

Maximum operation frequency

VDD = AVDD = CVDD = AVREF = 3.3 ±0.3 V

V^SS= AVSS = CVSS = 0 V

50 MHz (40 MHz when the in-circuit emulator is used for the

V850E/MA2)

External dimensions

Height

Length

Width

15 mm

(refer to APPENDIX A DIMENSIONS)

206 mm

96 mm

Power consumption

Weight

9.1 W (Max.)

190 g

Remark “xxx” indicates ROM code suffix.

{

Extremely lightweight and compact

Higher equivalence with target device can be achieved by omitting buffer between signal cables.

External data of 8 bits can be traced by connecting an external logic probe (included).

The following pins can be masked.

RESET, NMI, WAIT, HLDRQ, STOP

User’s Manual U14481EJ2V0UM

15

CHAPTER 1 OVERVIEW

1.3 System Specifications of IE-703107-MC-EM1 (When Connected to IE-V850E-MC-A)

Table 1-2. System Specifications of IE-703107-MC-EM1 (When Connected to IE-V850E-MC-A)

Parameter

Internal ROM

Specification

Emulation memory

capacity

1 MB (Max.)

4 MB (Max.)

1 MB (Max.)

External memory

Internal ROM

Execution/pass detection

coverage

Program execution

function

Real-time execution function

Go, execution from cursor position, automatic go, execution up

to cursor position, restart, return out

Non-real-time execution function

Step-in, next over, slow-motion

Break function

Event detection break, software break, forced break, break via

come function, break on condition met during step execution,

failsafe break

Trace function

Other functions

Trace condition

All trace, section trace, qualify trace

Memory capacity

168 bits × 32 K frames

Mapping function, event function, snapshot function, stub

function, register manipulation function, memory manipulation

function, time measurement function, real-time RAM sampling

function

Caution Some of the functions may not be supported depending on the debugger used.

User’s Manual U14481EJ2V0UM

16

CHAPTER 1 OVERVIEW

1.4 System Configuration

The system configuration when connecting the IE-703107-MC-EM1 to the IE-V850E-MC-A, which is then

connected to a personal computer (PC-9800 series, PC/AT^TMor compatible) is shown below.

• V850E/MA1 (144-pin LQFP): Refer to Figure 1-1.

• V850E/MA1 (161-pin FBGA): Refer to Figure 1-2.

• V850E/MA2 (100-pin LQFP): Refer to Figure 1-3.

Figure 1-1. System Configuration (V850E/MA1, 144-Pin LQFP)

<14>

<5>

<6>

<7>

<13>

<15>

<4>

<9>

<8>

Target

system

<10>

<11>

<9>

<10>

<3>

<12>

<11>

V850E/MA1

(144-pin LQFP)

<1>, <2>

<12>

Target

system

<11>

Target system

Remarks 1. <1> Personal computer (PC-9800 series, PC/AT or compatible)

<2> Debugger (sold separately), device file

<3> PC interface board (IE-70000-PCI-IF(-A), IE-70000-CD-IF-A: sold separately)

<4> PC interface cable (included with IE-V850E-MC-A)

<5> In-circuit emulator (IE-V850E-MC-A: sold separately)

<6> In-circuit emulator option board (IE-703107-MC-EM1: this product)

<7> External logic probe (included with IE-703107-MC-EM1)

<8> Extension probe (SC-144SDN, SWEX-144SD-1: sold separately)

<9> Guide screws (YQGUIDE: included)

<10> IE connector for 144-pin LQFP (YQPACK144SD: included)

<11> Target connection socket for 144-pin LQFP (NQPACK144SD: included)

<12> Cover for mounting device in 144-pin LQFP (HQPACK144SD: included)

<13> Power adapter (IE-70000-MC-PS-B: sold separately)

<14> AC100 V power cable (sold separately: included with IE-70000-MC-PS-B)

<15> AC220 V power cable (sold separately: included with IE-70000-MC-PS-B)

2. The encircled portions show enlarged figures of the connectors for target connection.

User’s Manual U14481EJ2V0UM

17

CHAPTER 1 OVERVIEW

Figure 1-2. System Configuration (V850E/MA1, 161-Pin FBGA)

<19>

<5>

<6>

<7>

<18>

<20>

<4>

<14>

<15>

<8>

V850E/MA1

(161-pin FBGA)

<9>

<10>

<16>

<3>

<17>

<11>

<14><15>

<12>

<13>

Target

system

<11><16><17>

<13>

<1>, <2>

<9>

<10><11>

<13>

Target

system

Target system

Remarks 1. <1> Personal computer (PC-9800 series, PC/AT or compatible)

<2> Debugger (sold separately), device file

<3> PC interface board (IE-70000-PCI-IF(-A), IE-70000-CD-IF-A: sold separately)

<4> PC interface cable (included with IE-V850E-MC-A)

<5> In-circuit emulator (IE-V850E-MC-A: sold separately)

<6> In-circuit emulator option board (IE-703107-MC-EM1: this product)

<7> External logic probe (included with IE-703107-MC-EM1)

<8> Extension probe (SC-144SDN, SWEX-144SD-1: sold separately)

<9> Guide screws (YQGUIDE: included)

<10> IE connector for 161-pin FBGA (CSICE161A1413N02: sold separately)

<11> Pogo pin connector for 161-pin FBGA (LSPACK161A1413N01: sold separately)

<12> Stacking socket for 161-pin FBGA (option) (CSSOCKET161A1413N01S1: sold separately)

<13> Target connection socket for 161-pin FBGA (CSSOCKET161A1413N01N: sold separately)

This is a type of target connection socket without guide pins.

The type of target connection socket with guide pins is the CSSOCKET161A1413N01.

<14> Screw for mounting device (included with LSPACK161A1413N01)

<15> Cover for mounting device (included with LSAPCK161A1413N01)

<16> Spacer for mounting device (included with LSPACK161A1413N01)

<17> Guide plate for mounting device (included with LSPACK161A1413N01)

<18> Power adapter (IE-70000-MC-PS-B: sold separately)

<19> AC100 V power cable (sold separately: included with IE-70000-MC-PS-B)

<20> AC220 V power cable (sold separately: included with IE-70000-MC-PS-B)

2. The encircled portions show enlarged figures of the connectors for target connection.

User’s Manual U14481EJ2V0UM

18

CHAPTER 1 OVERVIEW

Figure 1-3. System Configuration (V850E/MA2, 100-Pin LQFP)

<15>

<5>

<6>

<7>

<14>

<16>

<8>

<4>

<11>

<12>

Target

system

<9>

<3>

<10>

<11>

V850E/MA2

<1>, <2>

(100-pin LQFP)

<12>

<13>

<12>

Target

system

Target system

Remarks 1. <1> Personal computer (PC-9800 series, PC/AT or compatible)

<2> Debugger (sold separately), device file

<3> PC interface board (IE-70000-PCI-IF(-A), IE-70000-CD-IF-A: sold separately)

<4> PC interface cable (included with IE-V850E-MC-A)

<5> In-circuit emulator (IE-V850E-MC-A: sold separately)

<6> In-circuit emulator option board (IE-703107-MC-EM1: this product)

<7> External logic probe (included with IE-703107-MC-EM1)

<8> 144-pin to 100-pin conversion adapter (VP-V850E/MA1-MA2: sold separately)

<9> Extension probe (SC-100SDN, SWEX-100SD-1: sold separately)

<10> Guide screws (YQGUIDE: included)

<11> IE connector for 100-pin LQFP (YQPACK100SD: included with VP-V850E/MA1-MA2)

<12> Target connection socket for 100-pin LQFP (NQPACK100SD: included with VP-V850E/MA1-

MA2)

<13> Cover for mounting device in 100-pin LQFP (HQPACK100SD: included with VP-V850E/MA1-

MA2)

<14> Power adapter (IE-70000-MC-PS-B: sold separately)

<15> AC100 V power cable (sold separately: included with IE-70000-MC-PS-B)

<16> AC220 V power cable (sold separately: included with IE-70000-MC-PS-B)

2. The encircled portions show enlarged figures of the connectors for target connection.

User’s Manual U14481EJ2V0UM

19

CHAPTER 1 OVERVIEW

1.5 Contents in Carton

The carton of the IE-703107-MC-EM1 contains the main unit, a guarantee card, a packing list, and an accessory

bag. Make sure that the accessory bag contains this manual and connector accessories. In the case of missing or

damaged items, contact an NEC Electronics sales representative or distributor.

Figure 1-4. Contents in Carton

<2> Accessory bag

<1> IE-703107-MC-EM1

<5> IC socket

NQPACK144SD

<4> Packing list

<6> IC socket

YQPACK144SD

<3> Guarantee card

<7> IC socket

HQPACK144SD

<8> Guide screws

YQGUIDE

<1> IE-703107-MC-EM1 × 1

<2> Accessory bag × 1

<3> Guarantee card × 1

<4> Packing list × 1

<5> IC socket NQPACK144SD × 1

<6> IC socket YQPACK144SD × 1

<7> IC socket HQPACK144SD × 1

<8> Guide screws YQGUIDE × 4

Check that the accessory bag contains this manual, a packing list, an external logic probe, and a restriction

document.

User’s Manual U14481EJ2V0UM

20

CHAPTER 1 OVERVIEW

1.6 Connection Between IE-V850E-MC-A and IE-703107-MC-EM1

The procedure for connecting the IE-V850E-MC-A and IE-703107-MC-EM1 is described below.

Caution Connect carefully so as not to break or bend connector pins.

<1> Remove the POD cover (lower) of the IE-V850E-MC-A.

<2> Set the PGA socket lever of the IE-703107-MC-EM1 to the OPEN position as shown in Figure 1-5 (b).

<3> Connect the IE-703107-MC-EM1 to the PGA socket at the rear of the POD (refer to Figure 1-5 (c)). When

connecting, position the IE-V850E-MC-A and IE-703107-MC-EM1 so that they are horizontal.

Spacers can be connected to fix the POD (refer to APPENDIX D MOUNTING OF PLASTIC SPACER).

<4> Set the PGA socket lever of the IE-703107-MC-EM1 to the CLOSE position as shown in Figure 1-5 (b).

<5> Fix the POD cover (lower) to the soldered side of the IE-703107-MC-EM1 using the nylon rivets supplied with

the IE-V850E-MC-A.

Figure 1-5. Connection Between IE-V850E-MC-A and IE-703107-MC-EM1 (1/2)

(a) Connection overview

Nylon rivets

POD cover

(upper)

Nylon rivets

IE-703107-MC-EM1

IE-V850E-MC-A

POD cover

(lower)

Nylon rivets

User’s Manual U14481EJ2V0UM

21

CHAPTER 1 OVERVIEW

Figure 1-5. Connection Between IE-V850E-MC-A and IE-703107-MC-EM1 (2/2)

(b) PGA socket lever of IE-703107-MC-EM1

CLOSE

OPEN

(c) Connecting part (IE-703107-MC-EM1)

Pin A1 location

: Insertion guide pin

: IE-V850E-MC-A insertion area

User’s Manual U14481EJ2V0UM

22

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

This chapter describes the names, functions, and switch settings of components comprising the IE-703107-MC-

EM1. For the details of the pod, jumper, and switch positions, etc., refer to the IE-V850E-MC, IE-V850E-MC-A User’s

Manual (U14487E).

23

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

2.1 Names and Functions of IE-703107-MC-EM1 Components

Figure 2-1. IE-703107-MC-EM1

Direction of pin 1 of

the connector for

target connection

Connector for

target connection

LD2

LD1

DIRECT

SW1

D70F3107

TP1

PLL

TP2

TP3

TP4

TP5

TP6

TP7

JP1

JP2

1

7

2

8

CN1

1

3

2

4

Connector for connecting

IE-V850E-MC-A

Emulation memory

24

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

(1) Test pins (TP1 to TP7)

To leave the DMA cycle or refresh cycle in the tracer, or cause a break, connect these pins to the external logic

probe.

• TP1: GND

• TP2: REFRQ

• TP3: DMAAK0

• TP4: DMAAK1

• TP5: DMAAK2

• TP6: DMAAK3

• TP7: Test pin for product shipment inspection

(2) SW1

This is a switch for clock mode switching (for details, refer to 2.2 Clock Settings).

(3) JP1

This is a jumper for switching the clock supply source (for details, refer to 2.2 Clock Settings).

(4) JP2

This is a jumper for switching the power supply (for details, refer to 2.4 Power Supply Settings).

(5) CN1

Connects the external logic probe (included).

(6) LD1 (CKSEL: Green)

This LED indicates the level input to the CKSEL pin. If the target system is not connected, whether this LED lights

or not is determined by the setting of SW1.

LED Status

Lit

Extinguished

When Used as Stand-Alone Unit

SW1 = DIRECT

When Used Connected to Target System

The CKSEL signal from the target system is high

The CKSEL signal from the target system is low

SW1 = PLL

(7) LD2 (RUN: Yellow)

This LED indicates whether the program is under execution.

LED Status

Lit

Extinguished

Meaning

User program is being executed.

User program is halted.

(8) Connector for IE-V850E-MC-A connection

This is a connector for connecting the IE-V850E-MC-A.

(9) Connector for target connection

This is a connector for connecting the target system or the extension probe.

(10)Emulation memory

This is a memory that replaces the memory/memory mapped I/O on the target system (for details, refer to 2.5

Emulation Memory).

25

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

2.2 Clock Settings

2.2.1 Outline of clock settings

The following three clock setting methods are available.

For details, refer to 2.2.2 Clock setting methods.

(1) Use the crystal oscillator mounted on the IE-703107-MC-EM1 as the internal clock.

(2) Change the crystal oscillator mounted on the IE-703107-MC-EM1 and use it as the internal clock.

(3) Use the crystal oscillator on the target system as an external clock.

Caution When using an external clock, input a square wave to the X1 pin.

When a clock generated by a crystal/ceramic resonator is used, the IE-703107-MC-EM1 does not

operate.

Figure 2-2. Outline of Clock Settings

IE-703107-MC-EM1

Crystal oscillator

(can be changed)

Switching internal/

external clock

Target system

OSC

JP1

X1

Crystal

oscillator

IE-V850E-MC-A

SW1

PLL/direct

mode

switching

Emulation CPU

µ

PD70F3107

CKSEL

CLKOUT

26

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

2.2.2 Clock setting methods

A list of the hardware settings for each clock setting is shown below.

Table 2-1. List of Hardware Settings for Each Clock Setting

Type of Clock Used

Clock Source

Selection^{Note 1}

OSC Crystal

Oscillator

JP1 Setting

Clock

Mode

SW1

CKSEL

Pin^{Note 2}

PLL

(1) Use crystal oscillator (OSC)

mounted on IE-703107-MC-

EM1 as internal clock.

Internal

External

Factory setting

(5.000 MHz)

PLL

Low-level

input

2

1

Direct

PLL

Direct

PLL

High-level

input

8

2

7

Direct

PLL

(2) Change crystal oscillator

(OSC) mounted on IE-703107-

MC-EM1 and use it as the

Change (to other

than 5.000 MHz)

Low-level

input

1

Direct

PLL

internal clock^{Note 3}

.

Direct

PLL

High-level

input

8

2

7

Direct

PLL

(3) Use the crystal oscillator on

the target system as an

external clock.

Crystal oscillator

can be either

mounted or not

mounted

Low-level

input

1

Direct

PLL

Direct

High-level

input

8

7

Direct

Notes 1. Select the clock source in the clock source selection area in the configuration dialog box on the

debugger.

2. The input setting to the CKSEL pin is made only when a target system is connected. Leave this pin open

when operating the emulator on a stand-alone basis. The emulator operates according to the setting of

SW1.

3. When replacing the crystal oscillator on the emulator, use an oscillator with the following specifications.

Power supply voltage

Output level

Shape

5 V

CMOS

8-pin type

Pin layout

Pin 1: NC Pin 4: GND Pin 5: OUT Pin 8: VDD

Caution Settings other than those described above are prohibited.

27

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

(1) Using the crystal oscillator (OSC) mounted on the IE-703107-MC-EM1 as the internal clock

<1> Mount the 5.000 MHz crystal oscillator mounted at factory shipment in the OSC socket of the IE-703107-

MC-EM1 (with the default settings).

<2> Change JP1 as indicated in Table 2-2 (with the default settings).

<3> Set the SW1 and CKSEL pins according to the clock mode to be used, as shown in Table 2-2.

<4> To start up the integrated debugger (ID850), select “Internal” in the clock source selection area in the

configuration dialog box (clock selection in emulator).

Table 2-2. Settings When Using Mounted Internal Clock

Type of Clock Used

Clock Source

Selection

OSC Crystal

Oscillator

JP1

Clock

Mode

SW1

CKSEL

Pin^Note

Setting

PLL

2

1

Use crystal oscillator (OSC)

mounted on IE-703107-MC-EM1

as internal clock.

Internal

Factory setting

(5.000 MHz)

PLL

Low-level

input

Direct

PLL

Direct

High-level

input

8

Direct

7

Note The input setting to the CKSEL pin is made only when a target system is connected.

Leave this pin open when operating the emulator on a stand-alone basis. The emulator operates according

to the setting of SW1.

Figure 2-3. Outline When Using Mounted Internal Clock

IE-703107-MC-EM1

1-2 shorted

3-4 shorted

5-6 open

7-8 open

Select

“Internal”

on ID850

Mounted

crystal oscillator

Target system

OSC

JP1

5 MHz

X1

Crystal

oscillator

IE-V850E-MC-A

SW1

PLL/direct

mode

switching

Emulation

CPU

PD70F3107

µ

CKSEL

CLKOUT

28

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

(2) Changing the crystal oscillator (OSC) mounted on the IE-703107-MC-EM1 and using it as the internal clock

<1> Remove the crystal oscillator (OSC) that is mounted on the IE-703107-MC-EM1 and mount the oscillator to

be used.

<2> Set JP1 as shown in Table 2-3 (with the default settings).

<3> Set the SW1 and CKSEL pins according to the clock mode to be used, as shown in Table 2-3.

<4> Select “Internal” in the clock source selection area in the configuration dialog box on the integrated

debugger (ID850).

Table 2-3. Settings When Changing Mounted Internal Clock

Type of Clock Used

Clock Source

Selection

OSC Crystal

Oscillator

JP1

Clock

Mode

SW1

CKSEL

Pin^Note

Setting

PLL

2

1

Change the crystal oscillator

mounted on IE-703107-MC-EM1

and use it as the internal clock.

Internal

Change (to other

than 5.000 MHz)

PLL

Low-level

input

Direct

PLL

Direct

High-level

input

8

Direct

7

Note The input setting to the CKSEL pin is made only when a target system is connected.

Leave this pin open when operating the emulator on a stand-alone basis. The emulator operates according

to the setting of SW1.

Figure 2-4. Outline When Changing Mounted Crystal Oscillator and Using It as Internal Clock

IE-703107-MC-EM1

1-2 shorted

3-4 shorted

5-6 open

7-8 open

Select

“Internal”

on ID850

Change crystal

oscillator

Target system

OSC

JP1

other than

5 MHz

X1

Crystal

oscillator

IE-V850E-MC-A

SW1

PLL/direct

mode

switching

Emulation

CPU

µPD70F3107

CKSEL

CLKOUT

29

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

(3) Using the target system crystal oscillator as an external clock

<1> Set JP1 as shown in Table 2-5 (with the default setting).

<2> Set the SW1 and CKSEL pins according to the clock mode to be used, as shown in Table 2-5.

<3> Select “External” in the clock source selection area in the configuration dialog box on the integrated

debugger (ID850).

Table 2-4. Settings When Using External Clock

Type of Clock Used

Clock Source

Selection

OSC Crystal

Oscillator

JP1

Clock

Mode

SW1

CKSEL

Pin^Note

Setting

PLL

2

1

Use crystal oscillator on target

system as external clock.

External

Crystal oscillator

can be either

mounted or not

mounted

PLL

Low-level

input

Direct

PLL

Direct

High-level

input

8

Direct

7

Note The input setting to the CKSEL pin is made only when a target system is connected.

Leave this pin open when operating the emulator on a stand-alone basis. The emulator operates according

to the setting of SW1.

Caution Be sure to input a square wave to the X1 pin.

When a clock generated by a crystal/ceramic resonator is used, the IE-703107-MC-EM1 does not

operate.

Figure 2-5. Outline When Using Crystal Oscillator on Target System as External Clock

IE-703107-MC-EM1

1-2 shorted

3-4 shorted

5-6 open

7-8 open

Select

“External”

on ID850

Target system

JP1

OSC

X1

Crystal

oscillator

IE-V850E-MC-A

SW1

PLL/direct

mode

switching

Emulation

CPU

µ

PD70F3107

CKSEL

CLKOUT

30

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

2.3 Operation Mode Settings

The IE-703107-MC-EM1 supports the following operation modes equivalent to those of the actual device. These

operation modes are selected on the debugger.

Target Device

V850E/MA1

Operation Mode

Single-chip mode 0

Selection in ID850^Note

MODE00

Single-chip mode 1

ROMless mode 0

ROMless mode 1

ROMless mode 0

ROMless mode 1

MODE01

MODE02

MODE03

V850E/MA2

MODE00

MODE01

Note Make settings in accordance with the operation mode to be used in the mask setting area of the

configuration dialog box that opens when the debugger (ID850) is started.

Caution To operate the emulator in the ROMless mode, be sure to map the emulation memory or the

memory on the target system from address 0H.

Note that the IE-703107-MC-EM1 cannot emulate the MODE pin because the level input to the MODE pin is

realized by the pin mask function of the debugger.

For how to set the pins on the target system, refer to the V850E/MA1 Hardware User’s Manual (U14359E) or

V850E/MA2 Hardware User’s Manual (U14980E).

31

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

2.4 Power Supply Settings

The power supply (V^DD) is set by using JP2.

2.4.1 JP2 setting when emulator operates as stand-alone unit

When JP2 is set as shown in Figure 2-6, the IE-703107-MC-EM1 detects the power on the target system side and

automatically selects whether V^DDis supplied from the internal power supply of the emulator or from the target system

(with the default settings).

Caution If the JP2 setting is incorrect, the emulator may be damaged.

Figure 2-6. Setting of JP2 (for Automatic Selection of Power)

JP2^Note

4

3

2

1

4

3

Set to 1-2 shorted, 3-4 open

Note A relay is used for power selection. Depending on the combination with the target system, the relay

repeatedly turns ON/OFF when the power to the target system is turned OFF, issuing a sound continuously.

In this case, make the setting shown in Figure 2-7.

Caution If the JP2 setting is incorrect, the emulator may be damaged.

Figure 2-7. Setting of JP2 (to Use Power from Target System)

JP2

2

1

4

3

Set to 1-2 open, 3-4 shorted

Figure 2-7 shows the setting of JP2 to supply power from the target system to V^DD

.

With this setting, however, note that the emulator does not operate when the target system is not connected.

32

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

2.5 Emulation Memory

This is a substitute memory used to emulate the memory or memory mapped I/O on the target system (capacity: 4

MB).

The emulation memory is mounted on the IE-703107-MC-EM1.

2.5.1 Wait setting for emulation memory

The data wait, address wait, and idle state for the emulation memory are set as follows.

(1) ID850

Select from the following three types on the configuration screen.

Selection

WAIT MASK

Wait Type

Data wait

Emulation Memory Access

Fixed to 0 waits

External Memory Access

Depends on DWC0/1 register setting

WAIT signal masked

Address wait

Idle state

Fixed to 0 waits

Fixed to 0 cycles

Fixed to 1 wait

Depends on ASC register setting

Depends on BCC register setting

1 WAIT ACCESS

TARGET WAIT

Data wait

Depends on DWC0/1 register setting

and WAIT signal status

Address wait

Idle state

Fixed to 0 waits

Fixed to 0 cycles

Depends on ASC register setting

Depends on BCC register setting

Data wait

Depends on DWC0/1 register setting

However, 1 wait when set to 0 waits

Depends on DWC0/1 register setting

and WAIT signal status

Address wait

Idle state

Fixed to 0 waits

Depends on ASC register setting

Depends on BCC register setting

(2) MULTI

Select mask or unmask for WAIT and EMWAIT using the “Pinmask” command.

Selection

WAIT: Mask

Wait Type

Data wait

Emulation Memory Access

Fixed to 0 waits

External Memory Access

Depends on DWC0/1 register setting

WAIT signal masked

EMWAIT: Mask

Address wait

Idle state

Fixed to 0 waits

Fixed to 0 cycles

Fixed to 1 wait

Depends on ASC register setting

Depends on BCC register setting

WAIT: Unmask

EMWAIT: Mask

Data wait

Depends on DWC0/1 register setting

and WAIT signal status

Address wait

Idle state

Fixed to 0 waits

Fixed to 0 cycles

Depends on ASC register setting

Depends on BCC register setting

WAIT: Unmask

Data wait

Depends on DWC0/1 register setting

However, 1 wait when set to 0 waits

Depends on DWC0/1 register setting

and WAIT signal status

EMWAIT: Unmask

Address wait

Idle state

Fixed to 0 waits

Depends on ASC register setting

Depends on BCC register setting

33

User’s Manual U14481EJ2V0UM

CHAPTER 2 NAMES AND FUNCTIONS OF COMPONENTS

2.5.2 Cautions related to emulation memory

(1) Number of data waits required for emulation memory access

The number of data waits required to be inserted for emulation memory access varies depending on the operating

frequency of the emulator.

4 MHz ≤ Operating frequency < 25 MHz

25 MHz ≤ Operating frequency ≤ 40 MHz

40 MHz < Operating frequency

0 waits

1 wait

2 waits

(2) Bus sizing

Make the bus sizing 16 bits (set BSn0 of BSC register to 1).

An 8-bit bus cannot be used.

(3) WAIT pin

The number of data waits for the emulation memory is not affected by the WAIT pin.

(4) Address wait

Address waits cannot be inserted in the emulation memory.

When address waits need to be inserted, set as follows.

Number of address waits

Number of data waits

for external memory or

external I/O

Number of data waits for CS

=

for external memory or

external I/O

+

space of emulation memory

This setting is effective to make the access speed to the emulation memory equal to that of the external memory

or external I/O to measure the performance, etc.

For how to insert waits in the emulation memory, refer to 2.5.1 Wait setting for emulation memory.

34

User’s Manual U14481EJ2V0UM

CHAPTER 3 FACTORY SETTINGS

Item

Setting

Remark

JP1

JP2

SW1

All settings other than those set in the factory are

prohibited.

2

1

8

7

Detects the power of the target system and

automatically selects whether V^DDis supplied from

the internal power supply of the emulator or from

the target system.

JP2

4

3

2

1

4

3

Set to PLL mode.

PLL

DIRECT

OSC

5.000 MHz crystal oscillator is mounted.

The frequency can be varied by replacing the

crystal oscillator.

User’s Manual U14481EJ2V0UM

35

CHAPTER 4 CAUTIONS

4.1 Cautions on Terminating Pins

The pins that perform special processing in the emulator are explained below.

For detailed circuit configuration, refer to CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND

TARGET INTERFACE CIRCUITS.

(1) Pins that cannot be emulated

The following pins cannot be emulated because they are left open inside the emulator or connected to 3.3 V or

GND via resistor. Evaluate these pins by using the target device.

Table 4-1. Pins That Cannot Be Emulated

Pin Name 1

Target Device

Pin No.

58

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

MODE0

M8

36

57

MODE1

MODE2

X2

P8

35

18

G1

21

62

N9

40

61

CVDD

P9

39

(2) X1 pin

The X1 pin is pulled down using 33 kΩ when an external clock is selected.

Because the external clock is input to the clock generator via 74HC157, a delay time of up to 13.2 ns is

generated.

This pin is pulled down using 33 kΩ and is left open when the internal clock is selected.

(3) CKSEL pin

The CKSEL pin can be pulled up or down, depending on the setting of SW1.

It is pulled down using 33 kΩ when “PLL” is selected by SW1. This pin is pulled up using 33 kΩ when “DIRECT”

is selected.

User’s Manual U14481EJ2V0UM

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CHAPTER 4 CAUTIONS

(4) VDD pin

<1> V^DDin the target system is used to operate the circuits in the emulator.

When pins 1 and 2 of JP2 are shorted, and 3 and 4 are left open, the emulator detects V^DDof the target

system and automatically selects whether V^DDof the target system or the internal power supply of the

emulator is to be used.

<2> When pins 1 and 2 of JP2 are left open, and 3 and 4 are shorted, the emulator always uses V^DDfrom the

target system. With this setting of JP2, the emulator does not operate if the target system is not connected.

However, sneaking of power can be avoided.

Figure 4-1. Schematic Diagram of Power Supply Flow

IE-V850E-MC

Emulation CPU

IE-703107-MC-EM1

Target system

µ

PD70F3107

Power supply

circuit

VDD

Relay

Fixed

Automatically selected

JP2

2

1

4

3

2

1

4

3

4

3

4.2 Notes on Internal RAM

The emulator maps the internal RAM to a 12 KB space of 0xFFFC000 to 0xFFFEFFF.

V850E/MA1 (internal RAM: 4 KB):

V850E/MA1 (internal RAM: 10 KB):

V850E/MA2 (internal RAM: 4 KB):

0xFFFC000 to 0xFFFCFFF

0xFFFC000 to 0xFFFE7FF

0xFFFC000 to 0xFFFCFFF

The target device is mapped as shown above. Consequently, the higher 8 KB space (0xFFFD000 to 0xFFFEFFF)

or higher 2 KB space (0xFFFE800 to 0xFFFEFFF) of the emulator’s 12 KB internal RAM area does not exist in the

target device.

If the higher 8 KB or 2 KB space is accessed, the emulator cannot issue a fail-safe break. It is therefore necessary

to set an access break in advance.

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CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

This chapter shows the internal equivalent circuits of the emulator signals to be connected to the target system.

Some pins cannot be emulated because of the internal processing of the emulator (refer to CHAPTER 4 CAUTIONS).

The equivalent circuits are shown in Figures 5-1 to 5-10.

Tables 5-1 to 5-10 show lists of the pins corresponding to the respective equivalent circuits.

Figure 5-1. Pin Equivalent Circuit 1

5 V

2.5 V

µ

PC358

74VHCT541

22 Ω

IE-V850E-MC-A

LED (Target)

V

DD

1 kΩ

3.3 V

MA1_VDD

5

Relay

Emulation CPU

µ

PD70F3107

Table 5-1. Corresponding Pin List (Pin Equivalent Circuit 1)

Pin Name 1

Target Device

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

Pin No.

8, 27, 37, 47, 81, 98, 112, 124, 134

A12, C6, C8, F4, L6, F12, J3, K14, P1

11, 33, 55, 83, 93

VDD

Figure 5-2. Pin Equivalent Circuit 2

PDL0 to 15, PAH0 to 9,

PCT0 and 1, PCT4 to 7,

PCD0 to 3, PAL0 to 15,

PCS0 to 7, PBD0 to 3,

PCM0 to 5

Emulation CPU

38

User’s Manual U14481EJ2V0UM

CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Table 5-2. Corresponding Pin List (Pin Equivalent Circuit 2) (1/5)

Pin Name 1 Pin Name 2 Pin Name 3 Pin Name 4

Target Device

Pin No.

17

G3

20

16

H4

19

15

F1

18

14

F2

17

13

F3

16

12

E1

15

11

G4

14

10

E2

13

7

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

PDL0

PDL1

PDL2

PDL3

PDL4

PDL5

PDL6

PDL7

PDL8

PDL9

PDL10

PDL11

PDL12

PDL13

D0

D1

−

D2

D3

D4

D5

D6

D7

D8

E3

10

6

D9

C2

9

5

D10

D11

D12

D13

D2

8

4

E4

7

3

B2

6

2

C3

5

User’s Manual U14481EJ2V0UM

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CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Table 5-2. Corresponding Pin List (Pin Equivalent Circuit 2) (2/5)

Pin Name 1 Pin Name 2 Pin Name 3 Pin Name 4

Target Device

Pin No.

1

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

PDL14

PDL15

PAH0

PAH1

PAH2

PAH3

PAH4

PAH5

PAH6

PAH7

PAH8

PAH9

PCT0

PCT1

D14

D15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

LCAS

UCAS

−

D3

4

144

A2

−

3

123

D8

82

−

122

A9

−

81

121

B9

−

80

120

C9

79

−

119

D9

78

−

118

B10

77

−

117

C10

76

−

116

D10

75

−

115

A11

74

−

114

B11

−

97

LWR

UWR

LDQM

UDQM

F13

65

96

F14

64

User’s Manual U14481EJ2V0UM

40

CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Table 5-2. Corresponding Pin List (Pin Equivalent Circuit 2) (3/5)

Pin Name 1 Pin Name 2 Pin Name 3 Pin Name 4

Target Device

Pin No.

95

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

PCT4

PCT5

PCT6

PCT7

PCD0

PCD1

PCD2

PCD3

PAL0

PAL1

PAL2

PAL3

PAL4

PAL5

RD

WE

−

F11

63

94

−

G12

62

93

OE

−

G14

−

92

BCYST

SDCKE

SDCLK

LBE

UBE

A0

−

G13

−

111

D11

73

−

110

B12

72

−

109

A13

71

SDCAS

108

A14

70

SDRAS

143

B3

−

2

142

C4

1

A1

141

A3

A2

100

140

D4

99

A3

139

B4

A4

98

138

A4

A5

97

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CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Table 5-2. Corresponding Pin List (Pin Equivalent Circuit 2) (4/5)

Pin Name 1 Pin Name 2 Pin Name 3 Pin Name 4

Target Device

Pin No.

137

D5

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

PAL6

PAL7

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

−

96

136

C5

95

133

B6

PAL8

92

132

A6

PAL9

91

131

D6

PAL10

PAL11

PAL12

PAL13

PAL14

PAL15

PCS0

PCS1

PCS2

PCS3

90

130

C7

89

129

A7

88

128

B7

87

127

D7

86

126

A8

85

107

D12

69

106

B13

−

105

C13

−

104

C12

68

−

User’s Manual U14481EJ2V0UM

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CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Table 5-2. Corresponding Pin List (Pin Equivalent Circuit 2) (5/5)

Pin Name 1 Pin Name 2 Pin Name 3 Pin Name 4

Target Device

Pin No.

103

E12

67

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

PCS4

PCS5

PCS6

PCS7

PBD0

PBD1

PBD2

PBD3

PCM0

PCM1

PCM2

PCM3

PCM4

PCM5

−

102

D13

−

101

E11

−

100

E13

66

−

32

DMAAK0

DMAAK1

DMAAK2

DMAAK3

WAIT

−

L4

28

31

−

K3

27

30

−

L2

−

29

−

K4

−

91

−

G11

61

90

CLKOUT

HLDAK

HLDRQ

REFRQ

SELFRQ

BUSCLK

H14

60

89

−

H13

59

88

H13

58

87

H11

57

86

J13

−

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CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Figure 5-3. Pin Equivalent Circuit 3

3.3 V

33 kΩ

Emulation CPU

RESET

Table 5-3. Corresponding Pin List (Pin Equivalent Circuit 3)

Pin Name 1

Target Device

Pin No.

59

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

RESET

L9

37

Figure 5-4. Pin Equivalent Circuit 4

V

SS, AVSS

,

CVSS

GND

Table 5-4. Corresponding Pin List (Pin Equivalent Circuit 4)

Pin Name 1

Target Device

Pin No.

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

9, 28, 113, 125, 135, 48, 38, 99, 82

VSS

B5, B8, C11, D1, E14, K2, K13, M6, P2

12, 34, 56, 84, 94

72

N13

50

AVSS0

CVSS

64

N10

42

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CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Figure 5-5. Pin Equivalent Circuit 5

CVDD, MODE2,

X2, NC

OPEN

Table 5-5. Corresponding Pin List (Pin Equivalent Circuit 5)

Pin Name 1

Pin Name 2

Package

Pin No.

61

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

CVDD

−

P9

39

18

MODE2

X2

VPP

G1

−

62

−

N9

40

−

A1, A5, A10, B1, B14, C1, C14, D14, E5, L1,

M1, M14, N1, N14, P5, P11, P14

NC

−

V850E/MA2 (100-pin LQFP)

−

Figure 5-6. Pin Equivalent Circuit 6

P00 to 07, P10 to 13,

P20 to 27, P30 to 37,

P40 to 45, P50 to 52,

P70 to 77, AVDD

µ

PD70F3107

Table 5-6. Corresponding Pin List (Pin Equivalent Circuit 6) (1/4)

Pin Name 1 Pin Name 2 Pin Name 3

Target Device

Pin No.

26

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

P00

P01

P02

P03

PWM0

TI000

−

K1

−

25

INTP000

J2

26

24

INTP001

TO00

−

J4

25

23

J1

24

User’s Manual U14481EJ2V0UM

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CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Table 5-6. Corresponding Pin List (Pin Equivalent Circuit 6) (2/4)

Pin Name 1 Pin Name 2 Pin Name 3

Target Device

Pin No.

22

H3

23

21

H2

22

20

H1

−

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

P04

P05

P06

P07

P10

P11

P12

P13

P20

P21

P22

P23

P24

P25

DMARQ0

DMARQ1

DMARQ2

DMARQ3

PWM1

INTP100

INTP101

INTP102

19

G2

−

INTP103

36

N2

−

35

L3

30

34

M2

29

33

M3

−

INTP020

INTO011

TO01

TI010

−

46

N5

32

45

M5

−

NMI

−

TI020

−

INTP020

INTP021

TO02

44

P4

−

43

L5

−

42

N4

31

41

P3

−

TC0

INTP110

INTP111

TC1

User’s Manual U14481EJ2V0UM

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CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Table 5-6. Corresponding Pin List (Pin Equivalent Circuit 6) (3/4)

Pin Name 1 Pin Name 2 Pin Name 3

Target Device

Pin No.

40

M4

−

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

P26

P27

AVDD

P30

P31

P32

P33

P34

P35

P36

P37

P40

P41

P42

TC2

TC3

INTP112

INTP113

−

39

N3

−

71

N12

49

56

N8

−

AVREF

SO2

INTP130

INTP131

INTP132

INTP133

INTP120

−

55

L8

−

SI2

54

P7

−

SCK2

TXD2

RXD2

INTP121

INTP122

ADTRG

TXD0

RXD0

SCK0

53

N7

−

52

M7

−

51

P6

−

50

L7

−

49

N6

−

INTP123

SO0

70

M11

48

69

P13

47

68

N11

46

SI0

−

User’s Manual U14481EJ2V0UM

47

CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Table 5-6. Corresponding Pin List (Pin Equivalent Circuit 6) (4/4)

Pin Name 1 Pin Name 2 Pin Name 3

Target Device

Pin No.

67

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

P43

P44

P45

P50

P51

P52

P70

P71

P72

P73

P74

P75

P76

P77

TXD1

RXD1

SCK1

INTP030

INTP031

TO03

ANI0

SC1

L10

45

66

SI1

−

P12

44

65

M10

43

85

TI30

−

J12

−

84

J14

−

83

−

J11

−

80

−

K12

54

79

ANI1

−

K11

53

78

ANI2

−

L14

52

77

ANI3

−

L13

51

76

ANI4

−

L12

−

75

ANI5

−

M13

−

74

ANI6

−

M12

−

73

ANI7

−

L11

−

User’s Manual U14481EJ2V0UM

48

CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Figure 5-7. Pin Equivalent Circuit 7

When external clock is selected

74HC157

µ

PD70F3107

X1

33 kΩ

When internal clock is selected

X1

33 kΩ

Table 5-7. Corresponding Pin List (Pin Equivalent Circuit 7)

Pin Name 1

Package

Pin No.

63

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

X1

P10

41

Figure 5-8. Pin Equivalent Circuit 8

When SW1 “PLL” is selected

CKSEL

µ PD70F3107

33 kΩ

When SW1 “DIRECT” is selected

3.3 V

33 kΩ

µ

PD70F3107

CKSEL

Table 5-8. Corresponding Pin List (Pin Equivalent Circuit 8)

Pin Name 1

Package

Pin No.

60

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

CKSEL

M9

38

User’s Manual U14481EJ2V0UM

49

CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET INTERFACE CIRCUITS

Figure 5-9. Pin Equivalent Circuit 9

MODE0

33 kΩ

Table 5-9. Corresponding Pin List (Pin Equivalent Circuit 9)

Pin Name 1

Package

Pin No.

58

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

MODE0

M8

36

Figure 5-10. Pin Equivalent Circuit 10

3.3 V

33 kΩ

MODE1

Table 5-10. Corresponding Pin List (Pin Equivalent Circuit 10)

Pin Name 1

Package

Pin No.

57

V850E/MA1 (144-pin LQFP)

V850E/MA1 (161-pin FBGA)

V850E/MA2 (100-pin LQFP)

MODE1

P8

35

User’s Manual U14481EJ2V0UM

50

APPENDIX A DIMENSIONS

A.1 Corresponding Package Dimensions

(1) IE-V850E-MC-A + IE-703107-MC-EM1 (Unit: mm)

448

166

55

227

Top view

Pin 1 direction

Side view

IE-V850E-MC-A

IE-703107-MC-EM1

Bottom view

206.6

15.88

Top view

29.0

User’s Manual U14481EJ2V0UM

51

APPENDIX A DIMENSIONS

(2) SC-144SDN (Unit: mm)

144

109

108

1

36

37

73

72

40

130

213

43

52

User’s Manual U14481EJ2V0UM

APPENDIX A DIMENSIONS

(3) SC-100SDN (Unit: mm)

1

140

User’s Manual U14481EJ2V0UM

53

APPENDIX A DIMENSIONS

(4) SWEX-100SD-1 (Unit: mm)

(48)

(295±8)

(48)

CN4

TET

SG

FG

SG

FG

SWEX-100SD1

100

IC1

76

1

75

51

25

Target

φ

26

50

FG

SG

FG

SG

MADE IN JAPAN

TET

JAPAN

CN2

(20)

Red

Black

(5)

(45)

Ground Wire

54

User’s Manual U14481EJ2V0UM

APPENDIX A DIMENSIONS

(5) SWEX-144SD-1 (Unit: mm)

(55.5)

(295±8)

CN4

SG

FG

SWEX-144SD-1

TET ₁₄₄

109

1

108

73

36

Target

JAPAN

φ

37

72

CN2

FG

SG

TET

FG

MADE IN JAPAN

(24)

Red

Black

(5)

(45)

Ground Wire

User’s Manual U14481EJ2V0UM

55

APPENDIX A DIMENSIONS

(6) NQPACK144SD (Unit: mm)

[Top View]

27.0

0.55 × 5 = 17.5

3

R1.5

0.5

7.0

0.3

C1.5

109

144

108

1

φ

3

1.0

1 8 . 9

2 6 .

7 . 0

2

36

73

37

72

2.5

20.1

[Side View]

3 . 9

5 .

9 . 4 5

1 . 2

3 . 7

1 . 8 5

0.18

0 . 2

0.5

21.05

[Bottom View]

23.0

12.0

109

144

1

108

2 0 . 1

0 . 2

36

73

72

37

φ

4

2.0 Height of projection1.8

56

User’s Manual U14481EJ2V0UM

APPENDIX A DIMENSIONS

(7) YQPACK144SD (Unit: mm)

[Top View]

22.65

0.5 × 35 = 17.5

φ

4

2.2

0.5

7.0

C2.0

144

109

108

1

φ

1.0

3

7 . 0

2 7 . 0

2 9 . 0

2 1 .

1 8 . 8

1 9 . 4

2 3 . 6

1 6 . 4

36

73

37

72

3

R2.5

4

R1.5

[Side View]

0.3

0.25

×

0.3

2 . 5

3 . 7

1 . 2

9 . 0

1 . 2

3 . 1

7 . 4

3 . 9

2 .

0.25

[Bottom View]

22.8

19.6

C1.5

109

144

108

1

2 0 . 8

73

36

72

37

0 . 2

User’s Manual U14481EJ2V0UM

57

APPENDIX A DIMENSIONS

(8) HQPACK144SD (Unit: mm)

[Top View]

±

0.15

22.65

35 = 17.5

0.1

±

0.1

0.5

×

φ

4

2.2

±

C2.0

7.0

144

109

2 . 7 5

3 . 9 5

1

108

φ

3

1.0

2 7 . 0

2 9 . 0

2 3 . 9

7 . 0

1 9 . 4

1 6 . 0

1 8 . 4

73

36

3 . 9 5

2 . 7 5

37

72

3

R2.5

4

R1.5

[Side View]

1 . 2

2 . 3

3 . 1

7 . 4

1 . 6

3 . 9

2 .

0.25

[Bottom View]

22.8

19.6

C1.5

109

144

108

1

0 .

±

2 1 . 4

73

36

72

37

0 . 2

58

User’s Manual U14481EJ2V0UM

APPENDIX A DIMENSIONS

(9) NQPACK100SD (Unit: mm)

[Top View]

21.0

0.5 × 24 = 12.0

R2.2

C 1.5

−

0.5

5.8

0.3

3

Slit width

3 − 1.0

2.5

14.0⁺⁻^00.1

2.5

[Side View]

0.18

0.5

15.0

0.5

[Bottom View]

17.0

9.0

4 − 2.0 Projection height 1.8

User’s Manual U14481EJ2V0UM

59

APPENDIX A DIMENSIONS

(10) YQPACK100SD (Unit: mm)

[Top View]

16.6

0.5 × 24 = 12.0

4

−

0.5

5.8

φ

2.2

φ

3 – 1.0

4

10.9

13.3

15.7

−

R 3.2

R 2.2

−

4

18.1

[Side View]

0.3

0.25 × 0.3

0.25

0.4

[Bottom View]

0.2

C 1.5

13.4

60

User’s Manual U14481EJ2V0UM

APPENDIX A DIMENSIONS

(11) HQPACK100SD (Unit: mm)

[Top View]

16.6

0.5 × 24 = 12.0

4

−

0.5

5.8

φ

2.2

φ

3 – 1.0

R 2.2

R 3.2

[Side View]

0.23

0.58

[Bottom View]

0.2

C 1.5

13.4

User’s Manual U14481EJ2V0UM

61

APPENDIX A DIMENSIONS

(12) VP-V850E/MA1-MA2 (Unit: mm)

[Top View]

50

NDK

M401958/A

CN2

CN4

1PIN

VP-V850E/MA1-MA2

JAPAN

[Side View]

62

User’s Manual U14481EJ2V0UM

APPENDIX A DIMENSIONS

(13) CSSOCKET161A1413N01N (Unit: mm)

[Top View]

13

0.8 × 13 = 10.4

0.8

C0.5

1.6 1.2

11.8

[Side View]

φ

0.25

0.55

φ

User’s Manual U14481EJ2V0UM

63

APPENDIX A DIMENSIONS

(14) CSSOCKET161A1413N01 (Unit: mm)

[Top View]

13

0.8 × 13 = 10.4

0.8

C0.5

1.6 1.2

11.8

[Side View]

φ

0.48

φ

0.48

0.65

φ

0.25

0.55

φ

64

User’s Manual U14481EJ2V0UM

APPENDIX A DIMENSIONS

(15) CSSOCKET161A1413N01S1 (Unit: mm)

[Top View]

13

0.8 × 13 = 10.4

0.8

C0.5

1.6 1.2

11.8

[Side View]

φ

0.25

φ

0.55

User’s Manual U14481EJ2V0UM

65

APPENDIX A DIMENSIONS

(16) CSICE161A1413N02 (Unit: mm)

[Top View]

29

22.65

0.5 × 35 = 17.5

0.5

C2

Pin 1 direction

φ

4 − 2.2

Component hole

[Side View]

φ

1.03

0.32

φ

[Bottom View]

0.8 × 13 = 10.4

161-Soldering

0.8

φ

161-Land diameter: 0.5

φ

Resist diameter: 0.5

TH not possible

A

N

1

13

MADE IN JAPAN

TET

66

User’s Manual U14481EJ2V0UM

APPENDIX A DIMENSIONS

(17) LSPACK161A1413N01 (CSICE, without device mounting cover) (Unit: mm)

[Top View]

1.2

1.6

[Side View]

[Bottom View]

29

22.65

0.8 × 13 = 10.4

0.8

LSPACK161A

TET MADE IN JAPAN

User’s Manual U14481EJ2V0UM

67

APPENDIX A DIMENSIONS

(18) LSPACK161A1413N01 (with device mounting cover) (Unit: mm)

[Top View]

29

[Side View]

[Bottom View]

68

User’s Manual U14481EJ2V0UM

APPENDIX A DIMENSIONS

A.2 Conditions for Connecting of In-Circuit Emulator Option Board and Conversion Connector

The following shows a diagram of the conditions for connecting the in-circuit emulator option board and conversion

connector. Design your system making allowances for conditions such as the form of parts mounted on the target

system as shown below.

(1) V850E/MA1, 144-pin plastic LQFP (fine pitch) (20 × 20)

Side View

In-circuit emulator

IE-V850E-MC-A

option board

IE-703107-MC-EM1

Conversion connector

206.26 mm

YQGUIDE

YQPACK144SD

Note

NQPACK144SD

Target system

Note The YQSOCKET144SDN (sold separately) can be inserted here to adjust the height (height: 3.2 mm).

Top View

IE-V850E-MC-A

Target system

IE-703107-MC-EM1

YQPACK144SD, NQPACK144SD,

YQGUIDE

Connection condition diagram

IE-703107-MC-EM1

Connect to IE-V850E-MC-A

75 mm

YQGUIDE

YQPACK144SD

NQPACK144SD

13.3 mm

31.84 mm

17.99 mm

Target system

21.58 mm

27.205 mm

Remark The connector for the 161-pin plastic FBGA package is under development.

User’s Manual U14481EJ2V0UM

69

APPENDIX A DIMENSIONS

(2) V850E/MA1, 161-pin plastic FBGA (13 × 13)

Side View

In-circuit emulator

IE-V850E-MC-A

In-circuit emulator

option board

IE-703107-MC-EM1

Conversion connector

206.26 mm

CSICE161A1413N02

LSPACK161A1413N01

Target system

CSSOCKET161A1413N01N^{Note 2}

Note 1

Notes 1. The CSSOCKET161A1413N01S1 (sold separately) can be inserted here to adjust the height (height: 3.2

mm).

2. This is a target socket without guides. Remove suffix N from the part number when a target socket with

guides is needed.

Top View

IE-V850E-MC-A

Target system

IE-703107-MC-EM1

LSPACK161A1413N01, CSSOCKET161A1413N01N,

YQGUIDE

Connection condition diagram

IE-703107-MC-EM1

Connect to IE-V850E-MC-A

Pin 1 position

75 mm

CSICE161A1413N02

LSPACK161A1413N01

CSSOCKET161A1413N01N

15.7 mm

4.2 mm

31.84 mm

17.99 mm

Target system

27.205 mm

70

User’s Manual U14481EJ2V0UM

APPENDIX A DIMENSIONS

(3) V850E/MA2, 100-pin plastic LQFP (fine pitch) (14 × 14)

Side View

In-circuit emulator

IE-V850E-MC-A

In-circuit emulator

option board

IE-703107-MC-EM1

Conversion connector

206.26 mm

VP-V850E/MA1-MA2

YQGUIDE

Note

YQPACK100SD

NQPACK100SD

Target system

Note The YQSOCKET100SDN (sold separately) can be inserted here to adjust the height (height: 3.2 mm).

Top View

IE-V850E-MC-A

Target system

36.0 mm

11.5 mm

13.5 mm

IE-703107-MC-EM1

YQPACK100SD, NQPACK100SD,

YQGUIDE

Connection condition diagram

IE-703107-MC-EM1

Connect to IE-V850E-MC-A

Pin 1 position

75 mm

VP-V850E/MA1-MA2

25.8 mm

16.5 mm

50 mm

47.21 mm

Target system

YQPACK100SD

NQPACK100SD

User’s Manual U14481EJ2V0UM

71

APPENDIX B EXAMPLE OF USE OF CONNECTOR FOR TARGET CONNECTION

(1) When directly connecting device to target system (connector for target connection is not used)

Device

Target system

(2) When connecting device using connector for target connection

(a) LQFP package

Fastening screws

HQPACK144SD (V850E/MA1, 144-pin LQFP)

HQPACK100SD (V850E/MA2, 100-pin LQFP)

Device

NQPACK144SD (V850E/MA1, 144-pin LQFP)

NQPACK100SD (V850E/MA2, 100-pin LQFP)

Target system

(b) FBGA package

Device

LSPACK161A1413N01

CSSOCKET161A1413N01N

72

User’s Manual U14481EJ2V0UM

APPENDIX C CONNECTORS FOR TARGET CONNECTION

C.1 Usage (LQFP Package)

(1) When mounting NQPACK144SD on target system

<1> Coat the tip of the four projections (points) at the bottom of the NQPACK144SD or NQPACK100SD with

two-component type epoxy adhesive (cure time longer than 30 minutes) and bond the NQPACK144SD or

NQPACK100SD to the target system. If not bonded properly, the pad of the printed circuit board may peel

off when the emulator is removed from the target system. If the lead of the NQPACK144SD or

NQPACK100SD is not aligned with the pad of the target system easily, perform step <2> to adjust the

position.

<2> To adjust the position, insert the guide pins for position-adjustment (NQGUIDE) provided with the

NQPACK144SD or NQPACK100SD into the pin holes at the upper side of NQPACK144SD or

NQPACK100SD (refer to Figure C-1). The diameter of a hole is φ = 1.0 mm. There are three non-through

holes (refer to APPENDIX A DIMENSIONS).

<3> After setting the HQPACK144SD or HQPACK100SD, solder the NQPACK144SD or NQPACK100SD to the

target system. By following this sequence, adherence of flux or solder sputtering to contact pins of the

NQPACK144SD or NQPACK100SD can be avoided.

Recommended soldering conditions… Reflow:

240°C, 20 seconds max.

Partial heating: 240°C, 10 seconds max. (per pin row)

<4> Remove the guide pins.

Figure C-1. Mounting of NQPACK144SD or NQPACK100SD

HQPACK144SD or HQPACK100SD

Guide pins

(NQGUIDE)

NQPACK144SD or NQPACK100SD

Target system

Remark NQPACK144SD or NQPACK100SD: Connector for target connection

HQPACK144SD or HQPACK100SD: Cover for device mounting

User’s Manual U14481EJ2V0UM

73

APPENDIX C CONNECTORS FOR TARGET CONNECTION

(2) When mounting device

Caution Check for abnormal conditions such as resin burr or bent pins before mounting a device on the

NQPACK144SD or NQPACK100SD. Moreover, check that the hold pins of the HQPACK144SD or

HQPACK100SD are not broken or bent before mounting the HQPACK144SD or HQPACK100SD

on top of the device. If there are broken or bent pins, fix them with a thin, flat plate such as a

blade.

<1> Make sure that the NQPACK144SD or NQPACK100SD is clean and the device pins are parallel (flat)

before mounting a device on the NQPACK144SD or NQPACK100SD. Then, after mounting the

NQPACK144SD or NQPACK100SD to the target board, fix the device and the HQPACK144SD or

HQPACK100SD (refer to Figure C-2).

<2> Using the screws provided with the HQPACK144SD or HQPACK100SD (four locations: M2 × 6 mm),

secure the HQPACK144SD or HQPACK100SD, device, and NQPACK144SD or NQPACK100SD.

Tighten the screws in a crisscross pattern with the screwdriver provided or a driver with a torque gauge

(avoid tightening only one screw strongly). Tighten the screws with 0.55 kg⋅f⋅cm (0.054 Nm) max. torque.

Excessive tightening may diminish conductivity.

At this time, each pin is fixed inside the plastic wall dividers by the contact pin of the NQPACK144SD or

NQPACK100SD and the hold pin of the HQPACK144SD or HQPACK100SD (refer to Figure C-3). Thus,

pins cannot cause a short with pins of neighboring devices.

Figure C-2. Mounting of Device

Fastening screws

HQPACK144SD or HQPACK100SD

Device

NQPACK144SD or NQPACK100SD

Target system

Figure C-3. NQPACK144SD or NQPACK100SD and Device Pin

Hold pin of HQPACK144SD or HQPACK100SD

Divider

Device

Contact pin of NQPACK144SD or NQPACK100SD

User’s Manual U14481EJ2V0UM

74

APPENDIX C CONNECTORS FOR TARGET CONNECTION

C.2 Cautions on Handling Connectors (LQFP Package)

(1) When taking connectors out of the case, remove the sponge while holding the main unit.

(2) When soldering the NQPACK144SD or NQPACK100SD to the target system, cover with the HQPACK144SD or

HQPACK100SD to protect it against splashing flux.

Recommended soldering conditions… Reflow:

240°C, 20 seconds max.

Partial heating: 240°C, 10 seconds max. (per pin row)

(3) Check for abnormal conditions such as resin burr or bent pins before mounting a device on the NQPACK144SD

or NQPACK100SD. Moreover, check that the hold pins of the HQPACK144SD or HQPACK100SD are not broken

or bent before mounting the HQPACK144SD or HQPACK100SD. If there are broken or bent pins, fix them with a

thin, flat plate such as a blade.

(4) When securing the YQPACK144SD or YQPACK100SD (connector for emulator connection) or HQPACK144SD or

HQPACK100SD to the NQPACK144SD or NQPACK100SD with screws, tighten the four screws temporarily with

the screwdriver provided or a driver with a torque gauge, then tighten the screws in a crisscross pattern (with

0.054 Nm max. torque).

Excessive tightening of only one screw may diminish conductivity.

If the conductivity is diminished after screw-tightening, stop tightening, remove the screws and check that the

NQPACK144SD or NQPACK100SD is not dirty and make sure the device pins are parallel.

(5) Device pins do not have high strength. Repeatedly connecting to the NQPACK144SD or NQPACK100SD may

cause pins to bend. When mounting a device on NQPACK144SD or NQPACK100SD, check and adjust bent

pins.

User’s Manual U14481EJ2V0UM

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APPENDIX C CONNECTORS FOR TARGET CONNECTION

C.3 Notes on Board Design (FBGA Package)

(1) If a through hole is made in an IC pad or nearby, the cream solder melts and flows into the hole, causing open

pins.

(2) When making a through hole in an IC pad, fill the hole.

(3) If it is necessary to make a through hole near an IC pad, be sure to apply resist between the pad and through hole

as shown in Figure C-4 (a). It is also recommended to apply the resist on the through hole pad. In addition, be

sure to apply resist between pads as shown in Figure C-5 (b).

Figure C-4. Application of Resist

(a) Through hole

(b) Between pads

Pad

Via (through hole)

Resist

Pad

Slanted lines indicate resist

Resist

(4) When connecting pads to each other in a pattern for a power supply or GND, the solder may be hard to melt if the

pattern is too wide because heat diffuses.

(5) To use CSSOCKET with guides, a component hole or through hole is necessary. For the position and dimensions

of the hole, refer to the attached drawing.

The guide pin may be of stainless steel (which cannot be soldered) or may be gold-plated (which can be

soldered). A stainless steel guide pin only serves as a guide, but a gold-plated guide pin can be soldered from the

rear side of the target board if the guide hole is a through hole. This securely attaches the connector and board,

and mitigates the stress applied on the connector.

User’s Manual U14481EJ2V0UM

76

APPENDIX C CONNECTORS FOR TARGET CONNECTION

C.4 Soldering CSSOCKET (Main Enclosure Connector) to Target Board (FBGA Package)

(1) Apply cream solder to the BGA pad of the target board. The thickness of the cream solder on the pad should be

100 to 150 µm. Too thick cream solder may cause short-circuiting.

(2) On the part of CSSOCKET to be connected to LSPACK, protective tape (polyimide tape) is attached for protection

from flux splashing during reflow soldering. Do not remove this tape until reflow soldering is completed.

(3) Place CSSOCKET on the target board, with its guide pins inserted into the holes for the guides on the target

board, as shown in Figure C-5. Confirm that the pad on the board and CSSOCKET are correctly positioned.

(4) Mounting CSSOCKET

<1> The dimensions of CSSOCKET are the same as the actual IC package.

<2> Solder CSSOCKET at a temperature of 210°C or more and for 30 to 60 seconds, as indicated in the table

below.

<3> Table C-1 shows the recommended reflow conditions. Figure C-6 shows an example of the mounting

profile of CSSOCKET.

Table C-1. Recommended Reflow Conditions

Surface Temperature of CSSOCKET Connector

Preheating

Heating

150 to 180°C, 180 seconds

210°C or more, 30 to 60 seconds

(5) Remove the protective tape from the surface.

Figure C-5. Mounting of CSSOCKET on Target Board

CSSOCKET

Target board

Guide pin

Caution Do not clean CSSOCKET to remove flux.

User’s Manual U14481EJ2V0UM

77

APPENDIX C CONNECTORS FOR TARGET CONNECTION

Figure C-6. Example of Mounting Profile of CSSOCKET

CSSOCKET180A (Dimensions: 13 × 13 mm)

300

250

200

150

100

50

CSSOCKET bottom side

(soldering side)

13

Any point on board

CSSOCKET top side

35 seconds at more

than 183°C

Peak: 195°C

0

• 180 pins, 0.8 mm pitch

700

0

100

200

300

400

500

600

• 15 grids, 4 peripheral array type

Time [sec]

Equipment: Air Solder Reflow ARS-301 of Eighteck Tektron

Caution

• Because the construction of CSSOCKET allows flux and cleaning solvent to remain in the connector, do

not dip CSSOCKET into flux or clean it to remove flux. The same applies when using CSSOCKET with

other DIP components, as the flux of the DIP component may get into CSSOCKET.

• To solder the type of CSSOCKET without guide pins, correctly position it on the pad of the board.

• After soldering the CSSOCKET connector, it is recommended to solder the guide pins from the bottom

side of the board or to secure the connector peripheral parts with resin, for reinforcement. Use of two-

component type epoxy resin or a cure-type adhesive agent, and an adhesive agent for securing the

surface mount components is recommended.

User’s Manual U14481EJ2V0UM

78

APPENDIX C CONNECTORS FOR TARGET CONNECTION

C.5 Using LSPACK to Mount IC (FBGA Package)

Attach LSPACK to CSSOCKET, which has already been soldered, using the guide plate, spacer, and top cover.

(1) Align the guides of CSSOCKET and LSPACK, and attach LSPACK to CSSOCKET.

(2) Place the guide plate (included with models released after November 2000) and spacer, in that order, on

LSPACK. Align the guide of the spacer with the component hole of LSPACK and the guide plate.

(3) Noting the position of pin 1 of the IC (BGA), gently place the IC from the top in the opening at the center of the

spacer, aligning it with the connector pin position.

(4) Place the top cover on the spacer. The holes at the four corners of the guide plate, spacer, and top cover must

match. Secure LSPACK and the top cover using the attached screws. Use a dedicated screwdriver to tighten the

screws. Hold LSPACK on the sides with your fingers, so that no stress is applied to the soldered parts of

LSPACK and CSSOCKET, and sequentially tighten the screws at the four corners. The tightening torque should

be 0.55 kg⋅f⋅cm (0.054 Nm) maximum.

(5) To remove the top cover from LSPACK, loosen and remove the screws of the top cover while holding the cover on

sides, so that no stress is applied to the soldered parts of LSPACK and CSSOCKET.

Figure C-7. Mounting of IC

Four round head screws

Top cover

Spacer

Guide plate

LSPACK

CSSOCKET

Target board

User’s Manual U14481EJ2V0UM

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APPENDIX C CONNECTORS FOR TARGET CONNECTION

C.6 Connecting In-Circuit Emulator (FBGA Package)

CSICE connector: Conversion adapter to connect an existing tool supporting TQPACK/NQPACK (QFP) and

LSPACK (Conversion from BGA to QFP). Also for conversion to different pitches of BGA.

Attach LSPACK to CSSOCKET, which has already been soldered, using the guide plate, spacer, and top cover.

(1) Place the pad side of the CSICE connector on LSPACK. Make sure that the positions of the holes at the four

corners match.

(2) Using the attached guide screws (CSGUIDE) for CSICE, secure LSPACK and the CSICE connector. Hold

LSPACK the sides with your fingers, so that no stress is applied to the soldered parts of LSPACK and

CSSOCKET, and sequentially tighten CSGUIDE at the four corners. The tightening torque of CSGUIDE should

be 0.55 kg⋅f⋅cm (0.054 Nm) maximum. To remove the CSICE connector, hold LSPACK so that no stress is

applied to the soldered parts of LSPACK and CSSOCKET, and remove the screws.

Figure C-8. CSICE Connection

CSGUIDE

CSICE connector

User’s Manual U14481EJ2V0UM

80

APPENDIX C CONNECTORS FOR TARGET CONNECTION

C.7 Notes on Handling LSPACK/CSSOCKET (FBGA Package)

Caution When mounting CSSOCKET for the first time, refer to C.3 Notes on Board Design (FBGA

Package), and C.4 Soldering CSSOCKET (Main Enclosure Connector) to Target Board (FBGA

Package).

(1) When taking out LSPACK from the case, hold LSPACK and take out the sponge first.

(2) The case may be deformed if it is left for a long time in a location where temperature is 50°C or higher. Store it in

a location where it is not subject to direct sunlight, and the temperature is 40°C or below.

(3) Protective tape is attached to CSSOCKET for protection from flux splashing during reflow soldering. Do not

remove this tape until reflow soldering is completed.

(4) Recommended reflow conditions

Surface temperature of CSSOCKET

Preheating: 150 to 180°C, 180 seconds

Heating:

210°C or more, 30 to 60 seconds

(5) Because the construction of CSSOCKET allows flux and cleaning solvent to remain in the connector, do not dip

CSSOCKET into flux or clean it to remove flux. The same applies when using CSSOCKET with other DIP

components, as the flux of the DIP component may get into CSSOCKET.

(6) To secure LSPACK with screws, use a dedicated screwdriver (+) or torque driver to tighten the screws at four

places. The tightening torque should be 0.55 kg⋅f⋅cm (0.054 Nm) maximum. Do not tighten one screw too much

as it may cause a faulty contact.

(7) After soldering the CSSOCKET, it is recommended to solder the guide pins from the bottom side of the board or

to secure the connector peripheral parts with resin, for reinforcement.

(8) To use CSSOCKET between CSSOCKET and LSPACK for stacking, exercise care that the pins of CSSOCKET

for stacking are not bent.

(9) Use LSPACK/CSSOCKET as connector of evaluation.

(10)LSPACK/CSSOCKET must not be used in an environment subject to constant shock or vibration.

(11)It is assumed that this product is used for development and evaluation in a system. When using this product

domestically, it is not subject to The Electric Appliance and Material Control Law and protection from

electromagnetic interference.

User’s Manual U14481EJ2V0UM

81

APPENDIX D INSERTING PLASTIC SPACER

This chapter describes the method for inserting the plastic spacer supplied with the IE-V850E-MC-A.

When using the emulator connected to the target system, insert the plastic spacer in the IE-V850E-MC-A as shown

in Figure D-1 to fix the pod horizontally.

•

Inserting plastic spacer in IE-V850E-MC-A

<1> Remove the nylon rivet from the rear part of the pod.

<2> Fix the plastic spacer with the plastic screw supplied.

<3> To adjust the height, use your own spacer or a stand.

Figure D-1. Method of Inserting Plastic Spacer

Plastic spacer

Target system

User’s Manual U14481EJ2V0UM

82

APPENDIX E REVISION HISTORY

The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapter of

each edition in which the revision was applied.

(1/2)

Edition

Major Revision from Previous Edition

Applied to:

CHAPTER 1

2nd edition

1.1 Hardware Configuration Addition of SWEX-xxxSD-1 to extension probes.

Addition of conversion socket for V850E/MA1 (161-pin FBGA). Addition of conversion

socket for V850E/MA2 (100-pin LQFP)

OVERVIEW

Change of 1.2 Features (When Connected to IE-V850E-MC-A) to 1.2 Hardware

Specifications (When Connected to IE-V850E-MC-A)

Change of 1.3 Function Specifications (When Connected to IE-V850E-MC-A) to

1.3 System Specifications of IE-703107-MC-EM1 (When Connected to IE-V850E-

MC-A)

Change of Figure 1-1 System Configuration to Figure 1-1 System Configuration

(V850E/MA1, 144-Pin LQFP)

Addition of Figure 1-2 System Configuration (V850E/MA1, 161-Pin FBGA)

Addition of Figure 1-3 System Configuration (V850E/MA2, 100-Pin LQFP)

1.5 Contents in Carton Addition and modification of description

Modification of Figure 1-4 Contents in Carton

Modification of Figure 1-5 Connection Between IE-V850E-MC-A and IE-703107-

MC-EM1

Modification of Figure 2-1 IE-703107-MC-EM1

CHAPTER 2 NAMES

AND FUNCTIONS OF

COMPONENTS

Addition and modification of description in 2.1 (6) to (10)

2.2 Clock Settings Addition and modification of description

Addition of Figure 2-2 Outline of Clock Settings

Change of Table 2-1 Clock Setting (When the Emulator is Used as a Stand-Alone

Unit) to Table 2-1 List of Hardware Settings for Each Clock Setting

Change of Table 2-2 Clock Setting (When the Emulator is Used in Target System

Connection) to Table 2-2 Settings When Using Mounted Internal Clock

Addition of Figure 2-3 Outline When Using Mounted Internal Clock

Addition of Table 2-3 Settings When Changing Mounted Internal Clock

Addition of Figure 2-4 Outline When Changing Mounted Crystal Oscillator and

Using It as Internal Clock

Addition of Table 2-4 Settings When Using External Clock

Addition of Figure 2-5 Outline When Using Crystal Oscillator on Target System as

External Clock

Modification of 2.3 MODE Pin Setting to 2.3 Operation Mode Settings

Addition and modification of description in 2.4 Power Supply Settings

Addition of 2.5 Emulation Memory

Addition and modification of description in CHAPTER 3 FACTORY SETTINGS

CHAPTER 3

FACTORY SETTINGS

Addition and modification of description in CHAPTER 4 CAUTIONS

CHAPTER 4

CAUTIONS

User’s Manual U14481EJ2V0UM

83

APPENDIX E REVISION HISTORY

(2/2)

Edition

Major Revision from Previous Edition

Applied to:

2nd edition

Addition of CHAPTER 5 DIFFERENCES BETWEEN TARGET DEVICES AND TARGET

CHAPTER 5

INTERFACE CIRCUITS

DIFFERENCES

BETWEEN

TARGET

DEVICES AND

TARGET

INTERFACE

CIRCUITS

A.1 Corresponding Package Dimensions

• Modification of (1)

APPENDIX A

DIMENSIONS

• Addition of (3) to (5) and (9) to (18)

A.2 Conditions for Connecting of In-Circuit Emulator Option Board and Conversion

Connector

• Addition of (1) to (3)

Change of (3) Connection between emulator and target system to (2) When

APPENDIX B

EXAMPLE OF

USE OF

connecting device using connector for target connection (b) FBGA package

CONNECTOR

FOR TARGET

CONNECTION

Addition and modification of description in C.1 Usage (LQFP Package)

APPENDIX C

CONNECTORS

FOR TARGET

CONNECTION

Addition and modification of description in C.2 Cautions on Handling Connectors (LQFP

Package)

Addition of C.3 Notes on Board Design (FBGA Package)

Addition of C.4 Soldering CSSOCKET (Main Enclosure Connector) to Target Board

(FGBA Package)

Addition of C.5 Using LSPACK to Mount IC (FBGA Package)

Addition of C.6 Connecting In-Circuit Emulator (FBGA Package)

Addition of C.7 Notes on Handling LSPACK/CSSOCKET (FBGA Package)

Modification of Figure D-1 Method of Inserting Plastic Spacer

APPENDIX D

INSERTING

PLASTIC SPACER

84

User’s Manual U14481EJ2V0UM


型号：	IE-703107-MC-EM1
厂家：	ETC
描述：	IE-703107-MC-EM1 User＇s Manual \| User＇s Manual[09/2003] IE- 703107 -MC- EM1用户手册\|用户手册[ 09/2003 ]\n
文件：	总84页 (文件大小：1294K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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