IPM6220CB [ETC]

Analog IC ; 模拟IC\n


型号：	IPM6220CB
厂家：	ETC
描述：	Analog IC 模拟IC\n 模拟IC 开关光电二极管
文件：	总11页 (文件大小：127K)
中文：	中文翻译
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IPM6220

Data Sheet

July 2000

File Number 4903

PRELIMINARY

Multi-Output System Electronics

Regulator for Mobile PCs

Features

• Provides Five Regulated Voltages

- +5V-ALWAYS

- +3.3V-ALWAYS

- +5V-MAIN

[ /Title

(IPM6

220)

/Subjec

The IPM6220 provides the power control and protection for

five output voltages required in high-performance notebook

PC applications. The IC integrates three fixed frequency

pulse-width-modulation (PWM) controllers and two linear

regulators along with monitoring and protection circuitry into a

single 24 lead SSOP package.

- +3.3V-MAIN

- +12V

(Multi-

Output

System

Electro

nics

• High Efﬁciency Over Wide Load Range

- Synchronous Buck Converters on Main Outputs

- Hysteretic Operation at Light Load

The two PWM controllers regulate the system main +5V and

+3.3V voltages with synchronous-rectified buck converters.

Synchronous rectification and hysteretic operation at light

loads contributes to a high efficiency over a wide range of load

variation. Efficiency is even further enhanced by using FETs

• No Current-Sense Resistor Required

- Uses MOSFET’s r

DS(ON)

Regula

tor for

Mobile

PCs)

/Autho

r ()

/Keyw

ords

(Intersi

Corpor

ation,

semico

nducto

Multi-

Output

System

Electro

nics

Regula

tor for

Mobile

PCs)

/Creato

r ()

as a current sense resistor. Feed-forward ramp

- Optional Current-Sense Resistor for Precision

Overcurrent

DS(ON)

modulation, current mode control scheme, internal feed-back

compensation provide fast and firm transients handling when

powering advanced CPUs and chip sets.

• Operates Directly From Battery 5.6V to 24V Input

• Input Undervoltage Lock-Out (UVLO)

• Excellent Dynamic Response

The third PWM controller regulates output voltage of +12V

boost converter.

- Combined Voltage Feed-Forward and Current Mode

Control

Two linear regulators provide +5-ALWAYS and +3.3-ALWAYS

low current outputs required by the notebook system controller.

• Power-Good Output Voltages Monitor

• Out of Phase Clock Generator

The IPM6220 monitors all the output voltages. A single Power-

Good signal is issued when soft start is completed and all

outpovervoltage protection latches the chip off to prevent output

voltages from going above 115% of their settings. Undervoltage

protection latches the chip off when any of the output drops

below 75% of its setting value after soft-start sequence is

completed. The PWM controller’s over-current circuitry monitor

the output currents by sensing the voltage drop across the

lower MOSFETs. If precision current-sensing is required, an

external current-sense resistors may optionally be used.

• Separate Shutdown Pins for Advanced Conﬁguration

Power Interface (ACPI) Compliance

• 300kHz Fixed Switching Frequency

• Thermal Shutdown

Applications

•

Mobile PCs

• Hand-Held Portable Instruments

Pinout

Related Literature

• Technical Brief TB363 “Guidelines for Handling and

Processing Moisture Sensitive Surface Mount Devices

(SMDs)”

IPM6220 (SSOP)

TOP VIEW

VBATT

3.3V-ALWAYS

BOOT2

24 BOOT1

23 UGATE1

22 PHASE1

21 ISEN1

Ordering Information

PART NUMBER

TEMP. ( C)

PACKAGE

PKG. NO.

UGATE2

PHASE2

20 LGATE1

19 PGND1

18 VSEN1

17 SDWN1

16 GATE3

15 VSEN3

14 GND

IPM6220CB

0 to 70

24 Ld SSOP

M24.15-P

5V-ALWAYS

LGATE2

/DOCI

NFO

PGND2

ISEN2

VSEN2 10

SDWN2 11

PGOOD 12

13 SDWNALL

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

IPM6220

Generic Mobile Power System Diagram

BATT

PROCESSOR

5V-MAIN

SDWN1

SDWN2

CORE

µP CORE

3.3V-MAIN

I/O

5V-ALWAYS

3.3V-ALWAYS

12V

I/O

IPM6220

IPM6210

VID CODE

SDWN

µC8051

CLOCK

RESET

PGOOD

ENABLE

SDWNALL

ON/OFF

IPM6220

Absolute Maximum Ratings

Thermal Information

Input Voltage, VBATT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +30.0V

Phase, Isen and SDWNALL Pins. . . . . . . . . . . . GND-0.3V to +30.0V

BOOT and UGATE Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +35.0V

IBOOT1,2 with Respect to PHASE1,2 . . . . . . . . . . . . . . . . . . . . +7.0V

SDWN1, SDWN2 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V

All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.3V to 15V

ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 2

Thermal Resistance (Typical, Note 1)

θ_JA( C/W)

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SSOP Package (with 3 in of copper). . . . . . . . . . .

TBD

Thermal Resistance (Typical, Note 1)

θ_JC( C/W)

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28.5

Maximum Junction Temperature (Plastic Package) . . . . . . . .150 C

Maximum Storage Temperature Range. . . . . . . . . . -65 C to 150 C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300 C

Recommended Operating Conditions

(SSOP - Lead Tips Only)

Input Voltage, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . +5.6V to +24.0V

Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0 C to 70 C

Junction Temperature Range. . . . . . . . . . . . . . . . . . . . 0 C to 125 C

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. θ is measured with the component mounted on an evaluation PC board in free air.

Electrical Speciﬁcations Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

VCC SUPPLY

VBATT

5.6

Quiescent Current

LGATE1, LGATE2, UGATE1, UGATE2,

GATE3 Open

1.4

Standby Current

µA

CCSB

Shutdown Current

CCSN

INPUT UVLO

Rising VBATT Threshold

Falling VBATT Threshold

OSCILLATOR

4.4

3.9

4.5

4.0

4.6

4.1

PWM1,2 Oscillator Frequency

Ramp Amplitude, Peak to Peak

Ramp Offset

255

300

345

kHz

c1,2

Vin=16V

0.5

125

ROFF

Ramp/V

Gain

mV/V

BAT

REFERENCE AND SOFT START

Internal Reference Voltage

Reference Voltage Accuracy

Soft-Start Current During Startup

PWM 1 CONVERTER, 5V MAIN

Output Voltage

-1.0

2.5

+1.0

REF

µA

4.9

4.97

5.1

+2.0

3.75

TBD

OUT1

Load Regulation

100mA < I

< 5.0A; 5.6V < V

< 24.0V -2.0

BATT

-0.6

VOUT1

Undervoltage Shutdown Level

Overcurrent Comparator Threshold

Overvoltage Shutdown

2µs delay

UV1

OC1

5.75

TBD

OVP1

Switchover to Hysteretic Operation Threshold

PWM 2 CONVERTER, 3.3V MAIN

Output Voltage

HYST1

3.234 3.29 3.366

OUT2

Load Regulation

100mA < I

< 5.0A; 5.6V<V

< 24.0V

BATT

-2.0

-0.3

+2.0

2.48

TBD

VOUT2

Undervoltage Shutdown Level

Overcurrent Comparator Threshold

2µs Delay

UV2

OC2

IPM6220

Electrical Speciﬁcations Recommended Operating Conditions, Unless Otherwise Noted. Refer to Figures 1, 2 and 3 (Continued)

PARAMETER

Overvoltage Shutdown

SYMBOL

TEST CONDITIONS

MIN

3.80

TBD

TYP

MAX

UNITS

OVP2

Switchover to Hysteretic Operation

PWM1, 2 CONTROLLER GATE DRIVERS

Upper Drive Source Current

Upper Drive Pullup Resistance

Upper Drive Sink Current

HYST1

0.5

Ω

2UGON

2UGPUP

2UGOFF

0.75

Upper Drive Pulldown Resistance

Lower Gate Source Current

Lower Drive Pullup Resistance

Lower Gate Sink current

2UGPDN

0.5

2LGON

2LGPUP

2LGOFF

Lower Drive Pulldown Resistance

PWM 3 CONVERTER

1.5

2LGPDN

Output Voltage

VOUT3

Determined by external resistor divider

-2.0

2.0

Load Regulation

10mA < I

< 120mA

VOUT3

Undervoltage Shutdown Level

Overcurrent Shutdown

2µs delay

UV3

Maximum current which causes undervoltage

shutdown

120

360

oc3

Overvoltage Shutdown

17.5

100

kHz

OVP3

PWM3 Oscillator Frequency

Ramp Amplitude, Peak to Peak

Maximum Duty Cycle

115

PWM 3 CONTROLLER GATE DRIVERS

Source, Sink Current

0.5

Pullup, Pulldown Resistance

5V-ALWAYS AND 3.3V-ALWAYS

Linear Regulator Accuracy

Maximum Output Current

Overcurrent Shutdown

Ω

5.6V < V

< 24V; 0 < I

load

< 50mA

-2.0

+2.0

100

BATT

Undervoltage Shutdown

Bypass Switch r

DS(ON)

Ω

POWER GOOD AND CONTROL FUNCTIONS

Power Good Threshold for PWM1 and PWM2

-14

4.3

2.8

-12

-10

4.5

3.0

0.5

Threshold Voltage

4.4

PGD1

PG1

PG2

2.9

PWM2

PGOOD Leakage Current

PGOOD Voltage Low

= 5.0V

µA

PGLKG

PULLUP

= -4mA

PGOOD

PGOOD Min Pulse Width

SDWN1, 2,ALL- Low (OFF)

SDWN1, 2, - High (ON)

SDWNALL - High (ON)

µs

PGmin

0.8

2.0

3.0

Block Diagram

VBATT

CLK

BOOT1

GND

VSEN3

GATE3

HGDR1

UGATE1

PHASE1

BOOST

CON-

TROLLER

SHUTOFF

POWER-ON

RAMP 2

RAMP 1

CLK1

RESET (POR)

GATE LOGIC 1

GATE

CONTROL

CLK2

CLK1

POR

DEADT

VCC

PWM/HYST

PWM ON

LGDR1

OVP1

LGATE1

PGND1

BOOT2

HYST ON

UGATE2

PHASE2

HGDR2

HYST COMP1

SHUTOFF

CLK1

GATE LOGIC 2

OC COMP1

GATE

CONTROL

PWM

DEADT

PWM/HYST

OC LOGIC1

VCC

LATCH 1

IPM6220

EA1

LGDR2

OVP2

LGATE2

PGND2

Q D

PWM ON

VSEN1

HYST ON

REF1

VOLT-

SECOND

CLAMP

HYST COMP2

∑

FAST FEEDBACK COMP1

CLK2

FFBK1

LGATE1

R1 = 20K

OC COMP2

ISEN1

PWM

LATCH 2

LOGIC2

VCC

2.8V

EA2

D Q

VSEN2

VBATT

REF2

VOLT-

SECOND

CLAMP

∑

POR

VSEN1

FFBK2

SDWN1

FAST FEEDBACK COMP2

LDO1

LGATE2

ISEN2

R1 = 20K

SDWN

LGATE2

REFERENCE

SDWN2

REF1

REF2

AND

OUTPUT

VOLTAGE

LDO2

SOFT START

SDWNALL

MONITOR

3.3V-ALWAYS

5V-ALWAYS

PGOOD

FIGURE 1.

IPM6220

VSEN1, VSEN2 (Pin 18, 10)

Functional Pin Description

These pins are connected to the main outputs and provide

voltage feedback signal for respective PWM controllers. The

PGOOD and OVP circuits use these signals to report output

voltage status and for overvoltage protection.

VBATT (Pin 1)

Supplies all the power necessary to operate the chip. IC

starts to operate when voltage on this pin exceeds 4.5V and

stops to operate when voltage on this pin drops below 4.0V.

Also provides battery voltage to the oscillator for feed-

forward rejection of the input voltage variation.

SDWN2 (Pin 11)

This pin provides enable/disable function and soft start for

PWM2 controller. Controller is enabled when this pin is

pulled high and SDWNALL is high too. Controller is off when

the pin is pulled to the ground. To realize the soft-start

function, terminate this pin with a capacitor. Soft-start time

can be obtained from the following equitation.

3.3V-ALWAYS (Pin 2)

Output of 3.3V-AlWAYS linear regulator.

5V-ALWAYS (Pin 6)

Output of 5V-ALWAYS linear regulator.

3.5V × Css2

Tss1 = ---------------------------------

5µA

BOOT1, BOOT2 (Pins 24 and 3)

Through these pins power is supplied to the upper MOSFET

drivers of PWM1 and PWM2 converters. Connect these pins

to respective junctions of bootstrap capacitors with the

cathodes of the bootstrap diodes. Anodes of the bootstrap

diodes are connected to pin 3, 5V-ALWAYS.

PGOOD (Pin 12)

PGOOD is an open drain output used to indicate the status

of the PWM converters’ output voltages. This pin is pulled

low when any of the outputs except PWM3 (+12V) is not

within ±10% of respective nominal voltages, or when PWM3

(+12V) is not in between its undervoltage and overvoltage

thresholds.

UGATE1, UGATE2 (Pins 23 and 4)

These pins provide the gate drive for the upper MOSFETs.

Connect UGATE pins to the respective PWM converter’s

upper MOSFET gate.

SDWNALL (Pin 13)

This pin provides enable/disable function for all outputs. The

chip is completely disabled, no output is present when this

pin is pulled to the ground. When this pin is pulled high,

5V-ALWAYS and 3.3-ALWAYS outputs are regulated. Status

of the other outputs depends on SDWN1 and SDWN2.

PHASE1, PHASE2 (Pins 22 and 5)

The so called PHASE points are the junction points of the

upper MOSFET sources, output ﬁlter inductors, and lower

MOSFET drains. Connect the PHASE pins to the respective

PWM converter’s upper MOSFET source.

GND (Pin 14)

ISEN1, ISEN2 (Pins 21 and 9)

Signal ground for the IC. All voltage levels are measured with

respect to this pin.

These pins are used to monitor the voltage drop across the

lower MOSFETs for current feedback and over-current

protection. For precise current detection these inputs could

be connected to optional current sense resistors placed in

series with sources of the lower MOSFETs. To set the gain

of the current sense ampliﬁer, resistor should be placed in

series with each of those inputs. Value of the resistor

required can be obtained from the following equation:

VSEN3 (Pin 15)

This pin provides voltage feedback signal for PWM3

controller. The PGOOD and OVP circuits use this pin to

report output voltage status and for overvoltage protection.

Also, this pin is used to independently disable PWM3

controller when not used. Connect this pin to 5V-ALWAYS if

the boost converter is not populated in your design.

20k • Iosc • Rcs

= --------------------------------------------

Vth

GATE3 (Pin 16)

This pins drives the boost MOSFET.

where: Iosc - desired overload current; Rcs - either r

DS(ON)

the lower MOSFET, or the value of the optional current sense

resistor; Vth - threshold of the current protection circuitry.

SDWN1 (Pin 17)

This pin provides enable/disable function and soft-start for

PWM1 controller. Controller is enabled when this pin is

pulled high and SDWNALL is high too. Controller is off when

the pin is pulled to the ground. To realize the soft-start,

terminate this pin with a capacitor. Soft-start time can be

obtained from the following equation.

LGATE1, LGATE 2 (Pins 20 and 7)

These pins provide the gate drive for the lower MOSFETs.

Connect the lower MOSFET gate of each converter to the

corresponding pin.

PGND1, PGND2 (Pins 19 and 8)

3.5V × Css1

Tss1 = ---------------------------------

5µA

These are the power ground connection for PWM1 and

PWM2 converters, respectively. Tie each lower MOSFET

source to the corresponding pin.

IPM6220

the converter continuously delivers power about two times

the nominal without significant drop in the output voltage.

Description

Operation

To eliminate this, the time delay circuit (8:1 counter which

counts the clock cycles) is activated when the overcurrent

condition is detected for the first time. This limits the

inductor current buildup and essentially switches the

converter into current regulation mode for a short period of

time (eight clock cycles). If after the delay the overcurrent

condition is still present, the converter shuts down. If not -

the normal operation restores.

The IIPM6220 addresses system electronics power needs of

modern notebook and sub-notebook PCs. The IC integrates

control circuits for two synchronous buck converters for

+5.0V and +3.3V busses, two linear regulators for

3.3V-ALWAYS and 5V-ALWAYS, and control circuit for +12V

boost converter.

The PWM converters use the same clock generator with two

out-of-phase outputs. This reduces input current ripple and

requirements to the input ﬁlter.

This overcurrent scheme has been proven to be very

robust in applications like portable computers where fast

inductor current buildup is common due to a big difference

between input and output voltages and a low value of the

inductor.

The +12V boost controller uses 100kHz clock derived from

the main clock. This controller uses front edge PWM scheme

with maximum duty factor limited to 33%.

The chip has three input lines SDWN1, SDWN2 and

SDWNALL for advanced control power interface (ACPI) to

allow turn on and off all outputs, as well as independently

control +3.3V and +5V outputs.

Operation Mode Control

The mode control circuit changes the converter’s mode of

operation depending on the level of the load current. At

nominal current converter operates in ﬁxed frequency PWM

mode. When the load current drops lower than the critical

value, inductor current becomes discontinuous and the

operation mode is changed to hysteretic.

To maximize efﬁciency, current sense technique based on

MOSFET r

voltage drop is used. If accurate current

DS(ON)

protection is desired, current sense resistors can optionally

be used. Light load efﬁciency is enhanced by a hysteretic

mode of operation which is automatically engaged when

inductor current becomes discontinuous.

The mode control circuit consists of a ﬂip-ﬂop which outputs

provide HYST and NORMAL signals. These signals inhibit

normal PWM operation and activate hysteretic comparator

and diode emulation mode of the synchronous FET.

3.3V and 5V Architecture

Main outputs are generated from the unregulated DC source

by two independent synchronous buck converters. IC

integrates all the components required for output adjustment

and feedback compensation signiﬁcantly reducing the

number of external parts.

The inputs of the ﬂip-ﬂop are controlled by outputs of two

delay circuits, which constantly monitor output of the phase

node comparator. High level on the comparator output

during PWM cycle is associated with continuous mode of

operation. The low level - corresponds to the discontinuous

mode of operation. When the low level on the comparator

output is detected eight times in a row, the mode control ﬂip-

ﬂop is set and converter is commanded to operate in the

hysteretic mode. If during this pulse counting process the

comparator's output happens to be high, the counter of the

delay circuit will be reset and circuit will continue to monitor

for eight low level pulses in a row from the very beginning.

These buck PWM controllers are identical and employ ﬁxed

frequency current mode control scheme with addition of

feed-forward ramp programming for better rejection of the

input voltage variation. They use out-off-phase sequences

from the same unadjusted frequency clock oscillator to

reduce input current ripple.

Current Sensing and Overcurrent Protection

Both PWM converters employ the lower MOSFET on-state

TABLE 1. POWER CONTROL

3V AND

resistance, r

as a current sensing element. This

DS(ON)

technique eliminates need in a current sense resistor and

power losses usually associated with it.

SDWNALL SDWN1 SDWN2 ALWAYS MAIN 5V MAIN

The sensed voltage drop is used for the current feedback

and the overcurrent protection. The r

voltage drop is

DS(ON)

sampled after about 200ns after the lower MOSFET is

turned on.

The sampled voltage after amplification is compared with

internally set overcurrent threshold. To accommodate wide

range of the r

variation, the value of the overcurrent

DS(ON)

threshold should represent overload current about 180% of

the nominal value. This could lead to the situation where

IPM6220

the soft start capacitors can be calculated from the following

expression.

VOUT

IIND

5µA × t

Css= --------------------------

3.5V

Where: t - is a desired soft start time, and 3.5V is a

voltage on the soft start capacitor when undervoltage

protection is enabled.

PHASE

COMP

By varying the values of soft start capacitors it is

possible to provide sequencing of the main

outputs at startup.

HYSTERETIC

MODE

PWM

OPERATION

Gate Control Logic

FIGURE 2.

The gate control logic translates generated PWM control

signals into the MOSFET gate drive signals providing

necessary ampliﬁcation, level shift and shoot-trough

protection. Also, it bears some functions that help optimize

the IC performance over a wide range of the operational

conditions. As MOSFET switching time can very dramatically

from type to type and with the input voltage, gate control

logic provides adaptive dead time by monitoring gate

voltages of both upper and lower MOSFETs.

The circuit which restores normal PWM operation mode

works in the same way and is looking for eight in a row high

level pulses on the comparator's output. If during this

counting process the comparator’s output happens to be low,

the counter will be reset and the mode control ﬂip-ﬂop will

not change the state. The operation mode will only be

changed when eight pulses in a row ﬁll the counter. This

technique prevents jitter and chatter of the operation mode

at the load levels close to the critical.

12V Converter Architecture

The 12V boost converter generates its output voltage from

the main 5V output. An external inductor, a diode and a

capacitor are required to complete the circuit. The output

signal is fed back to the controller via an external resistive

divider. The divider allows to adjust the output voltage as

necessary. For example, to accommodate the linear

regulator if higher level of regulation is required. The boost

controller can be disabled in the systems where there is no

need for 12V power by connecting VSEN3 pin to

5V-ALWAYS rail.

Light Load (Hysteretic) Operation

In the light load (hysteretic) mode the output voltage is

regulated by the hysteretic comparator which forces the

upper gate driver high when the output voltage drops lower

the certain level. When the output voltage rises above the

set point the upper gate driver is inhibited.

Voltage on the non-inverting input of the hysteretic

comparator is a reference voltage with a small addition of the

clock frequency pulses. Such a scheme allows to

synchronize the upper MOSFET turn-on with the main clock

and contributes positively to the seamless transition between

the operation modes.

The control circuit for the 12V converter consists of a 3:1

frequency divider which drives a ramp generator and resets

a PWM latch (Figure 2). The length of the CLK/3 pulses is

equal to the period of the main clock. Thus, duty factor of the

pulse sequence after the divider is limited to 1/3. An output

of a non-inverting error ampliﬁer is compared with the rising

ramp voltage. When the ramp voltage becomes higher than

the error signal, the PWM comparator sets the latch and the

output of the gate driver is pulled high. The rising edge of the

CLK/3 pulses resets the latch and pulls the output of the

gate driver low. Operation of the circuit repeats after two idle

periods of the main clock.

3.3V and 5V Soft Start, Sequencing and Standby

The 5V and 3.3V converters are enabled if SDWN1 and

SDWN2 are high (open) and SDWNALL is also high. The

standby mode is deﬁned as a condition when SDWN1 and

SDWN2 are low and PWM converters are disabled but

SDWNALL is high (3.3V-ALWAYS and 5V-ALWAYS outputs

are enabled).

Soft start of the 3.3V and 5V converters is accomplished by

means of the capacitors connected from pins SDWN1 and

SDWN2 to the ground. In conjunction with pull up to +VCC

5µA current sources they provide controlled rise of the

voltage on these pins. The output voltage of the converter

should reach the regulation before the voltage on the soft

start capacitor reaches the threshold of 3.5V. The value of

IPM6220

The 12V converter starts to operate at the same time as the

VSEN3

REF

GATE3

5V converter. The softly rising voltage on the 5V output

accompanied with limited to 33% maximum duty factor

provides softly rising 12V output. The total capacitance on

the 12V output should be chosen appropriately, so that the

output voltage can buildup higher than the undervoltage limit

(9V) during the soft start time in order to avoid triggering of

the undervoltage protection.

PWM

COMPARATOR

LATCH 3

EA3

CLK/3

DIVIDER

CLK

RAMP

GENERATOR

3:1

CLK/3

Over Temperature Protection

The chip incorporates an over temperature protection circuit

that shuts all the outputs down when the die temperature of

CLK

150 C is reached. Normal operation restores at the die

CLK/3

temperatures below 125 C trough the full soft-start by

cycling the input voltage.

RAMP

VEA3

3V-ALWAYS, 5V-ALWAYS Linear Regulators

GATE3

The 3.3V-ALWAYS and 5V-ALWAYS outputs are derived

from the battery voltage and are the ﬁrst voltages available in

the notebook when the power button is pushed down

(Figure 2). The 5V-ALWAYS output is generated directly

from the battery voltage by a linear regulator and is used to

power the chip itself, the CPU regulator and their gate

drivers. The 3.3V-ALWAYS output is used to power the

keyboard controller and is generated from the 5V-ALWAYS

output. The total current capability of these outputs is 50mA.

When the system 5V rail is enabled and regulated, the

5V-ALWAYS output is connected to it via an internal 1Ω

switch. Simultaneously, the 5V-AWAYS linear regulator is

disabled to protect the chip from the excessive power

dissipation.

FIGURE 3.

The fact that the maximum duty factor of the converter is

limited to 1/3 allows for guaranteed discontinuous inductor

current operation over the all operation conditions. The

inductor should be kept lower some critical value.

Vinmin × Dmax × Ro

Lmax= ----------------------------------------------------------------

2 × Vo × F

where, Vinmin -- minimum input voltage; Dmax=1/3 --

maximum duty factor; Ro -- nominal load resistance; Vo --

nominal output voltage; F -- the switching frequency.

The boost converter with the limited duty factor in the

discontinuous inductor current mode can deliver to the load

and correspondingly draw from the source only certain

amount of energy. The output voltage starts to drop when

the maximum duty factor is reached.

IPM6220 DC-DC Converter Application

Circuit

Figure 4 shows an application circuit of a power supply for a

notebook PC microprocessor system. The power supply

provides +5V_ALWAYS, +3.3V_ALWAYS, +5.0V, +3.3V, and

+12.0V from +5.6-24V

battery voltage. For detailed

Vo= Vin × Dmax × ----------------------

2 × L × F

information on the circuit, including a Bill-of-Materials and

circuit board description, see Application Note ANXXXX.

Also see Intersil’s web site (www.intersil.com) or Intersil

AnswerFAX (321-724-7800) for the latest information.

Thus, providing automatic output overcurrent limiting. If the

value of the inductor is chosen properly, the output current

twice as high as a nominal will pull the output voltage down

to the point were the undervoltage protection comes into

effect.

IPM6220

+5-24V

C7-8

56µF

2x1µF

GND

CR1

BAT54WT1

VBATT

+3.3V-ALWAYS

(50mA)

BOOT1

3.3V-ALWAYS

5V-ALWAYS

10µF

0.22µF

UGATE1

PHASE1

+5V-ALWAYS

(50mA)

ITF86130SK8

+5V

(5A)

C10

680µF

8µH

ISEN1

68µF

CR2

BAT54WT1

680

IPM6220

BOOT2

6.8µH

LGATE1

PGND1

ITF86130SK8

0.22µF

UGATE2

PHASE2

+3.3V

(5A)

CR3

MBRS130

VSEN1

GATE3

ISEN2

680

8µH

HUF76113SK8

C11,C12

2x68µF

97K6

LGATE2

PGND2

680µF

ITF86130SK8

24K9

VSEN3

SDWN1

VSEN2

SDWN2

0.01µF

C13

0.01µF

SDWNALL

PGOOD

GND

FIGURE 4. APPLICATION CIRCUIT

IPM6220

Shrink Small Outline Plastic Packages (SSOP/QSOP)

M24.15-P

24 LEAD SHRINK NARROW BODY SMALL OUTLINE

PLASTIC PACKAGE

INDEX

AREA

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

MIN

MAX

1.75

NOTES

0.053

0.007

0.008

0.007

0.337

0.149

0.069

0.011

0.012

0.010

0.344

0.157

1.35

0.178

0.203

0.178

8.56

0.279

0.305

0.254

8.74

SEATING PLANE

h x 45

3.78

3.99

0.025 BSC

0.635 BSC

0.228

0.244

5.79

6.20

0.10(0.004)

0.015

0.38

0.17(0.007) M

0.016

0.050

0.41

1.27

NOTES:

1. Dimension “D” does not include mold flash, protrusions or gate burrs.

2. Dimension “E” does not include interlead flash or protrusions.

3. “L” is the length of terminal for soldering to a substrate.

4. “N” is the number of terminal positions.

Rev. 1 7/96

5. Terminal numbers are shown for reference only.

6. Controlling dimension: INCHES. Converted millimeter dimensions

are not necessarily exact.

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.

Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-

out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site www.intersil.com

Sales Ofﬁce Headquarters

NORTH AMERICA

EUROPE

ASIA

Intersil Corporation

Intersil SA

Intersil Ltd.

P. O. Box 883, Mail Stop 53-204

Melbourne, FL 32902

TEL: (321) 724-7000

FAX: (321) 724-7240

Mercure Center

8F-2, 96, Sec. 1, Chien-kuo North,

Taipei, Taiwan 104

Republic of China

TEL: 886-2-2515-8508

FAX: 886-2-2515-8369

100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111

FAX: (32) 2.724.22.05

IPM6220CB [ETC]

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