ML610Q338 [ROHM]
ML610Q327/ML610Q338/ML610Q339是内置蓝碧石科技自有的RISC架构8位CPU“U8 Core”的、具有语音输出功能的高性能8位微控制器。产品搭载了高音质的语音播放功能和高输出扬声器放大器，以单芯片实现了语音输出功能，非常适用于警报器和家电应用。为了实现高音质的语音播放功能，利用新开发的高音质、高压缩比的语音压缩算法HQ-ADPCM，可以用比以往ADPCM更少的数据量来确保清晰的声音和宽广的音域，从而实现百听不厌、悦耳动听的声音。ML610Q327的播放时间约为70秒*1，ML610Q338/ML610Q339的播放时间约为95秒*1。此外，还可以外接高达128Mbit的Flash存储器，因此也支持更长时间的播放。通过将这种出色的语音播放功能、低功耗高性能的U8 Core、支持3V/5V的电源以及丰富的外围控制功能集成于1枚芯片，为电池驱动和AC驱动的产品提供单芯片语音播放解决方案。*：程序区使用16KB、采样频率为6.4kHz、选择HQ-ADPCM时。;
| 型号： | ML610Q338 |
| 厂家： | 
ROHM |
| 描述： | ML610Q327/ML610Q338/ML610Q339是内置蓝碧石科技自有的RISC架构8位CPU“U8 Core”的、具有语音输出功能的高性能8位微控制器。产品搭载了高音质的语音播放功能和高输出扬声器放大器，以单芯片实现了语音输出功能，非常适用于警报器和家电应用。为了实现高音质的语音播放功能，利用新开发的高音质、高压缩比的语音压缩算法HQ-ADPCM，可以用比以往ADPCM更少的数据量来确保清晰的声音和宽广的音域，从而实现百听不厌、悦耳动听的声音。ML610Q327的播放时间约为70秒*1，ML610Q338/ML610Q339的播放时间约为95秒*1。此外，还可以外接高达128Mbit的Flash存储器，因此也支持更长时间的播放。通过将这种出色的语音播放功能、低功耗高性能的U8 Core、支持3V/5V的电源以及丰富的外围控制功能集成于1枚芯片，为电池驱动和AC驱动的产品提供单芯片语音播放解决方案。*：程序区使用16KB、采样频率为6.4kHz、选择HQ-ADPCM时。 电池 放大器 PC 驱动 控制器 微控制器 高压 存储 |
| 文件： | 总40页 (文件大小：1040K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FEDL610Q339-01
Issue Date: Apr. 18, 2022
ML610Q327/38/39
8-bit Microcontroller with Voice Output Function
GENERAL DESCRIPTION
Equipped with a 8-bit CPU nX-U8/100, the ML610Q327/338/339 is a high-performance 8-bit CMOS microcontroller that
integrates a wide variety of peripherals such as timer, PWM, UART, I2C bus interface, synchronous serial port, successive
approximation type 10-bit A/D converter and voice output function. The nX-U8/100 CPU is capable of executing instructions
efficiently on a one-instruction-per-clock-pulse basis through parallel processing by the 3-stage pipelined architecture. The
ML610Q327/338/339 is also equipped with a flash memory* that has achieved low voltage and low power consumption (at
read) equivalent to mask ROM, so it is best suited to battery-driven applications such as alarm and portable devices. In addition,
it has an on-chip debugging function, which allows software debugging/rewriting with the LSI mounted on the board.
*: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc.
SuperFlash® is a registered trademark of Silicon Storage Technology, Inc.
This product consists of seven varieties of LSI whose package and flash memory size are different each other.
LSI list of this product which has 48pin to 64pin and 192Kbyte*1 to 256Kbyte*1 in the lineup is shown below.
LSI List of This Product
Flash memory
(Program area),
Estimated audio
playback time
The number of pins, Package, Product name
48pin
52pin
64pin
TQFP48
TQFP52
TQFP64
256Kbyte*1, 95s*2
－
ML610Q338
ML610Q339
192Kbyte*1, 69s*2
ML610Q327
－
－
*1: Including unusable 1Kbyte test data area
*2: In case 16Kbyte is used for control program, 6.4kHz sampling frequency and HQ-ADPCM are
selected
Please see last 2 pages; “Notes for product usage” and “Notes” in this document on use with this production.
FEATURES
•CPU
− 8-bit RISC CPU (CPU name: nX-U8/100)
− Instruction system: 16-bit instructions
− Instruction set:
Transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit
manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on
− On-Chip debug function
− Minimum instruction execution time
Approx 30.5 s (@32.768kHz system clock)
Approx 0.244 s (@4.096 MHz system clock)@VDD=2.0 to 5.5V
Approx 0.122 s (@8.192 MHz system clock)@VDD=2.2 to 5.5V
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•Internal memory
− Flash-memory (Program area)
Product
Program area
192Kbyte ( 96K×16bits)*3
256Kbyte (128K×16bits)*3
Rewrite cycle
100 times
ML610Q327
ML610Q338/ML610Q339
*3: Including unusable 1Kbyte test data area
− Data Flash memory: 2Kbyte (1K×16 bits) Rewrite cycle: 10,000 times
Built into Back Ground Operation (BGO) function (CPU continues program processing while the data flash
erase/write)
− Internal RAM : 4Kbyte (4K 8 bits)
•Interrupt controller
− 1 non-maskable interrupt source
Internal source: 1(Watchdog timer)
− 29 maskable interrupt sources
Internal source: 21(Data flash erase/write completion, SSIO0, SSIO1, UART0, UART1, I2C bus master/slave interface,
Timer 0, Timer 1, Timer 2, Timer 3, PWM0, PWM1, PWM2,
A/D converter, Voice sound reproduction, Speaker pin short detection, TBC128Hz, TBC32Hz,
TBC16Hz, TBC2Hz)
External source: 8(P80, P81, P82, P83, P84, P85, P86, P87)
•Time base counter
− Low-speed time base counter 1 channel
− High-speed time base counter 1 channel
•Watchdog timer
− Generates a non-maskable interrupt upon the first overflow and a system reset occurs upon the second
− Free running
− Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s at 32.768kHz)
•Timers
− 8 bits 4ch (16-bit configuration available)
•PWM
− Resolution 16 bits × 3ch
•Voice output function
− Voice synthesis method: HQ-ADPCM / 4-bit ADPCM2 / non-linear 8-bit PCM / straight 8-bit PCM /
straight 16-bit PCM
− Sampling frequency: 6.4kHz, 8kHz, 10.7kHz, 12.8kHz, 16kHz, 21.3 kHz, 25.6 kHz, 32 kHz
HQ-ADPCM is audio compression technology featuring high-quality
sound. It was developed by “Ky’s”.
“Ky’s” is a registered trademark of Kyushu Institute of Technology,
one of the national universities in Japan.
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•Successive approximation type A/D converter
− 10-bit A/D converter
− Input: 8ch
− Conversion time: 24.4 μs per channel at 4.096MHz VDD≥2.2V
− Conversion time: 12.2 μs per channel at 8.192MHz VDD≥2.5V
− Continuous conversion / Single conversion selectable
•Synchronous serial port (SSIO)
− 2ch
− Master/slave selectable
− LSB first/MSB first selectable
− 8-bit length/16-bit length selectable
•UART
− Half-duplex × 2ch (A full-duplex is also possible by using 2 channels)
− TXD/RXD
− Bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits
− Positive logic/negative logic selectable
− Built-in baud rate generator
•I2C bus interface
− Master function: standard mode (100 kbps) and Fast mode (400 kbps)
− Slave function: standard mode (100 kbps) and Fast mode (400 kbps)
•General-purpose ports
− Output-only port 6ch (Including secondary functions)
− Input/output port (Including secondary functions)
Input/output ports
(Including secondary functions)
Product
ML610Q327
ML610Q338
ML610Q339
26ch
30ch
42ch
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•Speaker amplifier(D-class) output power
− 1.0W(at 5.0V)/0.45W(at 3.0V)
− Disconnection detection circuit
− Speaker pin short detection circuit
•Reset
− Reset through the RESET_N pin
− Power-on reset generation when powered on
− Reset by the watchdog timer (WDT) overflow
− PLL oscillation stop detection reset
− Low level detection (LLD) reset
•Clock
− Low-speed clock
Built-in RC oscillation (32.768 kHz)
− High-speed clock
Built-in PLL oscillation (Approx. 1.024MHz / 2.048MHz / 4.096MHz / 8.192MHz)
•Power management
− STOP mode: Stop of oscillation (Operations of CPU and peripheral circuits are stopped.)
− HALT mode: Instruction execution by CPU is suspended (peripheral circuits are in operating states).
− Clock gear: The frequency of high-speed system clock can be changed by software (1/2, 1/4, 1/8, or 1/16 of the
oscillation clock)
− Block control function: Operation of an intact functional block circuit is powerd down. (register reset and clock stop)
•Shipment
Product
Shipment
ML610Q327
ML610Q338
ML610Q339
48pin TQFP (P-TQFP48-0707-0.50-ZK6)
52pin TQFP (P-TQFP52-1010-0.65-ZK6)
64pin TQFP (P-TQFP64-1010-0.50-ZK6)
•Guaranteed operating range
− Operating temperature: −40C to 85C
− Operating voltage: VDD = 2.0V to 5.5V, SPVDD = 2.0V to 5.5V
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BLOCK DIAGRAM
Block Diagram of ML610Q327
CPU (nX-U8/100)
EPSW1～3
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
Program Memory
（Flash）
EA
Timing
Controller
ALU
SP
192Kbyte,
Data Flash
2Kbyte
BUS
Controller
Instruction
Decoder
Instruction
Register
On-Chip
ICE
VDD
VSS
INT
2
Data-bus
SCK0*
SSIO
SIN0*
RESET_N
SOUT0*
RESET &
TEST1_N
TEST
SCK1*
SIN1*
SOUT1*
RAM
4KByte
TEST0
INT
2
LSCLK*
OUTCLK*
OSC
LLD
Interrupt
Controller
I2C
SDA*
SCL*
Master/Slave
INT
4
INT
2
RXD0*
TXD0*
RXD1*
TXD1*
TBC
UART
PWM
INT
4
VDDL
POWER
INT
3
8bit Timer
PWM0*
PWM1*
PWM2*
INT
2
INT
1
VOICECNT
10bit-ADC
WDT
INT
8
P20 to P25
P40 to P47
P80 to P87
P90 to P92
PA0 to PA3
PB0 to PB2
INT
1
GPIO
VREF
AIN0 to AIN7*1
SPVDD
SPVSS
D-class
Speaker
Amplifier
SPP
SPM
*
:
:
Secondary or tertiary function
Select I/O port or A/D converter input terminal
*1
Block Diagram of ML610Q327
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Block Diagram of ML610Q338
CPU (nX-U8/100)
EPSW1～3
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
Program Memory
（Flash）
EA
Timing
Controller
ALU
SP
256Kbyte,
Data Flash
2Kbyte
BUS
Controller
Instruction
Decoder
Instruction
Register
On-Chip
ICE
VDD
VSS
INT
2
Data-bus
SCK0*
SSIO
SIN0*
RESET_N
SOUT0*
RESET &
TEST1_N
TEST
SCK1*
SIN1*
SOUT1*
RAM
4KByte
TEST0
INT
2
LSCLK*
OUTCLK*
OSC
LLD
Interrupt
Controller
I2C
SDA*
SCL*
Master/Slave
INT
4
INT
2
RXD0*
TXD0*
RXD1*
TXD1*
TBC
UART
PWM
INT
4
VDDL
POWER
INT
3
8bit Timer
PWM0*
PWM1*
PWM2*
INT
1
INT
2
VOICECNT
10bit-ADC
WDT
INT
8
P20 to P25
P40 to P47
P80 to P87
P90 to P93
GPIO
INT
1
PA0 to PA4
PB0 to PB3
PC0
VREF
AIN0 to AIN7*1
SPVDD
SPVSS
D-class
Speaker
Amplifier
SPP
SPM
*
:
:
Secondary or tertiary function
Select I/O port or A/D converter input terminal
*1
Block Diagram of ML610Q338
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Block Diagram of ML610Q339
CPU (nX-U8/100)
EPSW1～3
ELR1～3
LR
ECSR1～3
DSR/CSR
PC
GREG
0～15
PSW
Program Memory
（Flash）
EA
Timing
Controller
ALU
SP
256Kbyte,
Data Flash
2Kbyte
BUS
Controller
Instruction
Decoder
Instruction
Register
On-Chip
ICE
VDD
VSS
INT
2
Data-bus
SCK0*
SSIO
SIN0*
RESET_N
SOUT0*
RESET &
TEST1_N
TEST
SCK1*
SIN1*
SOUT1*
RAM
4KByte
TEST0
INT
2
LSCLK*
OUTCLK*
OSC
LLD
Interrupt
Controller
I2C
SDA*
SCL*
Master/Slave
INT
4
INT
2
RXD0*
TXD0*
UART
TBC
RXD1*
TXD1*
INT
4
VDDL
POWER
INT
3
8bit Timer
PWM0*
PWM1*
PWM2*
PWM
INT
1
INT
2
VOICECNT
10bit-ADC
WDT
INT
8
P20 to P25
P40 to P47
P80 to P87
GPIO
P90 to P96
INT
1
PA0 to PA7
PB0 to PB6
PC0 to PC3
VREF
AIN0 to AIN7*1
SPVDD
SPVSS
D-class
Speaker
Amplifier
SPP
SPM
*
:
:
Secondary or tertiary function
Select I/O port or A/D converter input terminal
*1
Block Diagram of ML610Q339
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PIN CONFIGURATION
Pin Layout of ML610Q327 48pin TQFP Package
VREF
37
SPM
SPM
24
23
22
21
20
19
18
17
16
15
14
13
P40/AIN0/SIN1/SIN0
P41/AIN1/SCK1/SCK0
P42/AIN2/SOUT1/SOUT0
P43/AIN3
38
39
40
41
42
43
44
45
SPP
SPP
RESET_N
P90
P44/AIN4
P45/AIN5
P46/AIN6
P47/AIN7
(TOP VIEW)
TQFP48
PA0/SIN1
PA1/SCK1
PA2/SOUT1
PA3/PWM0
P85/EXI5/SCK1
P86/EXI6/RXD0/SOUT1
P87/EXI7/TXD0/TXD1
46
47
48
P83/EXI3/TXD1/TXD0
P82/EXI2/RXD1/SOUT0
Pin Layout of ML610Q327 48pin TQFP Package
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Pin Layout of ML610Q338 52pin TQFP Package
VREF
40
SPM
SPM
26
25
24
23
22
21
20
19
18
17
16
15
14
P40/AIN0/SIN1/SIN0
P41/AIN1/SCK1/SCK0
P42/AIN2/SOUT1/SOUT0
P43/AIN3
41
42
43
44
45
46
47
48
49
50
51
52
SPP
SPP
RESET_N
P90
P44/AIN4
P45/AIN5
(TOP VIEW)
TQFP52
PA0/SIN1
P46/AIN6
P47/AIN7
PA1/SCK1
PA2/SOUT1
PA3/PWM0
P83/EXI3/TXD1/TXD0
P82/EXI2/RXD1/SOUT0
PA4
P85/EXI5/SCK1
P86/EXI6/RXD0/SOUT1
P87/EXI7/TXD0/TXD1
PC0
Pin Layout of ML610Q338 52pin TQFP Package
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Pin Layout of ML610Q339 64pin TQFP Package
SPM
PC3
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SPM
SPP
PC2
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VREF
P40/AIN0/SIN1/SIN0
P41/AIN1/SCK1/SCK0
P42/AIN2/SOUT1/SOUT0
P43/AIN3
SPP
RESET_N
P90
PA0/SIN1
PA1/SCK1
PA2/SOUT1
(TOP VIEW)
TQFP64
P44/AIN4
P45/AIN5
P46/AIN6
P47/AIN7
P85/EXI5/SCK1
P86/EXI6/RXD0/SOUT1
P87/EXI7/TXD0/TXD1
PC0
PA3/PWM0
P83/EXI3/TXD1/TXD0
P82/EXI2/RXD1/SOUT0
PA4
PA5
PA6
PA7
PC1
Pin Layout of ML610Q339 64pin TQFP Package
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LIST OF PINS
In the I/O column, “—” denotes a power pin, “I” an input pin, “O” an output pin, and “I/O” an input/output pin.
48
52
64
Primary function
Secondary function
Tertiary function
Quaternary function
Pin Pin Pin
No. No. No. Pin name I/O
Pin
name
Desc-
ription
Pin
name
Desc-
ription
Pin
name
Desc-
ription
Description
I/O
⎯
⎯
⎯
I/O
⎯
⎯
⎯
I/O
⎯
⎯
⎯
Positive output pin of
the built-in speaker
amplifier
Negative output pin of
the built-in speaker
Negative power
supply pin for built-in
speaker amplifier
Positive power supply
pin for built-in
speaker amplifier
Negative power
supply pin
Power supply for
internal logic
21, 23, 29,
22
SPP
SPM
O
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
24
30
23, 25, 31,
24 26 32
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
25, 27, 33,
26 28 34
SPVss
⎯
27, 29, 35,
28
SPVDD
VSS
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
30
36
6,
31
7,
33
8,
39
32
33
34
35
40
41
VDDL
VDD
(internally generated)
Positive power supply
pin
Reference power
supply pin for
37
40
51
VREF
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
successive-approxim
ation type ADC
Reset input pin
Input/output pin for
testing
20
12
11
22
13
12
28 RESET_N
I
I/O
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
16
15
TEST0
TEST1_N
Input pin for testing
⎯
Low-spe
ed clock
output
high-spe
ed clock
output
Output port / LED
port
3
4
4
5
5
6
P20/LED0
P21/LED1
O
O
LSCLK
O
⎯
⎯
⎯
⎯
⎯
⎯
Output port / LED
port
OUTCLK
O
⎯
⎯
⎯
⎯
⎯
⎯
Output port / LED
port
Output port / LED
port
Output port / LED
port
Output port / LED
port
5
7
8
9
6
8
7
9
P22/LED2
P23/LED3
O
O
O
O
⎯
⎯
O
O
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PWM0
output
PWM1
output
PWM2
output
PWM0
PWM1
PWM2
9
10 P24/LED4
11 P25/LED5
10
Input port/Output port
/Successive-approxi
mation type ADC
input0
Input port/Output port
/Successive-approxi
mation type ADC
input1
Input port/Output port
/Successive-approxi
mation type ADC
input2
Input port/Output port
/Successive-approxi
mation type ADC
input3
Input port/Output port
/Successive-approxi
mation type ADC
input4
Input port/Output port
/Successive-approxi
mation type ADC
input5
Input port/Output port
/Successive-approxi
mation type ADC
input6
SSIO1
data
input
SSIO0
data
input
38
39
40
41
42
43
44
41
42
43
44
45
46
47
52
53
54
55
56
57
58
P40/AIN0 I/O
P41/AIN1 I/O
P42/AIN2 I/O
P43/AIN3 I/O
P44/AIN4 I/O
P45/AIN5 I/O
P46/AIN6 I/O
SIN1
SCK1
SOUT1
⎯
I
SIN0
SCK0
SOUT0
⎯
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SSIO1
clock
input/out
put
SSIO0
clock
input/out
put
I/O
O
I/O
O
SSIO1
data
output
SSIO0
data
output
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
11/40
FEDL610Q339-01
ML610Q327/38/39
48
Pin Pin Pin
No. No. No. Pin name I/O
52
64
Primary function
Secondary function
Tertiary function
Quaternary function
Pin
Desc-
Pin
Desc-
Pin
Desc-
ription
Description
I/O
I/O
I/O
name
ription
name
ription
name
Input port/Output port
/Successive-approxi
mation type ADC
input7
45
1
48
2
59
3
P47/AIN7 I/O
P80/EXI0 I/O
P81/EXI1 I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
I2C data
input/
output
SSIO0
data
input
SSIO0
clock
input/out
put
Input port/Output port
/ External interrupt
SDA
SCL
I/O
I/O
SIN0
I
⎯
⎯
I2C clock
input/out
put
Input port/Output port
/ External interrupt
2
3
4
SCK0
I/O
UART1
data
input
UART1
data
output
SSIO0
data
output
UART0
data
output
SSIO1
data
Input port/Output port
/ External interrupt
13
14
29
15
16
31
21
22
37
P82/EXI2 I/O
P83/EXI3 I/O
P84/EXI4 I/O
RXD1
TXD1
⎯
I
SOUT0
TXD0
SIN1
O
O
I
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input port/Output port
/ External interrupt
O
⎯
Input port/Output port
/ External interrupt
⎯
⎯
input
SSIO1
clock
input/out
put
Input port/Output port
/ External interrupt
46
49
60
P85/EXI5 I/O
SCK1
I/O
⎯
⎯
⎯
⎯
⎯
UART0
data
input
UART0
data
SSIO1
data
output
UART1
data
Input port/Output port
/ External interrupt
47
48
50
51
61
62
P86/EXI6 I/O
P87/EXI7 I/O
RXD0
TXD0
I
SOUT1
TXD1
O
O
⎯
⎯
⎯
⎯
⎯
⎯
Input port/Output port
/ External interrupt
O
output
output
⎯
⎯
⎯
⎯
19
10
30
⎯
⎯
⎯
⎯
21
11
32
1
⎯
⎯
⎯
27
12
38
1
2
13
14
P90
P91
P92
P93
P94
P95
P96
I/O Input port/Output port
I/O Input port/Output port
I/O Input port/Output port
I/O Input port/Output port
I/O Input port/Output port
I/O Input port/Output port
I/O Input port/Output port
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
SSIO1
data
input
SSIO1
clock
input/out
put
⎯
⎯
18
20
26
PA0
I/O Input port/Output port
SIN1
I
⎯
⎯
⎯
⎯
⎯
⎯
17
19
25
PA1
I/O Input port/Output port
SCK1
I/O
⎯
⎯
⎯
⎯
SSIO1
data
output
PWM0
output
⎯
⎯
⎯
16
15
18
17
24
23
PA2
PA3
I/O Input port/Output port
I/O Input port/Output port
SOUT1
PWM0
O
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
14
⎯
⎯
⎯
20
19
18
17
PA4
PA5
PA6
PA7
I/O Input port/Output port
I/O Input port/Output port
I/O Input port/Output port
I/O Input port/Output port
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
I2C data
input/
output
I2C clock
input/out
put
⎯
34
36
42
PB0
I/O Input port/Output port
I/O Input port/Output port
SDA
I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
35
36
37
38
43
44
PB1
PB2
SCL
I/O
O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
PWM1
output
⎯
I/O Input port/Output port
I/O Input port/Output port
PWM1
39
⎯
⎯
⎯
52
⎯
⎯
⎯
45
46
47
48
63
64
50
49
PB3
PB4
PB5
PB6
PC0
PC1
PC2
PC3
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Input port/Output port
Input port/Output port
Input port/Output port
Input port/Output port
Input port/Output port
I/O
I/O
I/O
I/O
I/O
⎯
⎯
⎯
⎯
⎯
⎯
⎯
I/O Input port/Output port
I/O Input port/Output port
Note: The function which is not chosen is lost when either a secondary function or a tertiary function is chosen. However, when
using it as an input, read-out of an input data is possible at a port n data register (PnD).
12/40
FEDL610Q339-01
ML610Q327/38/39
PIN DESCRIPTION
In the I/O column, “—” denotes a power pin, “I” an input pin, “O” an output pin, and “I/O” an input/output pin.
Primary/
Pin name
I/O
Description
Secondary/
Tertiary
Logic
Power supply
VSS
Negative power supply pin
Positive power supply pin
—
—
—
—
—
—
—
—
—
VDD
VDDL
Positive power supply pin for internal logic (internally generated)
Connect the capacitor CL(1uF)( Refer to Measuring circuit 1) to
VSS
SPVSS
SPVDD
VREF
Negative power supply pin for built-in speaker amplifier
—
—
—
—
—
—
—
—
—
Positive power supply pin for built-in speaker amplifier
Reference power supply pin for successive-approximation type ADC
Test
TEST0
TEST1_N
System
Input/output pin for testing. Has a pull-down resistor built in.
Input pin for testing. Has a pull-up resistor built in.
I/O
I
—
—
Positive
Negative
Reset input pin. When this pin is set to a “L” level, the device is
placed in system reset mode and the internal circuit is initialized.
If after that this pin is set to a “H” level, program execution starts.
This pin has a pull-up resistor built in.
RESET_N
I
—
Negative
Low-speed clock output. This function is allocated to the secondary
function of the P20 pin.
LSCLK
O
O
Secondary
Secondary
—
—
High-speed clock output. This function is allocated to the secondary
function of the P21 pin.
OUTCLK
General-purpose Output port
General-purpose output ports.
P20 to P25
Provided with a secondary function. Cannot be used as ports if
their secondary function is used.
O
Primary
Positive
General-purpose Input/output port
General-purpose input/output ports.
Provided with a secondary function or a tertiary function. Cannot
be used as ports if their secondary function or tertiary function is
used.
P40 to P47
I/O
Primary
Primary
Positive
Positive
General-purpose input/output ports.
Provided with a secondary function or a tertiary function. Cannot
be used as ports if their secondary function or tertiary function is
used.
P80 to P87
I/O
P90 to P96*1
PA0 to PA7*1
PB0 to PB6*1
PC0 to PC3*1
General-purpose input/output ports.
I/O
I/O
I/O
I/O
Primary
Primary
Primary
Primary
Positive
Positive
Positive
Positive
General-purpose input/output ports.
Provided with a secondary function. Cannot be used as ports if
their secondary function is used.
General-purpose input/output ports.
Provided with a secondary function. Cannot be used as ports if
their secondary function is used.
General-purpose input/output ports.
*1: ML610Q327/ML610Q338/ML610Q339 have a different pin configuration for each package. See “LIST OF PINS”
for more details.
13/40
FEDL610Q339-01
ML610Q327/38/39
Primary/
Secondary/
Tertiary
Pin name
I/O
Description
Logic
I2C bus interface
I2C data input/output pin. This pin is used as the secondary
function of the P80 pin and PB0 pin. This pin has an NMOS open
drain output. When using this pin as a function of the I2C,
externally connect a pull-up resistor.
I2C clock input/output pin. This pin is used as the secondary
function of the P81 pin and PB1 pin. This pin has an NMOS open
drain output. When using this pin as a function of the I2C,
externally connect a pull-up resistor.
SDA
SCL
I/O
I/O
Secondary
Secondary
Positive
Positive
Synchronous serial (SSIO)
Synchronous serial data input pin. Allocated to the tertiary
function of the P40 pin and P80 pin.
Synchronous serial clock input/output pin. Allocated to the
tertiary function of the P41 pin and P81 pin.
Synchronous serial data output pin. Allocated to the tertiary
function of the P42 pin and P82 pin.
SIN0
I
Tertiary
Tertiary
Tertiary
Positive
—
SCK0
SOUT0
I/O
O
Positive
Synchronous serial data input pin. Allocated to the tertiary
function of the P84 pin and the secondary function of the P40 pin
and PA0 pin.
Secondary/
Tertiary
SIN1
I
Positive
—
Synchronous serial clock input/output pin. Allocated to the
Secondary/
Tertiary
SCK1
SOUT1
I/O tertiary function of the P85 pin and the secondary function of the
P41 pin and PA1 pin.
Synchronous serial data output pin. Allocated to the tertiary
function of the P86 pin and the secondary function of the P42 pin
and PA2 pin.
Secondary/
Tertiary
O
Positive
UART
TXD0
UART0 data output pin. Allocated to the secondary function of
the P87 pin and the tertiary function of the P83 pin.
UART0 data input pin. Allocated to the secondary function of the
P86 pin.
UART1 data output pin. Allocated to the secondary function of
the P83 pin and the tertiary function of the P87 pin.
UART1 data input pin. Allocated to the secondary function of the
P82 pin.
O
I
Secondary
Secondary
Secondary
Secondary
Positive
Positive
Positive
Positive
RXD0
TXD1
O
I
RXD1
PWM
PWM0 output pin. Allocated to the secondary function of the P23
pin and PA3 pin.
PWM1 output pin. Allocated to the secondary function of the P24
pin and PB2 pin.
PWM2 output pin. Allocated to the secondary function of the P25
pin.
PWM0
O
O
O
Secondary
Secondary
Secondary
Positive
Positive
Positive
PWM1
PWM2
External interrupt
External maskable interrupt input pins. It is possible, for each bit,
to specify whether the interrupt is enabled and select the
interrupt edge by software. Allocated to the primary function of
the P80 to P87 pins.
Positive/
Negative
EXI0 to 7
I
Primary
Primary
LED drive
Pins for LED driving. Allocated to the primary function of the P20
to P25 pins.
Positive/
Negative
LED0 to 5
O
Voice output function
—
—
—
—
SPP
SPM
O
O
Positive output pin of the internal speaker amplifier.
Negative output pin of the internal speaker amplifier.
Successive-approximation type A/D converter
Analog inputs to Ch0 to Ch7 of the successive-approximation
—
AIN0 to 7
I
type A/D converter. Allocated to the primary function of the P40
to P47 pins.
Primary
14/40
FEDL610Q339-01
ML610Q327/38/39
TERMINATION OF UNUSED PINS
How to Terminate Unused Pins
Pin
RESET_N
TEST0
Recommended pin termination
Open
Open
*2
TEST1_N
Open or connect to VDD
VREF
Connect to VDD
Open
P40 to P47 (AIN0 to AIN7)
SPVDD
Connect to VDD
Connect to VSS
Open
SPVSS
SPP
SPM
Open
P20 to P25
P80 to P87
P90 to P96*1
PA0 to PA7*1
PB0 to PB6*1
PC0 to PC3*1
Open
Open
Open
Open
Open
Open
*1: ML610Q327/ML610Q338/ML610Q339 have a different pin configuration for each package. See “LIST OF PINS” for
more details.
*2: TEST1_N pin has the built-in pull-up resistor (Typ.10k). It is recommended to connect to VDD or be pulled up by around
1k resistor in a severe enviroment such as noise.
Notes:
• The unused input ports or unused input/output ports should not be configured as high-impedance inputs and left open. If the
corresponding pins are configured as high-impedance inputs and left open, because the input buffer of both Nch and Pch MOS
transistor turn on, the supply current may become excessively large. Therefore, it is recommended to configure those pins as
either inputs with a pull-down resistor/pull-up resistor or outputs.
• When the power is turned on, the state of the general-purpose port is undefined. Therefore, there is a possibility of outputting
high-level or low-level.If the undefined state at the power-on is a problem, take measures with the peripheral components on the
user board.
15/40
FEDL610Q339-01
ML610Q327/38/39
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
(VSS= SPVSS=0V)
Unit
Parameter
Power supply voltage 1
Power supply voltage 2
Power supply voltage 3
Reference supply voltage
Input voltage
Symbol
VDD
Condition
Ta=25C
Ta=25C
Ta=25C
Ta=25C
Ta=25C
Ta=25C
Rating
−0.3 to +6.5
−0.3 to +6.5
V
V
V
V
V
V
SPVDD
VDDL
VREF
VIN
−0.3 to +2.0
−0.3 to VDD+0.3
−0.3 to VDD+0.3
−0.3 to VDD+0.3
Output voltage
VOUT
Output current 1
(P40 to P47,
P80 to P87,
P90 to P96*1,
PA0 to PA7*1,
PB0 to PB6*1,
PC0 to PC3*1)
IOUT1
Ta=25C
−12 to +11
−12 to +20
mA
mA
Ta=25C
When setting Nch open drain
mode.
Output current 2
(P20 to P25)
IOUT2
Power dissipation
PD
Ta=25C
1.0
W
Storage temperature
TSTG
―
−55 to +150
C
*1: ML610Q327/ML610Q338/ML610Q339 have a different pin configuration for each package. See “LIST OF PINS” for more
details.
Recommended Operating Conditions
(VSS= SPVSS=0V)
Parameter
Symbol
TOP
Condition
Range
Unit
Operating temperature
―
―
―
−40 to +85
2.0 to 5.5
2.0 to 5.5
C
VDD
Operating voltage
V
SPVDD
VREF
Reference supply voltage
Operating frequency (CPU)
VDD≥VREF
2.2 to VDD
27k to 4.2M
4.2M to 8.4M
V
VDD = 2.0 to 5.5V
VDD = 2.2 to 5.5V
fOP
CV
CL
Hz
Capacitor externally connected to
VDD pin
Capacitor externally connected to
VDDL pin
―
―
More than 1.030%
1.030%
F
F
16/40
FEDL610Q339-01
ML610Q327/38/39
Operating Conditions of Flash Memory
(VSS= SPVSS=0V)
Unit
Parameter
Symbol
TOP
Condition
At write/erase
(Data flash area)
At write/erase
Range
-40 to +70
Operating temperature
C
0 to +40
(Program code area)
At write/erase
Data flash area(512Byte x 4)
Program code area
Operating voltage
VDD
CEPD
CEPP
2.2 to 5.5
10,000
100
V
Maximum rewrite count*1
cycles
All program and data
―
―
Chip erase
―
area
Erase unit
Program area
Block erase
16
KB
Data area
2
―
―
―
Sector erase
Chip/Block/Sector erase
―
512
50
1word(2Bytes)
B
ms
―
Erase time(Maximum)
Program unit
Program area
1word(2Bytes)
40
60
15
Program time(Maximum)
Data retention period
―
μs
Data area
YDR
―
years
*1 : It means one erase and one program. Even when erasing is interrupted, it counts as one time.
DC Characteristics (Supply Current)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
Typ.
Max.
4.0
CPU: In STOP state.
0.7
0.7
Ta≤+50C
Ta≤+85C
―
Low-speed/high-speed
oscillation: stopped
CPU: In HALT state
(LTBC,WDT: Operating)
High-speed oscillation:
Stopped
Supply current 1
IDD1
9.0
5.0
10
―
―
2.0
2.0
15
Ta≤+50C
A
Supply current 2
Supply current 3
IDD2
IDD3
Ta≤+85C
―
―
CPU: Running at 32.768 kHz*1
High-speed oscillation: Stopped
30
VDD=SPVDD
=
=
=
―
―
―
1.0
1.0
2.0
2.5
2.5
3.5
3.0V
VDD=SPVDD
5.0V
CPU: Running at 4.096MHz
RC oscillating mode
Supply current 4
IDD4
VDD=SPVDD
3.0V
1
CPU: Running at 8.192MHz
RC oscillating mode
VDD=SPVDD
=
―
2.0
3.5
5.0V
CPU: Running at 4.096MHz
RC oscillating mode
During voice playback of
1kHz,2.98db,SIN-wave
(no output load)
mA
VDD=SPVDD
=
=
=
=
―
―
―
―
2.0
4.0
3.0
5.0
5.0
8.0
6.0
9.0
3.0V
VDD=SPVDD
5.0V
Supply current 5
IDD5
CPU: Running at 8.192MHz
RC oscillating mode
During voice playback of
1kHz,2.98db,SIN-wave
(no output load)
VDD=SPVDD
3.0V
VDD=SPVDD
5.0V
*1: Case when the CPU operating rate is 100% (no HALT state).
17/40
FEDL610Q339-01
ML610Q327/38/39
DC Characteristics (VOHL, IOHL, IIHL)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Measuring
circuit
Parameter
Symbol
VOH1
Condition
Unit
Min.
Typ.
Max.
Output voltage 1
(P20 to P25)
(P40 to P47)
(P80 to P87)
(P90 to P96*1)
(PA0 to PA7*1)
(PB0 to PB6*1)
IOH1=−0.5mA
(When one port is selected as output mode)
VDD
−0.5
―
―
―
IOL1=+0.5mA
(When one port is selected as output mode)
VOL1
VOL2
―
0.5
(PC0 to PC3*1)
V
2
IOL2=+5mA
―
―
―
―
0.5
0.5
(When one port is
selected as Nch open
drain mode)
V
DD≥2.2V
IOL2=+8mA
DD≥2.3V
Output voltage 2
(P20 to P25)
V
Output voltage 3
(P80 to P81)
(PB0 to PB1)
IOL3=+3mA
VOL3
IOOH
( I2C bus input/output mode,
―
―
―
―
0.4
1.0
When one port is selected as output)
Output leakage
(P20 to P25)
(P40 to P47)
(P80 to P87)
(P90 to P96*1)
(PA0 to PA7*1)
(PB0 to PB6*1)
VOH=VDD (in high-impedance state)
VOL=VSS (in high-impedance state)
A
3
IOOL
−1.0
―
―
(PC0 to PC3*1)
Input current 1
(RESET_N)
IIH1
IIL1
IIH2
VIH1=VDD
VIL1=VSS
0
−1500
2
―
−300
30
1.0
−20
250
(TEST1_N)
Input current 2
(P40 to P47)
(P80 to P87)
(P90 to P96*1)
(PA0 to PA7*1)
(PB0 to PB6*1)
VIH2=VDD (when pulled-down)
IIL2
VIL2=VSS (when pulled-up)
−250
−30
−2
A
4
IIH2Z
VIH2=VDD (in high-impedance state)
―
―
1.0
IIL2Z
VIL2=VSS (in high-impedance state)
−1.0
―
―
(PC0 to PC3*1)
Input current 3
(TEST0)
IIH3
IIL3
VIH3=VDD
VIL3=VSS
20
300
1500
−1.0
―
―
*1: ML610Q327/ML610Q338/ML610Q339 have a different pin configuration for each package. See “LIST OF PINS” for more
details.
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DC Characteristics (VIHL)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Measuring
circuit
Parameter
Symbol
VIH1
Condition
Unit
Min.
Typ.
Max.
VDD
Input voltage 1
(RESET_N)
(TEST0)
―
0.7VDD
―
―
(TEST1_N)
(P40 to P47)
(P80 to P87)
(P90 to P96*1)
(PA0 to PA7*1)
(PB0 to PB6*1)
VIL1
―
0
0.3VDD
(PC0 to PC3*1)
V
5
Hysteresis width
(RESET_N)
(TEST0)
(TEST1_N)
(P40 to P47)
(P80 to P87)
(P90 to P96*1)
(PA0 to PA7*1)
(PB0 to PB6*1)
⊿VT
―
0.05VDD
―
0.4VDD
(PC0 to PC3*1)
Input pin
capacitance
(P40 to P47)
(P80 to P87)
(P90 to P96*1)
(PA0 to PA7*1)
(PB0 to PB6*1)
f=10kHz
Vrms=50mV
Ta=25C
CIN
―
―
10
pF
―
(PC0 to PC3*1)
*1: ML610Q327/ML610Q338/ML610Q339 have a different pin configuration for each package. See “LIST OF PINS” for more
details.
Hysteresis Width
⊿VT
VDD
Input signal
VSS
VDDL
VSS
Internal signal
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Measuring circuit
・Measuring circuit 1
VDD VREF SPVDD
VSS
SPVSS
VDDL
CAV
CL
CSV
CV
：1.0μF
：1.0μF
：1.0μF
：1.0μF
A
CSV
CAV
CL
CV
・Measuring circuit 2
(* 2)
VIH
V
(* 1)
VIL
VDD VDDL
VREF SPVDD VSS
SPVSS
(* 1) Input logic circuit to determine the specified measuring conditions.
(* 2) Measured at the specified output pins.
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・Measuring circuit 3
(* 2)
VIH
A
(* 1)
VIL
VREF SPV
VDD VDDL
DD VSS
SPVSS
(* 1) Input logic circuit to determine the specified measuring conditions.
(* 2) Measured at the specified output pins.
・Measuring circuit 4
(* 3)
A
VDD VDDL
VREF SPVDD
SPVSS
VSS
(* 3) Measured at the specified output pins.
・Measuring circuit 5
VIH
(* 1)
VIL
VDD VDDL
VREF SPV
SPVSS
DD VSS
(* 1) Input logic circuit to determine the specified measuring conditions.
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AC Characteristics (Oscillation Circuit)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Typ.
Measuring
Circuit
Parameter
Symbol
fLCR
Condition
Unit
Min.
Typ
-1.5%
Typ
-3.0%
Typ
-1.5%
Typ
Max.
Typ
+1.5%
Typ
+3.0%
Typ
+1.5%
Typ
Ta = −10 to +50°C
Ta = −40 to +85°C
Ta = −10 to +50°C
Ta = −40 to +85°C
Built-in RC oscillation frequency
32.768
kHz
1
4.096
or
8.192
PLL oscillation frequency
fHPLL
MHz
-3.0%
+3.0%
Electrical Characteristics of Speaker amp
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Symbol
RLSP
Condition
Unit
Parameter
Min.
6.4
Typ.
Max.
SPM, SPP output load
resistance
―
8
—
SPVDD=3.0V, f=1kHz
RSPO=8, THD10%
PSPO1
—
—
0.45
1.0
—
—
Speaker amp output power
W
SPVDD=5.0V, f=1kHz
RSPO=8, THD10%
PSPO2
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AC Characteristics (Power on, Reset Sequence)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Typ.
Measuring
circuit
Parameter
Symbol
Condition
Unit
Min.
0
Max.
Time until it starts SPVDD after starting
VDD
tVDD
―
―
―
ns
Reset *1 pulse width
PRST
PNRST
SPOR
―
―
―
100
―
0.1
―
―
―
―
0.4
―
1
s
Reset *1 noise elimination pulse width
Power-on rising slope
V/ms
*1 : reset from RESET_N pin
VIL1
VIL1
PRST
RESET_N
RESET_N Pin Reset
SPOR
VDD
Power-on rising slope
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Electrical Characteristics of Low Level Detection Reset
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Measuring
circuit
Parameter
Symbol
Condition
Unit
Max.
Typ.
+5%
Typ.
+5%
Typ.
+5%
Typ.
+5%
Typ.
+7%
Min.
Typ.
-5%
Typ.
-5%
Typ.
-5%
Typ.
-5%
Typ.
-7%
Typ.
LLD2-0=7H
1.9
2.1
2.3
2.5
LLD2-0=2H or
LLD2-0=6H
LLD2-0=1H or
LLD2-0=5H
LLD2-0=0H or
LLD2-0=4H
Detection voltage
Hysteresis width
VTH
V
1
LLD2-0=3H
2.7
0.1
10
ΔVTH
―
―
0.05
0.15
V
Output delay when power
rising
TPLH
―
200
s
Output delay when power
falling
Low level detection reset
operating voltage
TPHL
VMIN
―
―
―
10
200
s
1.0
―
―
V
SPOR
ΔVTH
VTH
VDD
VMIN
0V
“H”
“H”
Low level
Detection
Reset
TPLH
TPLH
TPHL
TPHL
“L”
(*)“L”: reset
Note:
When the detection voltage of Low Level Detection Reset (VTH) is set to 1.9V(LLD2-0=7H), Low Level Detection Reset is not
asserted in the voltage lange from lower minimum recommended operating volatge (VDD=2.0V) to upper detection voltage
(VTH=1.9V). During power shutdown sequence, if this voltage lange is kept, depending on the LSI operationg condition, the
internal regulated power supply circuit (VRL) can not keep the operationg votage, and the program may NOT operate properly.
Therefore, please take measures, such as, setting Low Level Detection Reset (VTH) to except 1.9V (LLD2-0 =7H), and reset
generation from RESET_N pin for fail-safe
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Power-on/Shutdown Sequence
・When the power-on rising slope is 0.1V/ms(Min.) or more
When Power-on
When Shutdown
VDD
SPOR
SPVDD
・When the power-on rising slope is less than 0.1V/ms(Min.)
When Shutdown
When Power-on
90%
VDD
SPOR
90%
SPVDD
10ms(min.)
10ms(min.)
VIL
RESET_N
Recommended power-on/shutdown sequence
There are no ristrictions of order, slope time, time lag in turnning on/off VDD and SPVDD
.
Notes:
• When the power is turned on, the state of the general-purpose port is undefined. Therefore, there is a possibility of outputting
high-level or low-level.If the undefined state at the power-on is a problem, take measures with the peripheral components on the
user board.
• When power-on reset is generated because of instantaneous power failure etc., or, when the glitch which is narrower than
output delay when power falling (TPHL) is generated on VDD power, or, When VDD power is decreased below low level detection
reset operating voltage (VMIN) before output delay when power falling (TPHL) is passed, the LSI may NOT get reset, and the
program may NOT operate properly. Therefore, please take measures, such as, power voltage drop prevention by bypass
capacitors, and reset generation from RESET_N pin for fail-safe.
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AC Characteristics (Oscillation stable time after STOP release)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Typ.
Parameter
Symbol
TPUP1
Condition
Unit
ms
Min.
Max.
2
Oscillation stable time
after STOP release
―
―
―
High-speed oscillation
waveform
High-speed oscillation waveform
High-speed oscillation waveform
TPUP1
OSCLK, HSCLK
OSCLK, HSCLK waveform
OSCLK, HSCLK waveform
HSCLK waveform
SYSCLK
HSCLK waveform
Interruput request
Program operation mode
STOP mode
Program operation mode
AC Characteristics (External Interrupt)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Parameter
Symbol
TNUL
Condition
Unit
Min.
Typ.
Max.
Interrupt: Enabled (MIE=1)
CPU: NOP operation
External interrupt disable
period
2.5sysclk
―
3.5sysclk
s
P80 to P87
(Rising-edge interrupt)
tNUL
tNUL
tNUL
P80 to P87
(Falling-edge interrupt)
P80 to P87
(Both-edge interrupt)
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AC Characteristics (Synchronous Serial Port)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Parameter
SCK input cycle
Symbol
tSCYC
tSCYC
tSW
Condition
Unit
Min.
10
Typ.
Max.
When high-speed oscillation is not
active
―
―
s
(slave mode)
When high-speed oscillation is active
500
―
―
4
―
―
―
ns
VDD≥2.4V
SCK output cycle
(master mode)
MHz
VDD≥2.0V
When high-speed oscillation is not
active
―
2
4
―
―
s
ns
s
SCK input pulse width
(slave mode)
When high-speed oscillation is active
200
SCK*1
0.4
―
SCK*1
0.5
―
SCK*1
0.6
SCK output pulse width
(master mode)
tSW
tSD
tSD
―
―
―
SOUT output delay time
(slave mode)
SOUT output delay time
(master mode)
SIN input
―
―
―
―
180
80
ns
ns
setup time
(slave mode)
SIN input
tSS
―
50
―
―
―
―
ns
ns
tSH
―
50
hold time
*1: Clock period selected with SnCK3–0 of the serial port n mode register (SIOnMOD1) (n=0,1)
tSCYC
tSW
tSW
SCKn*
SOUTn*
SINn*
tSD
tSD
tSS
tSH
*: Indicates the secondary/tertiary function of the port. n=0, 1
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AC Characteristics (I2C Bus Interface: Standard Mode 100kbps)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Typ.
⎯
Parameter
Symbol
fSCL
Condition
Unit
kHz
s
Min.
0
Max.
100
SCL clock frequency
⎯
⎯
SCL hold time
tHD:STA
4.0
⎯
⎯
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
tLOW
tHIGH
⎯
⎯
4.7
4.0
⎯
⎯
⎯
⎯
s
s
tSU:STA
⎯
4.7
⎯
⎯
s
tHD:DAT
tSU:DAT
⎯
⎯
0
⎯
⎯
⎯
⎯
s
s
SDA setup time
SDA setup time
(stop condition)
Bus-free time
0.25
tSU:STO
tBUF
⎯
⎯
4.0
4.7
⎯
⎯
⎯
⎯
s
s
AC Characteristics (I2C Bus Interface: Fast Mode 400kbps)
(VDD= 2.0 to 5.5V, SPVDD=2.0 to 5.5V, VSS= SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Parameter
Symbol
Condition
Unit
Min.
0
Typ.
⎯
Max.
400
SCL clock frequency
fSCL
⎯
⎯
kHz
SCL hold time
tHD:STA
0.6
⎯
⎯
s
(start/restart condition)
SCL ”L” level time
SCL ”H” level time
SCL setup time
(restart condition)
SDA hold time
tLOW
tHIGH
⎯
⎯
1.3
0.6
⎯
⎯
⎯
⎯
s
s
tSU:STA
⎯
0.6
⎯
⎯
s
tHD:DAT
tSU:DAT
⎯
⎯
0
0.1
⎯
⎯
⎯
⎯
s
s
SDA setup time
SDA setup time
(stop condition)
Bus-free time
tSU:STO
tBUF
⎯
⎯
0.6
1.3
⎯
⎯
⎯
⎯
s
s
Start
condition
Restart
condition
Stop
condition
SDA
SCL
tBUF
tSU:STO
tHD:STA
tLOW
tHIGH
tSU:STA tHD:STA
tSU:DAT
tHD:DAT
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Electrical Characteristics of Successive Approximation Type A/D Converter
(VDD=SPVDD=2.2 to 5.5V, VREF=2.2 to 5.5V, VSS=SPVSS=0V, Ta=−40 to +85C, unless otherwise specified)
Rating
Parameter
Symbol
n
Condition
Unit
bit
Min.
―
Typ.
―
―
―
―
―
―
―
―
―
Max.
10
+4
Resolution
―
2.7V≤VREF≤5.5V
2.2V≤VREF<2.7V
2.7V≤VREF≤5.5V
2.2V≤VREF<2.7V
RI≤5kΩ
−4
−5
−3
−4
−4
−4
―
Integral non-linearity error
IDL
+5
+3
+4
+4
+4
5k
VDD
Differential non-linearity error
DNL
LSB
Zero-scale error
Full-scale error
Prefilter resistance
Reference supply voltage
VOFF
FSE
RI
RI≤5kΩ
―
―
Ω
VREF
2.2
V
Conversion time
tCONV
HSCLK=4M to 8.4MHz
―
102
―
/CH
: Period of high-speed clock (HSCLK)
VDD
Reference
supply voltage
VREF
VDDL
1μF
1μF
A
RI≤5k
0.1μF
AIN0
to
AIN7
−
1μF
+
Analog input
VSS
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Example of Application Circuit
Supply voltage
CSV
SPVDD
SPVss
EASE1000 V2
I/F
VDD
3.3VOUT
CV
VTref
RST_OUT/SCK
SDATA
TEST1_N
TEST0
Speaker
ML610Q327
ML610Q338
ML610Q339
Vss
SPP
SPM
CL
VDDL
RESET_N
P40/AIN0 to P47/AIN7
ANALOG
RXD0
TXD0
P86
P87
RXD1
TXD1
P82
P83
VREF
CAV
VSS
VSS
P20 to P25
CV
CL
CAV
CSV
: 1.0uF
: 1.0uF
: 1.0uF
: 1.0uF
LED
VDD and SPVDD are supplied from same power supply
Note:
Design the PCB layout having the shortest wiring distance between VDDL pin and VDDL pin's external capacitor (CL), and
between VDDL pin's external capacitor (CL) and VSS for noise reduction purpose.
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Supply voltage
IN
DC-DC
OUT
GND
CSV
SPVDD
SPVss
EASE1000 V2
I/F
VDD
CV
3.3VOUT
VTref
RST_OUT/SCK
SDATA
Vss
TEST1_N
TEST0
Speaker
ML610Q327
ML610Q338
ML610Q339
SPP
SPM
CL
VDDL
RESET_N
P40/AIN0 to P47/AIN7
ANALOG
RXD0
TXD0
P86
P87
RXD1
TXD1
P82
P83
VREF
CAV
VSS
VSS
P20-P25
CV
CL
CAV
CSV
: 1.0uF
: 1.0uF
: 1.0uF
: 1.0uF
LED
VDD is supplied through DC-DC converter from SPVDD
Note:
Design the PCB layout having the shortest wiring distance between VDDL pin and VDDL pin's external capacitor (CL), and
between VDDL pin's external capacitor (CL) and VSS for noise reduction purpose.
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PACKAGE DIMENSIONS (48pin TQFP)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin
number, package code and desired mounting conditions (reflow method, temperature and times).
The heat resistance (example) of this LSI is shown below. Heat resistance (θJa) changes with the size and the number of
layers of a substrate.
PCB
W/L/t=76.2 / 114.3 / 1.6（mm）
JEDEC 4layers
Calm（0m/sec）
53.5 [oC/W]
PCB Layer
Air cooling conditions
Heat resistance（θJa）
Power consumption of Chip PMax
0.300[W]
TjMax of this LSI is 110 oC. TjMax is expressed with the following formulas.
TjMax = TaMax + θJa × PMax
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Figure of soldering department terminal existence range (48pin TQFP)
Reference drawing
Unit
Attention of the layout of a mounting board
Please take into consideration enough that there are not ease of a mounting, the reliability of contact, leading about of a
wiring, and a solder bridge generate in the case of layout of the foot pattern of a mounting board.
The optimal layout of a foot pattern changes by the board quality of material, the solder paste category to be used,
thickness, the soldering methodology, etc. Therefore, since the span where the terminator of this package may exist is
shown as a "soldering part terminator extent drawing", please give as reference data of a foot pattern design.
33/40
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PACKAGE DIMENSIONS (52pin TQFP)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin
number, package code and desired mounting conditions (reflow method, temperature and times).
The heat resistance (example) of this LSI is shown below. Heat resistance (θJa) changes with the size and the number of
layers of a substrate.
PCB
W/L/t=76.2 / 114.3 / 1.6（mm）
JEDEC 4layers
Calm（0m/sec）
49.9 [oC/W]
PCB Layer
Air cooling conditions
Heat resistance（θJa）
Power consumption of Chip PMax
0.300[W]
TjMax of this LSI is 110 oC. TjMax is expressed with the following formulas.
TjMax = TaMax + θJa × PMax
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Figure of soldering department terminal existence range (52pin TQFP)
Reference drawing
Unit
Attention of the layout of a mounting board
Please take into consideration enough that there are not ease of a mounting, the reliability of contact, leading about of a
wiring, and a solder bridge generate in the case of layout of the foot pattern of a mounting board.
The optimal layout of a foot pattern changes by the board quality of material, the solder paste category to be used,
thickness, the soldering methodology, etc. Therefore, since the span where the terminator of this package may exist is
shown as a "soldering part terminator extent drawing", please give as reference data of a foot pattern design.
35/40
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PACKAGE DIMENSIONS (64pin TQFP)
Notes for Mounting the Surface Mount Type Package
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin
number, package code and desired mounting conditions (reflow method, temperature and times).
The heat resistance (example) of this LSI is shown below. Heat resistance (θJa) changes with the size and the number of
layers of a substrate.
PCB
W/L/t=76.2 / 114.3 / 1.6（mm）
JEDEC 4layers
Calm（0m/sec）
39.6 [oC/W]
PCB Layer
Air cooling conditions
Heat resistance（θJa）
Power consumption of Chip PMax
0.300[W]
TjMax of this LSI is 110 oC. TjMax is expressed with the following formulas.
TjMax = TaMax + θJa × PMax
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Figure of soldering department terminal existence range (64pin TQFP)
Reference drawing
Unit
Attention of the layout of a mounting board
Please take into consideration enough that there are not ease of a mounting, the reliability of contact, leading about of a
wiring, and a solder bridge generate in the case of layout of the foot pattern of a mounting board.
The optimal layout of a foot pattern changes by the board quality of material, the solder paste category to be used,
thickness, the soldering methodology, etc. Therefore, since the span where the terminator of this package may exist is
shown as a "soldering part terminator extent drawing", please give as reference data of a foot pattern design.
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Revision History
Page
Previous
Edition
Document No.
Date
Description
Current
Edition
FEDL610Q339-01
Apr. 18, 2022
―
―
Final edition 1
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Notes for product usage
Notes on this page are applicable to the all LAPIS Technology microcontroller products.
For individual notes on each LAPIS Technology microcontroller product, refer to [Note]
in the chapters of each user's manual.
The individual notes of each user’s manual take priority over those contents in this page if they are different.
1. HANDLING OF UNUSED INPUT PINS
Fix the unused input pins to the power pin or GND to prevent to cause the device performing wrong operation or
increasing the current consumption due to noise, etc. If the handlings for the unused pins are described in the
chapters, follow the instruction.
2. STATE AT POWER ON
At the power on, the data in the internal registers and output of the ports are undefined until the power supply voltage
reaches to the recommended operating condition and "L" level is input to the reset pin.
On LAPIS Technology microcontroller products that have the power on reset function, the data in the internal
registers and output of the ports are undefined until the power on reset is generated.
Be careful to design the application system does not work incorrectly due to the undefined data of internal registers
and output of the ports.
3. ACCESS TO UNUSED MEMORY
If reading from unused address area or writing to unused address area of the memory, the operations are not
guaranteed.
4. CHARACTERISTICS DIFFERENCE BETWEEN THE PRODUCT
Electrical characteristics, noise tolerance, noise radiation amount, and the other characteristics are different from
each microcontroller product.
When replacing from other product to LAPIS Technology microcontroller products, please evaluate enough the
apparatus/system which implemented LAPIS Technology microcontroller products.
5. USE ENVIRONMENT
When using LAPIS Technology microcontroller products in a high humidity environment and an environment where
dew condensation, take moisture-proof measures.
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Notes
1) The information contained herein is subject to change without notice.
2) When using LAPIS Technology Products, refer to the latest product information (data sheets, user’s manuals, application
notes, etc.), and ensure that usage conditions (absolute maximum ratings, recommended operating conditions, etc.) are within
the ranges specified. LAPIS Technology disclaims any and all liability for any malfunctions, failure or accident arising out of
or in connection with the use of LAPIS Technology Products outside of such usage conditions specified ranges, or without
observing precautions. Even if it is used within such usage conditions specified ranges, semiconductors can break down and
malfunction due to various factors. Therefore, in order to prevent personal injury, fire or the other damage from break down
or malfunction of LAPIS Technology Products, please take safety at your own risk measures such as complying with the
derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail-safe procedures.
You are responsible for evaluating the safety of the final products or systems manufactured by you.
3) Descriptions of circuits, software and other related information in this document are provided only to illustrate the standard
operation of semiconductor products and application examples. You are fully responsible for the incorporation or any other
use of the circuits, software, and information in the design of your product or system. And the peripheral conditions must be
taken into account when designing circuits for mass production. LAPIS Technology disclaims any and all liability for any
losses and damages incurred by you or third parties arising from the use of these circuits, software, and other related
information.
4) No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Technology
or any third party with respect to LAPIS Technology Products or the information contained in this document (including but
not limited to, the Product data, drawings, charts, programs, algorithms, and application examples，etc.). Therefore LAPIS
Technology shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising
out of the use of such technical information.
5) The Products are intended for use in general electronic equipment (AV/OA devices, communication, consumer systems,
gaming/entertainment sets, etc.) as well as the applications indicated in this document. For use of our Products in applications
requiring a high degree of reliability (as exemplified below), please be sure to contact a LAPIS Technology representative
and must obtain written agreement: transportation equipment (cars, ships, trains, etc.), primary communication equipment,
traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems,
etc. LAPIS Technology disclaims any and all liability for any losses and damages incurred by you or third parties arising by
using the Product for purposes not intended by us. Do not use our Products in applications requiring extremely high reliability,
such as aerospace equipment, nuclear power control systems, and submarine repeaters, etc.
6) The Products specified in this document are not designed to be radiation tolerant.
7) LAPIS Technology has used reasonable care to ensure the accuracy of the information contained in this document. However,
LAPIS Technology does not warrant that such information is error-free and LAPIS Technology shall have no responsibility
for any damages arising from any inaccuracy or misprint of such information.
8) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive.
LAPIS Technology shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws
or regulations.
9) When providing our Products and technologies contained in this document to other countries, you must abide by the
procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export
Administration Regulations and the Foreign Exchange and Foreign Trade Act..
10) Please contact a ROHM sales office if you have any questions regarding the information contained in this document or
LAPIS Technology's Products.
11) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Technology.
(Note) “LAPIS Technology” as used in this document means LAPIS Technology Co., Ltd.
Copyright 2022 LAPIS Technology Co., Ltd.
2-4-8 Shinyokohama, Kouhoku-ku,Yokohama 222-8575, Japan
http://www.lapis-tech.com/en/
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相关型号：
ML610Q339
ML610Q327/ML610Q338/ML610Q339是内置蓝碧石科技自有的RISC架构8位CPU“U8 Core”的、具有语音输出功能的高性能8位微控制器。产品搭载了高音质的语音播放功能和高输出扬声器放大器，以单芯片实现了语音输出功能，非常适用于警报器和家电应用。为了实现高音质的语音播放功能，利用新开发的高音质、高压缩比的语音压缩算法HQ-ADPCM，可以用比以往ADPCM更少的数据量来确保清晰的声音和宽广的音域，从而实现百听不厌、悦耳动听的声音。ML610Q327的播放时间约为70秒*1，ML610Q338/ML610Q339的播放时间约为95秒*1。此外，还可以外接高达128Mbit的Flash存储器，因此也支持更长时间的播放。通过将这种出色的语音播放功能、低功耗高性能的U8 Core、支持3V/5V的电源以及丰富的外围控制功能集成于1枚芯片，为电池驱动和AC驱动的产品提供单芯片语音播放解决方案。*：程序区使用16KB、采样频率为6.4kHz、选择HQ-ADPCM时。
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