W530H [ETC]
Analog IC ; 模拟IC\n
ETC 
W530
Frequency Multiplying, Peak Reducing EMI Solution
Features
Key Specifications
• Cypress PREMIS™ family offering
• Generates an EMI optimized clocking signal at the out-
put
• Selectable output frequency range
• Single 1.25%, 2.5%, 5% or 10% down or center spread
output
• Integrated loop filter components
• Operates with a 3.3 or 5V supply
• Low power CMOS design
Supply Voltages:......................................... V = 3.3V±0.3V
DD
or V = 5V±10%
DD
Frequency range: ............................13 MHz ≤ F ≤ 120 MHz
in
Cycle to Cycle Jitter: .........................................250 ps (max)
Output duty cycle: .................................40/60% (worst case)
• Available in 20-pin SSOP (Small Shrunk Outline
Package)
[1]
Simplified Block Diagram
Pin Configuration
3.3V or 5.0V
SSOP
X1
X1
X2
REFOUT
VDD
1
20
19
18
17
16
15
14
13
12
11
XTAL
Input
X2
2
AVDD
MW0^
STOP^
GND
IR1*
IR2*
3
Spread Spectrum
Output
(EMI suppressed)
W530
4
5
SSOUT
MW1*
GND
6
OR1^
NC
7
8
3.3V or 5.0V
GND
VDD
9
OR2*
10
SSON#^
MW2^
Oscillator or
Reference Input
X1
Spread Spectrum
W530
Note:
O utput
(EMI suppressed)
1. Pins marked with ^ are internal pull-down resistors
with weak 250 Ω. Pins marked with * are internal
pull-up resistors with weak 250 Ω.
PREMIS is a trademark of Cypress Semiconductor.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
November 22, 2000
W530
Pin Definitions
Pin
Pin Name
SSOUT
Pin No.
15
Type
Pin Description
I
Spread Spectrum Control.
REFOUT
20
O
Non-Modulated Output: This pin provides a copy of the reference frequency.
This output will not have the Spread Spectrum feature enabled regardless of
the state of logic input SSON#.
X1
1
I
Crystal Connection or External Reference Frequency Input: This pin has
dual functions. It may either be connected to an external crystal, or to an
external reference clock.
X2
2
I
I
Crystal Connection: Input connection for an external crystal. If using an ex-
ternal reference, this pin must be left unconnected.
SSON#
10
Spread Spectrum Control (Active LOW): Asserting this signal (active LOW)
turns the internal modulation waveform on. This pin has an internal pull-down
resistor.
MW0:2
IR1:2
4, 14, 11
17, 16
6, 9
I
I
I
Modulation Width Selection: When the Spread Spectrum feature is turned
on, these pins are used to select the amount of variation and peak EMI reduc-
tion that is desired on the output signal. MW0: Down, MW1: Up, MW2: Down.
(See Table 2.)
Reference Frequency Selection: Logic level provided at this input indicates
to the internal logic what range the reference frequency is in and determines
the factor by which the device multiplies the input frequency. Refer to Table 1.
These pins have internal pull-up resistors.
OR1:2
Output Frequency Selection Bits: These pins select the frequency operation
for the output. Refer to Table 1. OR1: DOWN, OR2: UP.
NC
7
5
NC
I
No Connection: Leave this pin unconnected.
STOP
Output Disable: When pulled HIGH, stops all outputs at logic low voltage
level. This pin has an internal pull-down.
VDD
12, 19
3
P
P
G
Power Connection: Connected to 3.3V or 5V power supply.
AVDD
GND
Analog Power Connection: Connected to 3.3V or 5V power supply.
Ground Connection: Connect all ground pins to the common ground plane.
8, 13, 18
2
W530
Table 1. Frequency Configuration Table
Range of Fin
Frequency
Multiplier Set-
tings
Output /
Input
Required R Set-
tings
Modulation & Power
Down Settings
Range of Fout
Min.
Max.
30
OR2
OR1
1
Min.
14
Max.
30
IR2
IR1
MW2
MW1
Table 2
14
14
14
25
25
25
50
50
50
0
1
1
0
1
1
0
1
1
0
0
0
0
1
2
0
1
30
0
28
60
0
1
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
Table 2
30
1
4
56
120
30
0
1
60
1
0.5
1
13
1
0
60
0
25
60
1
1
0
0
60
1
2
50
120
30
120
120
120
1
0.25
0.5
1
13
1
1
0
25
60
1
1
1
50
120
N/A
N/A
N/A
N/A
1
1
Reserved
0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
As Set
As Set
As Set
As Set
As Set
As Set
As Set
As Set
1
1
0
0
0
1
0
1
Power Down Hi-Z
Power Down 0
Power Down 1
0
0
0
Table 2. Modulation Percentage Selection Table
Bandwith Limit Frequencies as a % Value of Fout
MW0 = 0 MW0 = 1
High
EMI Reduction
Modulation Setting
MW2
MW1
Low
High
100%
100%
100%
100%
Low
99.375%
98.75%
97.5%
95%
Minimum EMI Control
Suggested Setting
0
0
1
1
0
1
0
1
98.75%
97.5%
95.0%
90.0%
100.625%
101.25%
102.5%
105%
Alternate Setting
Maximum EMI reduction
times the reference frequency. (Note: For the W530 the output
frequency is nominally equal to the input frequency.) The
unique feature of the Spread Spectrum Frequency Timing
Generator is that a modulating waveform is superimposed at
the input to the VCO. This causes the VCO output to be slowly
swept across a predetermined frequency band.
Overview
The W530 product is one of a series of devices in the Cypress
PREMIS family. The PREMIS family incorporates the latest
advances in PLL spread spectrum frequency synthesizer tech-
niques. By frequency modulating the output with a low fre-
quency carrier, peak EMI is greatly reduced. Use of this tech-
nology allows systems to pass increasingly difficult EMI testing
without resorting to costly shielding or redesign.
Because the modulating frequency is typically 1000 times
slower than the fundamental clock, the spread spectrum pro-
cess has little impact on system performance.
In a system, not only is EMI reduced in the various clock lines,
but also in all signals which are synchronized to the clock.
Therefore, the benefits of using this technology increase with
the number of address and data lines in the system. The Sim-
plified Block Diagram shows a simple implementation.
Frequency Selection With SSFTG
In Spread Spectrum Frequency Timing Generation, EMI re-
duction depends on the shape, modulation percentage, and
frequency of the modulating waveform. While the shape and
frequency of the modulating waveform are fixed for a given
frequency, the modulation percentage may be varied.
Functional Description
Using frequency select bits (FS2:1 pins), the frequency range
can be set (see Table 2). Spreading percentage is set with pins
MW as shown in Table 2.
The W530 uses a Phase Locked Loop (PLL) to frequency
modulate an input clock. The result is an output clock whose
frequency is slowly swept over a narrow band near the input
signal. The basic circuit topology is shown in Figure 1. The
input reference signal is divided by Q and fed to the phase
detector. A signal from the VCO is divided by P and fed back
to the phase detector also. The PLL will force the frequency of
the VCO output signal to change until the divided output signal
and the divided reference signal match at the phase detector
input. The output frequency is then equal to the ratio of P/Q
A larger spreading percentage improves EMI reduction. How-
ever, large spread percentages may either exceed system
maximum frequency ratings or lower the average frequency to
a point where performance is affected. For these reasons,
spreading percentage options are provided.
3
W530
VDD
Clock Input
SSOUT
(EMI suppressed)
Freq.
Divider
Q
Phase
Detector
Charge
Pump
Post
Dividers
Reference Input
Σ
VCO
Modulating
Waveform
Feedback
Divider
P
PLL
GND
Figure 1. Functional Block Diagram
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing Generator
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Table 2.
The output clock is modulated with a waveform depicted in
Figure 3. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is described in Table 2. Figure
3 details the Cypress spreading pattern. Cypress does offer
options with more spread and greater EMI reduction. Contact
your local Sales representative for details on these devices.
As shown in Table 2, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
dB = 6.5 + 9*log (P) + 9*log (F)
10
10
4
W530
EMI Reduction
SSFTG
Typical Clock
Spread
Spectrum
Enabled
Non-
Spread
Spectrum
Frequency Span (MHz)
Down Spread
Frequency Span (MHz)
Center Spread
Figure 2. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 3. Typical Modulation Profile
5
W530
Absolute Maximum Ratings
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
0 to +70
Unit
V
V
, V
DD IN
T
°C
°C
°C
W
STG
T
Operating Temperature
A
T
Ambient Temperature under Bias
Power Dissipation
–55 to +125
0.5
B
P
D
: 0°C < T < 70°C, V = 3.3V ± 0.3V
DC Electrical Characteristics
A
DD
Parameter
Description
Supply Current
Test Condition
Min.
Typ.
Max.
Unit
mA
ms
I
18
32
5
DD
ON
t
Power Up Time
First locked clock cycle after Power
Good
V
V
V
V
Input Low Voltage
0.8
0.4
V
V
IL
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
2.4
2.4
IH
V
OL
OH
V
I
I
I
I
Note 2
Note 2
–100
µA
µA
mA
mA
pF
kΩ
Ω
IL
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
10
IH
@ 0.4V, V = 3.3V
15
15
OL
OH
DD
@ 2.4V, V = 3.3V
DD
C
R
7
I
250
25
P
Z
OUT
Note:
2. Inputs OR1:2 and IR1:2 have a pull-up resistor, Input SSON# has a pull-down resistor.
6
W530
DC Electrical Characteristics: 0°C < T < 70°C, V = 5V ±10%
A
DD
Parameter
Description
Supply Current
Test Condition
Min.
Typ.
Max.
50
Unit
mA
ms
I
t
30
DD
ON
Power Up Time
First locked clock cycle after
Power Good
5
V
V
V
V
Input Low Voltage
0.15V
0.4
V
V
IL
DD
Input High Voltage
Output Low Voltage
Output High Voltage
Input Low Current
0.7V
DD
IH
V
OL
OH
2.4
V
I
I
I
I
Note 2
Note 2
–100
µA
µA
mA
mA
pF
kΩ
Ω
IL
Input High Current
Output Low Current
Output High Current
Input Capacitance
Input Pull-Up Resistor
Clock Output Impedance
10
IH
@ 0.4V, V = 5V
24
24
OL
OH
DD
@ 2.4V, V = 5V
DD
C
R
7
I
250
25
P
Z
OUT
AC Electrical Characteristics: T = 0°C to +70°C, V = 3.3V ±0.3V or 5V±10%
A
DD
Symbol
Parameter
Input Frequency
Test Condition
Min.
14
Typ.
Max.
Unit
MHz
MHz
ns
f
Input Clock
120
120
5
IN
f
t
t
t
t
t
Output Frequency
Output Rise Time
Output Fall Time
Output Duty Cycle
Input Duty Cycle
Jitter, Cycle-to-Cycle
Spread Off
13
OUT
R
15-pF load, 0.8V–2.4V
15-pF load, 2.4 –0.8V
15-pF load
2
2
5
ns
F
40
40
60
60
300
%
OD
ID
%
250
ps
JCYC
Ordering Information
Package
Name
Ordering Code
Package Type
W530
H
20-Pin Plastic SSOP (209-mil)
Document #: 38-00913-*A
7
W530
Package Diagram
20-Pin Small Shrink Outline Package (SSOP, 209-mil)
© Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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