FAN302HLMY_F117 [FAIRCHILD]
Battery Charge Controller;
| 型号： | FAN302HLMY_F117 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Battery Charge Controller 电池 |
| 文件： | 总19页 (文件大小：939K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2013
FAN302HLMY_F117
PWM Controller for Low Standby Power Battery-
Charger Applications — mWSaver™ Technology
Description
Features
The FAN302HLMY_F117 advanced PWM controller
significantly simplifies isolated power supply design that
requires CC regulation of the output. The output current
is precisely estimated with information in the primary
side of the transformer and controlled with an internal
compensation circuit. This removes the output current
sensing loss and eliminates all external Control Circuitry
(CC). The Green-Mode function, with an extremely low
operating current (200 µA) in Burst Mode, maximizes
the light-load efficiency, enabling conformance to
worldwide Standby Mode efficiency guidelines.
.
mWSaver™ Technology Provides Industry’s
Best-in-Class Standby Power
- Ultra Low Power Consumption at No Load
(<10 mW at 230 VAC
)
- Proprietary 500V High-Voltage JFET Startup
Reduces Startup Resistor Loss
- Low Operation Current in Burst Mode:
350 µA Maximum
.
.
Constant-Current (CC) Control without Secondary-
Feedback Circuitry
Integrated protections include two-level pulse-by-pulse
current limit, Over-Voltage Protection (OVP), brownout
protection, and Over-Temperature Protection (OTP).
Fixed PWM Frequency at 85kHz with Frequency
Hopping to Reduce EMI
Compared with a conventional approach using an
external control circuit in the secondary side for CC
regulation, the FAN302HLMY_F117 can reduce total
cost, component count, size, and weight; while
simultaneously increasing efficiency, productivity, and
system reliability.
.
.
.
High-Voltage Startup
Low Operating Current: 3.5 mA
Peak-Current-Mode Control with Slope
Compensation
.
.
.
.
.
.
.
Cycle-by-Cycle Current Limiting
Maximum
Typical
VO
VDD Over-Voltage Protection (Auto-Restart)
VS Over-Voltage Protection (Latch Mode)
VDD Under-Voltage Lockout (UVLO)
Minimum
Gate Output Maximum Voltage Clamped at 15 V
Fixed Over-Temperature Protection (Latch Mode)
Available in an 8-Lead SOIC Package
Applications
IO
.
Battery Chargers for Cellular Phones, Cordless
Phones, PDAs, Digital Cameras, and Power Tools
Figure 1. Typical Output V-I Characteristic
.
Replaces Linear Regulators and RCC SMPS
Ordering Information
Operating
Temperature Range
Packing
Method
Part Number
Package
8-Lead, Small Outline Package (SOIC),
JEDEC MS-012, .150-Inch Narrow Body
FAN302HLMY_F117
Tape & Reel
-40°C to +105°C
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
Application Diagram
Figure 2. Typical Application
Internal Block Diagram
Figure 3. Functional Block Diagram
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
2
Marking Information
F- Fairchild Logo
Z: Assembly Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: M=SOIC
P: Y= Green Package
M: Manufacture Flow Code
Figure 4.Top Mark
Pin Configuration
CS
GATE
VDD
VS
HV
NC
FB
GND
Figure 5. Pin Assignments
Pin Definitions
Pin #
Name
Description
Current Sense. This pin connects a current-sense resistor to sense the MOSFET current for
Peak-Current-Mode control for output regulation. The current-sense information is also used to
estimate the output current for CC regulation.
1
CS
PWM Signal Output. This pin has an internal totem-pole output driver to drive the power
MOSFET. It is internally clamped at 15 V.
2
3
GATE
VDD
Power Supply. IC operating current and MOSFET driving current are supplied through this pin.
This pin is typically connected to an external VDD capacitor.
Voltage Sense. This pin detects the output voltage information and diode current discharge
time based on the voltage of the auxiliary winding.
4
5
6
VS
GND
FB
Ground
Feedback. Typically, an opto-coupler is connected to this pin to provide feedback information to
the internal PWM comparator. This feedback is used to control the duty cycle in CV regulation.
7
8
NC
HV
No Connect
High Voltage. This pin connects to the DC bus for high-voltage startup.
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
3
Absolute Maximum Ratings
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
VHV
Parameter
Min.
Max.
500
30
Unit
V
HV Pin Input Voltage
DC Supply Voltage(1,2)
VS Pin Input Voltage
CS Pin Input Voltage
FB Pin Input Voltage
VVDD
VVS
V
-0.3
-0.3
-0.3
7.0
V
VCS
7.0
V
VFB
7.0
V
PD
660
150
mW
Power Dissipation (TA=25°C)
θJA
Thermal Resistance (Junction-to-Air)
Thermal Resistance (Junction-to-Case)
Operating Junction Temperature
°C/W
°C/W
°C
θJC
TJ
39
-40
-55
+150
+150
+260
TSTG
TL
Storage Temperature Range
°C
Lead Temperature, (Wave Soldering or IR, 10 Seconds)
°C
Human Body Model,
JEDEC:JESD22_A114
5000
1500
(Except HV Pin)(3)
Electrostatic Discharge Capability
ESD
V
Charged Device Model,
JEDEC:JESD22_C101
(Except HV Pin)(3)
Notes:
1. All voltage values, except differential voltages, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD ratings including the HV pin: HBM=400 V, CDM=750 V.
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
4
Electrical Characteristics
VDD=15 V and TA=25°C unless noted.
Symbol
HV Section
VHV-MIN
Parameter
Condition
Min. Typ. Max. Unit
Minimum Startup Voltage on HV Pin
Supply Current Drawn from HV Pin
50
V
V
HV=100 V, VDD=0 V,
Controller Off
IHV
0.8
1.5
0.8
5.0
mA
VHV=500 V, VDD=15 V
(Controller On with Auxiliary
Supply)
IHV-LC
Leakage Current Drawn from HV Pin
3.0
μA
VDD Section
Limited by VDD Over-Voltage
Protection (OVP)
VOP
Continuous Operation Voltage
25
V
VDD-ON
VDD-OFF
VDD-LH
IDD-ST
Turn-On Threshold Voltage
Turn-Off Threshold Voltage
VDD Rising
VDD Falling
15
16
5.0
17
V
V
4.7
5.3
Threshold Voltage for Latch-Off Release VDD Falling
2.5
V
Startup Current
VDD=VDD-ON – 0.16 V
400
3.5
450
4.0
μA
mA
μA
V
IDD-OP
Operating Supply Current
VDD=18 V, f=fOSC, CGATE=1 nF
VDD=8 V, CGATE=1 nF
IDD-BURST Burst-Mode Operating Supply Current
200
26.5
350
28.0
VDD-OVP
VDD Over-Voltage Protection Level
25.0
82
VDD Over-Voltage Protection Debounce
Time
tD-VDDOVP
f=85 kHz
100
180
μs
Oscillator Section
Center Frequency VCS=5 V, VS=2.5 V, VFB=5 V
Hopping Range
85
88
fOSC
Frequency
kHz
±3
Minimum Frequency for Continuous
fOSC-CM-MIN
Conduction Mode (CCM) Prevention
13
23
18
26
23
29
kHz
kHz
Circuit(4)
Minimum Frequency in Constant Current
(CC) Regulation
fOSC-CCM
VCS=5 V, VS=0 V
Feedback Input Section
Internal Voltage Scale-Down Ratio of FB
AV
1/3.5 1/3.0 1/2.5 V/V
Pin(5)
ZFB
FB Pin Input Impedance
38
42
44
kΩ
VFB-OPEN FB Pin Pull-Up Voltage
FB Threshold to Disable Gate Drive in
FB Pin Open
5.3
V
VFB-L
VFB Falling,VCS=5 V, VS=0 V
1.2
1.3
1.4
1.5
1.6
1.7
V
V
Burst Mode
FB Threshold to Enable Gate Drive in
Burst Mode
VFB-H
VFB Rising,VCS=5 V, VS=0 V
Over-Temperature Protection Section
Threshold for Over-Temperature
Protection (OVP)
TOTP
+130 +140 +150
°C
Continued on the following page…
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
5
Electrical Characteristics (Continued)
VDD=15 V and TA=25°C unless noted.
Symbol
Parameter
Condition
Min. Typ. Max. Unit
Voltage-Sense Section
ITC
Bias Current
VS Sampling Voltage to Switch to the
VCS=5 V
8.75 10.00 11.25
0.55
μA
VVS-CM-MIN Second Pulse-by-Pulse Current Limit in
V
Power Limit Mode(6)
VS Sampling Voltage to Switch Back to the
VVS-CM-MAX
0.75
V
V
V
Normal Pulse-by-Pulse Current Limit(6)
VS Sampling Voltage to Start Frequency
Decreasing in CC Mode
VSN-CC
V
CS=5 V, fS1=fOSC-2 kHz
CS=5 V, fS2=fOSC-CCM
2.05
0.45
30
2.15 2.25
0.70 0.95
Vs Sampling Voltage to End Frequency
Decreasing in CC Mode
V
VSG-CC
+2 kHz
G-CC= (fS1-fS2) / (VSN-CC
VSG-CC
Frequency Decreasing Slope of CC
Regulation
S
-
kHz/V
mV
V
SG-CC
38
46
)
VVS-OFFSET ZCD Comparator Internal Offset Voltage(6)
200
Output Over-Voltage Protection with VS
Sampling Voltage
VVS-OVP
2.70
2.80 2.85
8
Output Over-Voltage Protection Debounce
tVS-OVP
Time
fOSC=85 kHz
cycles
Current-Sense Section
Internal Reference Voltage for CC
Regulation
VVR
2.475 2.500 2.525
2.405 2.430 2.455
V
V
Variation Test Voltage on CS Pin for CC
Output (Non-Inverting Input of Error
Amplifier for CC Regulation)
VCCR
VCS=0.47 V
VSTH
VSTH-VA
tPD
Normal Current Limit Threshold Voltage
Second Current Limit Threshold Voltage,
0.8
V
V
VVS=0.3 V
0.30
Power Limit Mode (VS<VVS-CM-MAX
)
GATE Output Turn-Off Delay
100
530
150
630
200
ns
ns
VCS=5 V, VVS=2.5 V,
tMIN
Minimum On Time
430
100
VFB=5 V (Test Mode)
tLEB
Leading-Edge Blanking Time(6)
Slope Compensation(6)
150
0.3
ns
V
VSLOPE
Maximum Duty Cycle
GATE Section
DMAX
Maximum Duty Cycle
Output Voltage Low
64
0
67
70
1.5
8
%
V
VGATE-L
VDD=25 V, IO=10 mA
VDD=8 V, IO=1 mA
VGATE-H Output Voltage High
VGATE-H Output Voltage High
5
V
VDD=5.5 V, IO=1 mA
VDD=15 V, CGATE=1 nF
VDD=15 V, CGATE=1 nF
4.0
100
30
5.5
180
70
V
tr
tf
Rising Time
Falling Time
140
50
ns
ns
VGATE-
CLAMP
Gate Output Clamping Voltage
VDD=25 V
13
15
17
V
Notes:
4. fOSC-CM-MIN occurs when the power unit enters CCM operation.
5. AV is a scale-down ratio of the internal voltage divider of the FB pin.
6. Guaranteed by design; not production tested.
© 2012 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN302HLMY_F117 • Rev. 1.0.2
6
Typical Performance Characteristics
16.8
16.5
16.2
15.9
15.6
15.3
15.0
5.04
5.01
4.98
4.95
4.92
4.89
4.86
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 6. VDD Turn-On Threshold Voltage (VDD-ON
)
Figure 7. VDD Turn-Off Threshold Voltage (VDD-OFF
)
vs. Temperature
vs. Temperature
4.0
3.7
3.4
3.1
2.8
2.5
2.2
0.23
0.22
0.21
0.20
0.19
0.18
0.17
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 8. Operating Current (IDD-OP) vs. Temperature
Figure 9. Burst Mode Operating Current (IDD-BURST
vs. Temperature
)
28
27
26
25
24
23
22
1.50
1.45
1.40
1.35
1.30
1.25
1.20
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 10. CC Regulation Minimum Frequency
(fOSC-CCM) vs. Temperature
Figure 11. Enter Zero-Duty Cycle of FB Voltage (VFB-L
vs. Temperature
)
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
7
Typical Performance Characteristics
1.80
1.70
1.60
1.50
1.40
1.30
1.20
2.95
2.90
2.85
2.80
2.75
2.70
2.65
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 12. Leave Zero Duty Cycle of FB Voltage
(VFB-H) vs. Temperature
Figure 13. VS Over-Voltage Protection (VVS-OVP
vs. Temperature
)
2.53
2.52
2.51
2.50
2.49
2.48
2.47
2.50
2.48
2.46
2.44
2.42
2.40
2.38
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 14. Reference Voltage of CS (VVR
)
Figure 15.Variation Voltage on CS Pin for Constant-
Current Regulation (VCCR) vs. Temperature
vs. Temperature
2.18
2.17
2.16
2.15
2.14
2.13
2.12
1
0.9
0.8
0.7
0.6
0.5
0.4
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 16. Starting Voltage of Frequency Decreasing Figure 17. Ending Voltage of Frequency Decreasing of
of CC Regulation (VSN-CC) vs. Temperature CC Regulation (VSG-CC) vs. Temperature
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
8
Typical Performance Characteristics
0.33
0.32
0.31
0.3
0.83
0.82
0.81
0.80
0.79
0.78
0.77
0.76
0.75
0.29
0.28
0.27
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 18. Threshold Voltage for Current Limit (VSTH
)
Figure 19. Threshold Voltage for Current Limit at
Power Mode (VSTH-VA) vs. Temperature
vs. Temperature
590
580
570
560
550
540
530
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Figure 20. Minimum On Time (tMIN) vs. Temperature
Figure 21.Leading-Edge Blanking Time (tLEB
)
vs. Temperature
67.6
67.4
67.2
67.0
66.8
66.6
66.4
16.5
16.0
15.5
15.0
14.5
14.0
13.5
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
25
50
75
85
100
125
Temperature (ºC)
Temperature (ºC)
Figure 22. Maximum Duty Cycle (DCYMAX
vs. Temperature
)
Figure 23. Gate Output Clamp Voltage (VGATE-CLAMP
vs. Temperature
)
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
9
Operational Description
Basic Control Principle
Figure 24 shows the internal PWM control circuit. The
constant voltage (CV) regulation is implemented in the
same way as the conventional isolated power supply,
where the output voltage is sensed using a voltage
divider and compared with the internal 2.5 V reference
of
a
shunt regulator (KA431) to generate
a
compensation signal. The compensation signal is
transferred to the primary side using an opto-coupler
and scaled down through attenuator Av, generating the
VEA.V signal. Then the error signal VEA.V is applied to the
PWM comparator (PWM.V) to determine the duty cycle.
Meanwhile, the CC regulation is implemented internally
without directly sensing the output current. The output
current estimator reconstructs output current information
(VCCR) using the transformer primary-side current and
diode current discharge time. Then VCCR is compared
with a reference voltage (2.5 V) by an internal error
amplifier, generating the VEA.I signal to determine the
duty cycle.
Figure 25. PWM Operation for CC and CV
Output Current Estimation
Figure 26 shows the key waveform of a flyback
converter operating in Discontinuous Conduction Mode
(DCM), where the secondary-side diode current reaches
zero before the next switching cycle begins. Since the
output current estimator is designed for DCM operation,
the power stage should be designed such that DCM is
guaranteed for the entire operating range. The output
current is obtained by averaging the triangular output
diode current area over a switching cycle:
The two error signals, VEA.I and VEA.V, are compared with
an internal sawtooth waveform (VSAW
) by PWM
comparators PWM.I and PWM.V to determine the duty
cycle. As shown in Figure 25, the outputs of two
comparators (PWM.I and PWM.V) are combined with an
OR gate and used as a reset signal of flip-flop to
determine the MOSFET turn-off instant. The lower
signal, VEA.V or VEA.I, determines the duty cycle, as
shown in Figure 25. During CV regulation, VEA.V
determines the duty cycle while VEA.I is saturated to
HIGH. During CC regulation, VEA.I determines the duty
cycle while VEA.V is saturated to HIGH.
NP tDIS
IO =< ID >AVG = IPK
•
(1)
NS 2tS
where IPK is the peak value of the primary-side
current; NP and NS are the number of turns of
transformer
primary-side
and
secondary-side,
respectively; tDIS is the diode current discharge time;
and tS is the switching period.
With a given current sensing resistor, the output current
can be programmed as:
1.25
NP
IO
=
(2)
K • RSENSE NS
where K is the design parameter of IC, which is 10.5.
The peak value of primary-side current is obtained by an
internal peak detection circuit, while diode current
discharge time is obtained by detecting the diode
current zero-crossing instant. Since the diode current
cannot be sensed directly with primary-side control,
Zero Crossing Detection (ZCD) is accomplished
indirectly by monitoring the auxiliary winding voltage.
When the diode current reaches zero, the transformer
winding voltage begins to drop by the resonance
between the MOSFET output capacitance and the
transformer magnetizing inductance. To detect the
starting instant of the resonance, the VS is sampled at
85% of diode current discharge time of the previous
switching cycle, then compared with the instantaneous
VS voltage. When instantaneous VS drops below the
sampled voltage by more than 200 mV, ZCD of diode
current is obtained, as shown in Figure 27.
Figure 24. Internal PWM Control Circuit
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
10
I PK
NP
NS
IPK
⋅
< ID >AVG = IO
Figure 26. Key Waveforms of DCM Flyback
Converter
Figure 28. tDIS Variation in CC Mode
Figure 29. Frequency Reduction with VSH
Switching Freq. (kHz)
Figure 27. Detailed Waveform for ZCD
Frequency Reduction in CC Mode
An important design consideration is that the
transformer guarantee DCM operation across the whole
range since the output current is properly estimated only
in DCM operation. As can be seen in Figure 28, the
discharge time (tDIS) of the diode current increases as
the output voltage decreases in CC Mode. The
converter tends to go into CCM as output voltage drops
in CC Mode when operating at the fixed switching
frequency. To prevent this CCM operation while
maintaining good output current estimation in DCM,
FAN302HLMY_F117 decreases switching frequency as
output voltage drops, as shown in Figure 28 and Figure
29. FAN302HLMY_F117 indirectly monitors the output
voltage by the sample-and-hold voltage (VSH) of VS,
which is taken at 85% of diode current discharge time of
the previous switching cycle, as shown in Figure 27.
Figure 30 shows how the frequency reduces as the
sample-and-hold voltage of VS decreases.
2kHz
85kHz
83kHz
Δf
ΔV
= SG−CC
2kHz
28kHz
26kHz
VSH
VSN-CC
VSG-CC
Figure 30. Frequency Reduction Curve in
CC Regulation
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
11
CCM Prevention Function
Even if the power supply is designed to operate in DCM,
it can go into CCM when there is not enough design
margin to cover all the circuit parameter variations and
operating conditions. FAN302HLMY_F117 has a CCM-
prevention function that delays the next cycle turn-on of
MOSFET until ZCD on the VS pin is obtained, as shown
in Figure 31. To guarantee stable DCM operation,
FAN302HLMY_F117 prohibits the turn-on of the next
switching cycle for 10% of its switching period after ZCD
is obtained. In Figure 31, the first switching cycle has
ZCD before 90% of its original switching period and,
therefore, the turn-on instant of the next cycle is
determined without being affected by the ZCD instant.
The second switching cycle does not have ZCD by the
end of the original switching period; thus, the turn-on of
the third switching cycle occurs after ZCD is obtained,
with a delay of 10% of its original switching period. The
minimum switching frequency that CCM prevention
function allows is 18 kHz (fOSC-CM-MIN). If the ZCD is not
given until the end of maximum switching period of
55.6 µs (1/18 kHz), the converter can go into CCM
operation, losing output regulation.
Figure 32. Power Limit Mode Operation
High-Voltage Startup
Figure 33 shows the high-voltage (HV) startup circuit.
Internally, JFET is used to implement the high-voltage
current source, whose characteristics are shown in
Figure 34. Technically, the HV pin can be directly
connected to the DC link (VDL). To improve reliability
and surge immunity; it is typical to use about a 100 kꢀ
resistor between the HV pin and the DC link. The actual
HV current with given DC link voltage and startup
resistor is determined by the intersection of V-I
characteristics line and load line, as shown in Figure 34.
During startup, the internal startup circuit is enabled and
the DC link supplies the current, IHV, to charge the hold-
up capacitor, CVDD, through RSTART. When the VDD
voltage reaches VDD-ON, the internal HV startup circuit is
disabled and the IC starts PWM switching. Once the HV
startup circuit is disabled, the energy stored in CVDD
should supply the IC operating current until the
transformer auxiliary winding voltage reaches the
nominal value. Therefore, CVDD should be designed to
prevent VDD from dropping to VDD-OFF before the auxiliary
winding builds up enough voltage to supply VDD
Capacitance tolerance is an important factor to consider
for CDD selection. Connecting 22 μF capacitor
.
a
between the VDD and GND pins is recommended to
ensure system stability across the wide operation
temperature range.
Figure 31. CCM Prevention Function
Power Limit Mode
When the sampled voltage of VS (VSH) drops below VS-
(0.55 V), FAN302HLMY_F117 enters constant
CM-MIN
Power Limit Mode, where the primary-side current-limit
voltage (VCS) changes from VSTH (0.8 V) to VSTH-VA
(0.3 V) to avoid VS sampling and ZCD, as shown in
Figure 32. Once VS sampling voltage is higher than VS-
(0.75 V), the VCS returns to VSTH. This mode
CM-MAX
prevents the power supply from going into CCM and
losing output regulation when the output voltage is too
low. This effectively protects the power supply when
there is a fault condition in the load, such as output
short or overload. This mode also implements soft-start
by limiting the transformer current until VS sampling
voltage reaches VS-CM-MAX (0.75 V).
Figure 33. HV Startup Circuit
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
12
VDL −VHV
IHV
=
RHV
VDL
RHV
Figure 36. Burst-Mode Operation
VDL
Figure 34.V-I Characteristics of HV Pin
Slope Compensation
The sensed voltage across the current-sense resistor is
used for Current-Mode control and pulse-by-pulse
Frequency Hopping
EMI reduction is accomplished by frequency hopping,
which spreads the energy over a wider frequency range
than the bandwidth of the EMI test equipment. The
frequency-hopping circuit changes the switching
frequency progressively between 82 kHz and 88 kHz
with a period of tp, as shown in Figure 35.
current limiting.
A synchronized ramp signal with
positive slope is added to the current sense information
at each switching cycle, improving noise immunity of
Current-Mode control.
Protections
The self-protection functions include VDD Over-Voltage
Protection (OVP), internal Over-Temperature Protection
(OTP), VS Over-Voltage Protection (OVP), and
brownout protection. VDD OVP and brownout protection
are implemented as Auto-Restart Mode, while the VS
OVP and internal OTP are implemented as Latch Mode.
When an Auto-Restart Mode protection is triggered,
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD turn-
off voltage of 5 V; the protection is reset, the internal
startup circuit is enabled, and the supply current drawn
from the HV pin charges the hold-up capacitor. When
VDD reaches the turn-on voltage of 16 V, normal
operation resumes. In this manner, auto-restart
alternately enables and disables MOSFET switching
until the abnormal condition is eliminated, as shown in
Figure 37.
When a Latch Mode protection is triggered, PWM
switching is terminated and the MOSFET remains off,
causing VDD to drop. When VDD drops to the VDD turn-off
voltage of 5 V, the internal startup circuit is enabled
without resetting the protection and the supply current
drawn from HV pin charges the hold-up capacitor. Since
the protection is not reset, the IC does not resume PWM
switching even when VDD reaches the turn-on voltage of
16 V, disabling HV startup circuit. Then VDD drops down
to 5 V. In this manner, the Latch Mode protection
alternately charges and discharges VDD until there is no
more energy in the DC link capacitor. The protection is
reset when VDD drops to 2.5 V, which is allowed only
after the power supply is unplugged from the AC line, as
shown in Figure 38.
Figure 35. Frequency Hopping
Burst-Mode Operation
The power supply enters Burst Mode at no-load or
extremely light-load conditions. As shown in Figure 36,
when VFB drops below VFBL; the PWM output shuts off
and the output voltage drops at a rate dependent on
load current. This causes the feedback voltage to rise.
Once VFB exceeds VFBH, the internal circuit starts to
provide switching pulse. The feedback voltage then falls
and the process repeats. Burst Mode operation
alternately enables and disables switching of the
MOSFET, reducing the switching losses in Standby
Mode. Once FAN302HLMY_F117 enters Burst Mode,
the operating current is reduced from 3.5 mA to 200 μA
to minimize power consumption.
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
13
Input Voltage Sensing
Power On
The FAN302HL indirectly senses input voltage using the
VS pin current while the MOSFET is turned on. Since
the VS pin voltage is clamped at 0.7 V when the
MOSFET is turned on, the current flowing out of the VS
pin is approximately proportional to the input voltage as:
VDS
NA
(
VDL + 0.7)
Fault
Occurs
VDD
NP
0.7 NA VDL
+ ≅
(3)
IVS.ON
=
VDD-OVP
RVS1
RVS 2 NP RVS1
VDD-ON
Fault
Removed
VDD-OFF
Operating Current
IDD-OP
IDD-ST
Figure 37. Auto-Restart Mode Operation
Figure 39. Vs Pin Current Sensing
FAN302HL modulates the minimum on time of the
MOSFET such that it reduces as input voltage
increases, as shown Figure 40. This allows smaller
minimum on time for high line condition, ensuring Burst
Mode operation occurs at almost same power level
regardless of line voltage variation. The minimum on
time is related to the bundle frequency of Burst Mode.
When selecting RVS1 and RVS2, 150 µA is the VS current
level to consider seriously. If the VS current is lower
than 150 µA, ton_min won’t be larger.
tON.MIN (µs)
Figure 38. Latch-Mode Operation
Over-Temperature Protection (OTP)
The temperature-sensing circuit shuts down PWM
output if the junction temperature exceeds 140°C (tOTP).
150 µA, Minimum value
VDD Over-Voltage Protection
VDD over-voltage protection prevents IC damage from
over-voltage exceeding the IC voltage rating. When the
VDD voltage exceeds 26.5 V due to an abnormal
condition, the protection is triggered. This protection is
typically caused by open circuit in the secondary-side
feedback network.
IVS (µA)
Figure 40. Minimum On Time vs. VS Pin Current
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
14
VS Over-Voltage Protection (OVP)
VS over-voltage protection prevents damage due to
output over-voltage conditions. Figure 41 shows the
VS OVP protection method. The OVP is triggered
when the VS sampling voltage is above 2.8 V (VVS_OVP
)
for longer than eight switching cycles. Then PWM
pulses are disabled and FAN302HL enters Latch
Mode. The protection is reset and normal operation
resumes when VDD drops below VDD-LH. VS over-
voltage conditions are usually caused by an open
circuit in the secondary-side feedback network or
abnormal behavior by the VS pin divider resistor.
Figure 41. VS OVP Protection
Leading-Edge Blanking (LEB)
When the secondary-side feedback circuit is opened,
no current flows through the opto-coupler diode, which
pulls up the feedback voltage, commanding maximum
power be delivered to the load. Since more power than
the load demand is delivered, the output voltage rises
until the OVP is triggered.
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a 150 ns leading-
edge blanking time is built in. Conventional RC filtering
can therefore be omitted. During this blanking period,
the current-limit comparator is disabled and it cannot
switch off the gate driver.
The worst-case OVP trip point at no load is calculated as:
2
Noise Immunity
NS R +R
2ESURPLUS
VOOVP
=
V
+
VS1
VS 2
Noise from the current sense or the control signal can
cause significant pulse-width jitter. While slope
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoid long PCB
traces and component leads. Locate bypass filter
components near the PWM IC.
(4)
VS_OVP NA
R
CO
VS2
where ESURPLUS is the surplus energy delivered to the
load during the debounce time.
The ESURPLUS can be defined as:
2
L
VSTH
RCS
V
m
DL (tDLY.OFF
Lm
)
×8
(5)
ESURPLUS
=
+
2
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
15
Typical Application Circuit (Flyback Charger)
Application
Fairchild Device
Input Voltage Range
Output
Cell Phone Charger
FAN302HLMY_F117
90~265 VAC
5 V/1.2 A (6 W)
Features
.
.
High Efficiency (>71% Avg.), Meets Energy Star V2.0 Standard (Avg. 68.17%)
Ultra-Low Standby Power Consumption, <10 mW at 230 VAC (Pin=6.3 mW for 115 VAC and Pin=7.3 mW
for 230 VAC
Output Regulation: CV= ±5%, CC= ±15%
)
.
Figure 42. Measured Efficiency and Output Regulation
C6
R12
1mH
L1
EI12.5 93T/7T/11T
1.8µH
L3
VO
IO
10Ω
1nF
D7
R1
10Ω
+
VDL
-
C4
R10
270KΩ
3A/40V
NS
NP
C1
470pF
C2
C9
330µF
C8
330µF
6.8µF
6.8µF
AC Line
R3
0Ω
D1~D4
FFM107M*4
D6
FFM107M
47Ω
R5
D9
R11
5.6KΩ
R20
1KΩ
R2
10Ω
4A/650V
Q1
1N4148
D5
R18
FAN302HLMY_F11
7
64.9KΩ
R4
100Ω
R9
FOD817S
TL431
IN4935
C7
1
2
3
4
CS
8
7
6
5
HV
NA
R6 0Ω
10nF
GATE
VDD
VS
NC
1.3ꢀ
FB
R17
63.4KΩ
C3
C10
1nF
R7
33µF
GND
91KΩ
C11
U1
470pF
R8
C5
40.2KΩ
20pF
Figure 43.Schematic of Typical Application Circuit
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
16
Typical Application Circuit (Continued)
Transformer Specification
.
.
Core: EI12.5
Bobbin: EI12.5
Figure 44.Transformer
Notes:
7. W1 consists of four layers with different number of turns. The number of turns of each layer is specified in Table
1. Add one insulation tape between the second and third layers.
8. W2 consists of two layers with triple-insulated wire. The leads of positive and negative fly lines are 3.5 cm and
2.5 cm, respectively.
9. W3 is space winding in one layer.
Table 1. Transformer Winding Specifications
Terminal
Insulation
NO.
Wire
Turns
Start Pin
End Pin
Turns
26
25
24
18
7
0
1
0
2
2
2
3
0
2
W1
4
5
2UEW 0.1*1
W2
W3
Fly+
1
Fly-
2
TEX-E 0.45*1
2UEW 0.18*1
Core Rounding Tape
Core
11
W4
2
2UEW 0.18*1
5
Note:
10. W4 is the outermost and space winding.
Pin
Specifications
Remark
Primary-Side Inductance
4－5
4－5
100 kHz, 1 V
Short One of the Secondary-Side Windings
700 μH ±7%
130 μH ±7%
Primary-Side Leakage Inductance
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
17
Physical Dimensions
5.00
4.80
A
0.65
3.81
8
5
B
1.75
6.20
5.80
4.00
3.80
5.60
1
4
PIN ONE
INDICATOR
1.27
1.27
(0.33)
M
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
0.19
C
1.75 MAX
0.10
C
0.51
0.33
OPTION A - BEVEL EDGE
0.50
0.25
x 45°
R0.10
R0.10
GAGE PLANE
OPTION B - NO BEVEL EDGE
0.36
NOTES: UNLESS OTHERWISE SPECIFIED
8°
0°
0.90
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
SEATING PLANE
(1.04)
0.406
D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
E) DRAWING FILENAME: M08AREV13
DETAIL A
SCALE: 2:1
Figure 45. 8-Lead, Small Outline Package (SOIC), JEDEC MS-012, .150-Inch, Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
18
© 2012 Fairchild Semiconductor Corporation
FAN302HLMY_F117 • Rev. 1.0.2
www.fairchildsemi.com
19
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