FIN224AC_0611 [FAIRCHILD]
uSerDes 22-Bit Bi-Directional Serializer/Deserializer; uSerDes 22位双向串行器/解串器
| 型号： | FIN224AC_0611 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | uSerDes 22-Bit Bi-Directional Serializer/Deserializer |
| 文件： | 总23页 (文件大小：497K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Click here for this datasheet
translated into Korean!
November 2006
FIN224AC
µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer
Features
FIN224AC to FIN24AC Comparison
■ Industry smallest 22-bit Serializer/Deserializer pair
■ Up to 20% power reduction
■ Low power for minimum impact on battery life
■ Double wide CKP pulse on FIN224AC, Mode 3
– Multiple power-down modes
■ Rolled edge rate for deserializer outputs on
■ 100nA in standby mode, 5mA typical operating
FIN224AC, for single display applications
conditions
■ Same voltage range
■ Highly rolled LVCMOS edge rate option to meet
■ Same pinout and package
regulatory requirements
■ Cable reduction: 25:4 or greater
General Description
■ Differential signaling:
The FIN224AC µSerDes™ is a low-power Serializer/
Deserializer (SerDes) that can help minimize the cost
and power of transferring wide signal paths. Through the
use of serialization, the number of signals transferred
from one point to another can be significantly reduced.
Typical reduction is 4:1 to 6:1 for unidirectional paths.
For bidirectional operation, using half duplex for multiple
sources, it is possible to reach signal reduction close to
10:1. Through the use of differential signaling, shielding
and EMI filters can also be minimized, further reducing
the cost of serialization. The differential signaling is also
important for providing a noise-insensitive signal that can
withstand radio and electrical noise sources. Major
reduction in power consumption allows minimal impact
on battery life in ultra-portable applications. A unique
word boundary technique assures that the actual word
boundary is identified when the data is deserialized. This
guarantees that each word is correctly aligned at the
deserializer on a word-by-word basis through a unique
sequence of clock and data that is not repeated except
at the word boundary. It is possible to use a single PLL
for most applications including bi-directional operation.
––90dBm EMI when using CTL in lab conditions
–Minimized shielding
–Minimized EMI filter
–Minimum susceptibility to external interference
■ Up to 22 bits in either direction
■ Up to 26MHz parallel interface operation
■ Voltage translation from 1.65V to 3.6V
■ High ESD protection: > 15kV HBM
■ Parallel I/O power supply (VDDP) range, 1.65V - 3.6V
■ Can support Microcontroller or RGB pixel interface
Applications
■ Image sensors
■ Small displays
– LCD, cell phone, digital camera, portable gaming,
printer, PDA, video camera, automotive
Ordering Information
Package
Order Number
Number
Pb-Free
Package Description
FIN224ACGFX
BGA042
Yes
42-Ball Ultra Small Scale Ball Grid Array (USS-BGA),
JEDEC MO-195, 3.5mm Wide (Slow LVCMOS Edge Rate)
FIN224ACMLX
MLP040
Yes
40-Terminal Molded Leadless Package (MLP), Quad,
JEDEC MO-220, 6mm Square (Slow LVCMOS Edge Rate)
Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only.
TM
µSerDes is a trademark of Fairchild Semiconductor Corporation.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
Basic Concept
LVCMOS
22
LVCMOS
CTL
4
FIN224AC
Serializer
FIN224AC
Deserializer
22
Figure 1. Conceptual Diagram
Functional Block Diagram
+
-
CKS0+
Word
PLL
CKREF
0
I
Boundary
Generator
CKS0-
STROBE
cksint
Serializer
DP[21:22]
DP[1:20]
Control
DSO+/DSI-
DSO-/DSI+
+
-
Serializer
oe
100 Gated
Termination
+
-
Deserializer
Deserializer
Control
cksint
+
-
CKSI+
CKSI-
DP[23:24]
CKP
100
Termination
WORD CK
Generator
Control Logic
S1
DIRO
Freq
Direction
Control
S2
Control
oe
DIRI
Power Down
Control
Figure 2. Block Diagram
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
2
Terminal Description
Terminal
Number of
I/O Type Terminals
Name
DP[1:20]
DP[21:22]
DP[23:24]
CKREF
STROBE
CKP
Description of Signals
LVCMOS parallel I/O, Direction controlled by DIRI pin
LVCMOS parallel unidirectional inputs
I/O
20
2
I
O
2
LVCMOS unidirectional parallel outputs
IN
1
LVCMOS clock input and PLL reference
LVCMOS strobe signal for latching data into the serializer
LVCMOS word clock output
CTL differential serial I/O data signals(1)
DSO: Refers to output signal pair
DSI: Refers to input signal pair
IN
1
OUT
DIFF-I/O
1
DSO+ / DSI-
DSO- / DSI+
2
DSO(I)+: Positive signal of DSO(I) pair
DSO(I)-: Negative signal of DSO(I) pair
CKSI+
CKSI-
DIFF-IN
2
2
CTL differential deserializer input bit clock
CKSI: Refers to signal pair
CKSI+: Positive signal of CKSI pair
CKSI-: Negative signal of CKSI pair
CKSO+
CKSO-
DIFF-OUT
CTL differential serializer output bit clock
CKSO: Refers to signal pair
CKSO+: Positive signal of CKSO pair
CKSO-: Negative signal of CKSO pair
S1
S2
IN
IN
IN
1
1
1
LVCMOS mode selection terminals used to select frequency range for
the reflect, CKREF
DIRI
LVCMOS control input used to control direction of data flow:
DIRI = “1” Serializer
DIRI = “0” Deserializer
DIRO
VDDP
VDDS
VDDA
GND
OUT
1
1
1
1
2
LVCMOS control output inversion of DIRI
Power supply for parallel I/O and translation circuitry
Power supply for core and serial I/O
Supply
Supply
Supply
Supply
Power supply for analog PLL circuitry
For ground signals (2 for µBGA, 1 for MLP)
Notes:
1. The DSO/DSI serial port pins have been arranged such that if one device is rotated 180 degrees with respect to the
other device, the serial connections properly align without the need for any traces or cable signals to cross. Other
layout orientation may require that traces or cables cross.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
3
Connection Diagrams
1
2
3
4
5
6
7
8
9
10
DP[9]
DP[10]
DP[11]
DP[12]
VDDP
30 DIRO
29 CKSO+
28 CKSO-
27
DSO+
26 DSO-
25 CKSI-
24 CKSI+
23 DIRI
22 S2
CKP
DP[13]
DP[14]
DP[15]
DP[16]
21 VDDS
Figure 3. Terminal Assignments for µBGA
(Top View)
Pin Assignments
1
2
3
4
5
6
A
B
C
D
E
F
J
DP[9]
DP[11]
CKP
DP[7]
DP[5]
DP[6]
DP[8]
VDDP
GND
DP[3]
DP[2]
DP[4]
GND
DP[1]
CKREF
DIRO
DP[10]
DP[12]
DP[14]
DP[16]
DP[18]
DP[20]
STROBE
CKSO+
CKSO-
DP[13]
DP[15]
DP[17]
DP[19]
DSO-/DSI+ DSO+/DSI-
VDDS
VDDA
DP[23]
CKSI+
S2
CKSI-
DIRI
S1
DP[21]
DP[22]
DP[24]
Figure 4. Terminal Assignments for µBGA
(Top View)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
4
Turn-Around Functionality
Control Logic Circuitry
The device passes and inverts the DIRI signal through
the device asynchronously to the DIRO signal. Care
must be taken by the system designer to ensure that no
contention occurs between the deserializer outputs and
the other devices on this port. Optimally the peripheral
device driving the serializer should be put into a HIGH-
impedance state prior to the DIRI signal being asserted.
When a device with dedicated data outputs turns from a
deserializer to a serializer, the dedicated outputs remain
at the last logical value asserted. This value only
changes if the device is once again turned around into a
deserializer and the values are overwritten.
The FIN224AC has the ability to be used as a 22-bit seri-
alizer or a 22-bit deserializer. Pins S1 and S2 must be
set to accommodate the clock reference input frequency
range of the serializer. Table 1 shows the pin program-
ming of these options based on the S1 and S2 control
pins. The DIRI pin controls whether the device is a serial-
izer or a deserializer. When DIRI is asserted LOW, the
device is configured as a deserializer. When the DIRI pin
is asserted HIGH, the device is configured as a serial-
izer. Changing the state on the DIRI signal reverses the
direction of the I/O signals and generate the opposite
state signal on DIRO. For unidirectional operation the
DIRI pin should be hardwired to the HIGH or LOW state
and the DIRO pin should be left floating. For bi-direc-
tional operation, the DIRI of the master device is driven
by the system and the DIRO signal of the master is used
to drive the DIRI of the slave device.
Power-Down Mode: (Mode 0)
Mode 0 is used for powering down and resetting the
device. When both of the mode signals are driven to a
LOW state, the PLL and references are disabled, differ-
ential input buffers are shut off, differential output buffers
are placed into a HIGH-impedance state, LVCMOS out-
puts are placed into a HIGH-impedance state, and LVC-
MOS inputs are driven to a valid level internally.
Additionally all internal circuitry is reset. The loss of
CKREF state is also enabled to ensure that the PLL only
powers-up if there is a valid CKREF signal.
Serializer/Deserializer with Dedicated I/O Variation
The serialization and deserialization circuitry is set up for
24 bits. Because of the dedicated inputs and outputs,
only 22 bits of data are ever serialized or deserialized.
Regardless of the mode of operation, the serializer is
always sending 24 bits of data plus 2 boundary bits and
the deserializer is always receiving 24 bits of data and 2
word boundary bits. Bits 23 and 24 of the serializer
always contain the value of zero and are discarded by
the deserializer. DP[21:22] input to the serializer is dese-
rialized to DP[23:24] respectively.
In a typical application mode, signals of the device do not
change states other than between the desired frequency
range and the power-down mode. This allows for sys-
tem-level power-down functionality to be implemented
via a single wire for a SerDes pair. The S1 and S2 selec-
tion signals that have their operating mode driven to a
“logic 0” should be hardwired to GND. The S1 and S2
signals that have their operating mode driven to a “logic
1” should be connected to a system-level power-down or
reset signal.
Table 1. Control Logic Circuitry
Mode
Number
S2
S1
DIRI
Description
0
1
0
0
x
1
0
1
0
1
Power-Down Mode
0
1
22-Bit Serializer 2MHz to 5MHz CKREF
22-Bit Deserializer
0
1
2
3
1
0
22-Bit Serializer 5MHz to 15MHz CKREF
22-Bit Deserializer
1
0
1
1
22-Bit Serializer 10MHz to 26MHz CKREF (Divide by 2 Serial Data)
(Note: FIN224C required for RGB applications)
1
1
0
22-Bit Deserializer
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
5
Serializer Operation Mode
The serializer configurations are described in the following sections. The basic serialization circuitry works essentially
identically in these modes, but the actual data and clock streams differ depending on if CKREF is the same as the
STROBE signal or not. When it is stated that CKREF does not equal STROBE, each signal is distinct and CKREF
must be running at a frequency high enough to avoid any loss of data condition. CKREF must never be a lower fre-
quency than STROBE.
The PLL must receive a stable CKREF signal to achieve lock prior to any valid
data being sent. The CKREF signal can be used as the data STROBE signal
provided that data can be ignored during the PLL lock phase.
Serializer Operation: (Figure 5)
MODE 1 or MODE 2,
DIRI = 1,
Once the PLL is stable and locked, the device can begin to capture and serialize
data. Data is captured on the rising edge of the STROBE signal and then serial-
ized. The serialized data stream is synchronized and sent source synchronously
with a bit clock with an embedded word boundary. When operating in this mode,
the internal deserializer circuitry is disabled, including the serial clock, serial data
input buffers, the bi-directional parallel outputs, and the CKP word clock. The
CKP word clock is driven HIGH.
CKREF = STROBE
DPI[1:24] WORD n-1
CKREF/STROBE
WORD n
WORD n+1
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
b
B
5
DSO
24 25 26
1
2
3
4
22 23 24 25 26
1
2
3
4
CKS0
WORD n-2
WORD n-1
WORD n
Figure 5. Serializer Timing Diagram (CKREF = STROBE)
If the same signal is not used for CKREF and STROBE, the CKREF signal must
be run at a higher frequency than the STROBE rate to serialize the data cor-
rectly. The actual serial transfer rate remains at 13 times the CKREF frequency.
A data bit value of zero is sent when no valid data is present in the serial bit
stream. The operation of the serializer otherwise remains the same.
Serializer Operation: (Figure 6),
DIRI = 1,
CKREF does not = STROBE
The exact frequency that the reference clock needs to run at depends upon the
stability of the CKREF and STROBE signal. If the source of the CKREF signal
implements spread spectrum technology, the max frequency of the spread spec-
trum clock should be used in calculating the ratio of STROBE frequency to the
CKREF frequency. Similarly, if the STROBE signal has significant cycle-to-cycle
variation, the maximum cycle-to-cycle time needs to be factored into the selec-
tion of the CKREF frequency.
CKREF
DP[1:24]
STROBE
WORD n-1
WORD n
WORD n+1
DSO
b
b
b
b
b
b
b
b b b b b
22 23 24 25 26
b
b
b
2 3
1
2
3
4
5
6
7
1
CKS0
No Data
No Data
WORD n-1
WORD n
Figure 6. Serializer Timing Diagram (CKREF does not equal STROBE)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
6
Serializer Operation Mode (Continued)
When operating in mode 3, the effective serial speed is divided by two. This
mode has been implemented to accommodate cases where the reference clock
frequency is high compared to the actual strobe frequency. The actual strobe
frequency must be less than or equal to 50% of the CKREF frequency for this
mode to work properly. This mode, in all other ways, operates the same as
described in the section where CKREF does not equal STROBE.
Serializer Operation: (Figure 7),
MODE 3 (S1 = S2 = 1), DIRI = 1,
CKREF Divide by 2 mode
CKREF
DP[1:24]
WORD n-1
WORD n
WORD n+1
STROBE
DSO
b
b
b
b
b
b
b
b
b
b
b
22 23 24 25 26
b
b
b
b
3
1
2
3
4
5
6
7
1
2
CKS0
No Data
WORD n-1
WORD n
No Data
Figure 7. CKREF > 2x STROBE Frequency; Mode 3 Operation (S1 = S2 = 1)
A third method of serialization can be acheived by providing a free-running bit
clock on the CKSI signal. This mode is enabled by grounding the CKREF signal
and driving the DIRI signal HIGH. At power-up, the device is configured to accept
a serialization clock from CKSI. If a CKREF is received, this device enables the
CKREF serialization mode. The device remains in this mode even if CKREF is
stopped. To re-enable this mode, the device must be powered down and then
powered back up with a “logic 0” on CKREF.
Serializer Operation: (Figure 8),
DIRI = 1, No CKREF
CKSI
DP[1:24]
STROBE
WORD n-1
WORD n
WORD n+1
DSO
b
b
b
b
b
b
b
b b b b b
22 23 24 25 26
b
b
b
2 3
1
2
3
4
5
6
7
1
CKS0
WORD n-1
WORD n
No Data
No Data
Figure 8. Serializer Timing Diagram Using Provided Bit Clock (No CKREF)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
7
Deserializer Operation Mode
The operation of the deserializer is only dependent upon the data received on the DSI data signal pair and the CKSI
clock signal pair. The following two sections describe the operation of the deserializer under two distinct serializer
source conditions. References to the CKREF and STROBE signals refer to the signals associated with the serializer
device used in generating the serial data and clock signals that are inputs to the deserializer. When operating in this
mode, the internal serializer circuitry is disabled, including the parallel data input buffers. If there is a CKREF signal
provided, the CKSO serial clock continues to transmit bit clocks. Upon device power-up (S1 or S2 = 1), all deserializer
output data pins are driven LOW until valid data is passed through the deserializer.
When the DIRI signal is asserted LOW, the device is configured as a deserial-
izer. Data is captured on the serial port and deserialized through use of the bit
clock sent with the data. The word boundary is defined in the actual clock and
data signal. Parallel data is generated at the time the word boundary is defined
in the actual clock and data signal. Parallel data is generated at the time the
word boundary is detected. The falling edge of CKP occurs approximately six bit
times after the falling edge of CKSI. The rising edge of CKP goes HIGH approxi-
mately 13 bit times after CKP goes LOW. The rising edge of CKP is generated
approximately 13 bit times later. When no embedded word boundary occurs, no
pulse on CKP is generated and CKP remains HIGH.
Deserializer Operation: DIRI = 0
(Serializer Source:
CKREF = STROBE)
WORD n-1
WORD n
WORD n+1
b
b
b
25 26
bj bj+1
bj+13 bj+14
b
b b
25 26
0
0
0
0
DSI
24
24
CKSI
13 bit times
WORD n-1
CKPO
6 bit times
DP[1:24]
WORD n-2
WORD n
Figure 9. Deserializer Timing Diagram (Serializer Source: CKREF equals STROBE)
The logical operation of the deserializer remains the same if the CKREF is equal
in frequency to the STROBE or at a higher frequency than the STROBE. The
Deserializer Operation: DIRI = 0
(Serializer Source:
CKREF does not = STROBE)
actual serial data stream presented to the deserializer is different because it has
non-valid data bits sent between words. The duty cycle of CKP varies based on
the ratio of the frequency of the CKREF signal to the STROBE signal. The fre-
quency of the CKP signal is equal to the STROBE frequency. The falling edge of
CKP occurs six bit times after the data transition. The LOW time of the CKP sig-
nal is equal to 13 serial bit times. In modes 1 and 2, the CKP LOW time equals
half of the CKREF period of the serializer. In mode 3, the CKP LOW is equal to
the CKREF period. The CKP HIGH time is approximately equal to the STROBE
period, minus the CKP LOW time. Figure 10 is representative of a waveform that
could be seen when CKREF is not equal to STROBE. If CKREF was significantly
faster, additional non-valid data bits would occur between data words.
WORD n-1
WORD n
WORD n+1
DSI
b
b
b
25 26
b
b
b
b
b
b
b
b
b
b
25 26
b
b
2
24
1
6
7
8
9
19
20
24
1
CKSI
CKPO
DP[1:24]
WORD n-2
WORD n-1
WORD n
Figure 10. Deserializer Timing Diagram (Serializer Source: CKREF does not equal STROBE)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
8
LVCMOS Data I/O
The LVCMOS input buffers have a nominal threshold
value equal to half VDD. The input buffers are only oper-
ational when the device is operating as a serializer.
When the device is operating as a deserializer, the inputs
are gated off to conserve power.
tive greater sensitivity of the current sense receiver of
CTL allows it to work at much lower current drive and a
much lower voltage.
During power down mode, the differential inputs are dis-
abled and powered down and the differential outputs are
placed in a HIGH-Z state. CTL inputs have an inherent
failsafe capability that supports floating inputs. When the
CKSI input pair of the serializer is unused, it can reliably
be left floating. Alternately both of the inputs can be con-
nected to ground. CTL inputs should never be connected
to VDD. When the CKSO output of the deserializer is
unused, it should be allowed to float.
The LVCMOS 3-STATE output buffers are rated for a
source / sink current of approximately 0.5mA at 1.8V.
The outputs are active when the DIRI signal and either
S1 or S2 is asserted HIGH. When the DIRI signal and
either S1 or S2 is asserted LOW, the bi-directional LVC-
MOS I/Os is in a HIGH-Z state. Under purely capacitive
load conditions, the output swings between GND and
VDDP. When S1 or S2 initially transitions HIGH, the initial
state of the deserializer LVCMOS outputs is zero.
+
–
DS+
DS-
From
Serializer
Unused LVCMOS input buffers must be either tied off to
a valid logic LOW or a valid logic HIGH level to prevent
static current draw due to a floating input. Unused LVC-
MOS output should be left floating. Unused bi-directional
pins should be connected to GND through a high-value
resistor. If a FIN224AC device is configured as an unidi-
rectional serializer, unused data I/O can be treated as
unused inputs. If the FIN224AC is hardwired as a deseri-
alizer, unused data I/O can be treated as unused outputs.
From
Control
Gated
Termination
(DS Pins Only)
+
–
To
Deserializer
Figure 11. Bi-Directional Differential
I/O Circuitry
The FIN224AC family offers fast and slow LVCMOS
edge rates to meet emissions and loading requirements.
Phase-Locked Loop (PLL) Circuitry
Differential I/O Circuitry
The CKREF input signal is used to provide a reference to
the PLL. The PLL generates internal timing signals capa-
ble of transferring data at 13 times the incoming CKREF
signal. The output of the PLL is a bit clock that is used to
serialize the data. The bit clock is also sent source syn-
chronously with the serial data stream. There are two
ways to disable the PLL. The PLL can be disabled by
entering the Mode 0 state (S1 = S2 = 0). The PLL dis-
ables immediately upon detecting a LOW on both the S1
and S2 signals. When any of the other modes are
entered by asserting either S1 or S2 HIGH and by pro-
viding a CKREF signal, the PLL powers-up and goes
through a lock sequence. One must wait the specified
number of clock cycles prior to capturing valid data into
the parallel port.
The FIN224AC employs FSC proprietary Current Tran-
sistor Logic (CTL) Input / Output (I/O) technology. CTL is
a low-power, low-EMI differential swing I/O technology.
The CTL output driver generates a constant output
source and sink current. The CTL input receiver senses
the current difference and direction from the correspond-
ing output buffer to which it is connected. This differs
from LVDS, which uses a constant current source output,
but a voltage sense receiver. Like LVDS, an input source
termination resistor is required to properly terminate the
transmission line. The FIN224AC device incorporates an
internal termination resistor on the CKSI receiver and a
gated internal termination resistor on the DS input
receiver. The gated termination resistor ensures proper
termination regardless of direction of data flow. The rela-
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
9
Application Mode Diagrams
µSerDes Serializer
U20
µSerDes DeSerializer
U22
FIN224AC
FIN224AC
TP6
VDDP
A6
B5
PIXCLK_M
CKREF
STROBE
J6
F5
F6
S2
F6
F5
J6
DIRI
S2
S1
S1
TP5
GPIO_MODE
DIRI
C1
PIXCLK_S
CKP
J5
J4
J5
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
J4
LCD_ENABLE_S
J3
B5
A6
J3
STROBE
CKREF
F3
J2
J1
F3
J2
LCD_ENABLE_M
LCD_VSYNC_M
LCD_HSYNC_M
LCD17_M
B6
C1
LCD_VSYNC_S
LCD_HSYNC_S
LCD17_S
LCD16_S
LCD15_S
LCD14_S
LCD13_S
LCD12_S
LCD11_S
LCD10_S
LCD9_S
DIRO
CKP
B6
J1
DIRO
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
LCD16_M
LCD15_M
LCD14_M
D6
D5
D5
D6
LCD13_M
DSO+/DSI-
DSO-/DSI+
DSO-/DSI+
DSO+/DSI-
LCD12_M
LCD
Controller
Out
LCD11_M
C6
C5
E6
E5
LCD10_M
CKSO-
CKSO+
CKSI-
CKSI+
LCD
Display
In
LCD9_M
LCD8_M
LCD7_M
LCD6_M
LCD5_M
LCD4_M
LCD3_M
LCD2_M
LCD1_M
LCD0_M
LCD8_S
E6
E5
C6
C5
LCD7_S
DP8
CKSI-
CKSI+
CKSO-
CKSO+
DP8
LCD6_S
DP7
DP7
LCD5_S
DP6
DP6
2.8V
2.8V
LCD4_S
DP5
DP5
F4
E4
D3
1.8V
2.8V
F4
E4
D3
LCD3_S
DP4
VDDA
VDDS
VDDP
VDDA
VDDS
VDDP
DP4
LCD2_S
DP3
DP3
LCD1_S
DP2
DP2
LCD0_S
DP1
DP1
C12
.01µF
C10
1nF
C11
C6
1nF
C3
.01µF
2.2µF
Assumptions:
1) 18-bit Unidirectional RGB Application
2) Mode 2 Operation (5Mhz to 15Mhz CKREF)
3) VDDP= (1.65V to 3.6V)
Figure 12. FIN224AC RGB
µSerDes Serializer
µSerDes DeSerializer
U21
FIN224AC
U23
FIN224AC
TP2
VDDP
A6
REFCLK
CKREF
B5
LCD_/WRITE_ENABLE_M
STROBE
J6
S1
S2
F6
F5
J6
F5
F6
DIRI
S2
TP1
TP3
GPIO_MODE
DIRI
C1
LCD_/WRITE_ENABLE_S
S1
CKP
J5
J4
J5
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
DP24
DP23
DP22
DP21
DP20
DP19
DP18
DP17
DP16
DP15
DP14
DP13
DP12
DP11
DP10
DP9
J4
J3
B5
A6
J3
STROBE
CKREF
F3
J2
F3
J2
B6
C1
LCD_/CS_M
LCD_/CS_S
LCD_ADDRESS_S
LCD17_S
DIRO
CKP
J1
B6
J1
LCD_ADDRESS_M
LCD17_M
DIRO
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
F2
F1
E2
E1
D2
D1
C2
B1
B2
A1
C3
A2
B3
A3
C4
A4
B4
A5
LCD16_M
LCD16_S
LCD15_M
LCD15_S
LCD14_M
LCD14_S
D6
D5
D5
D6
LCD13_M
LCD13_S
DSO+/DSI-
DSO-/DSI+
DSO-/DSI+
DSO+/DSI-
LCD12_M
LCD12_S
LCD
Controller
Out
LCD11_M
LCD11_S
C6
C5
E6
E5
LCD10_M
LCD10_S
CKSO-
CKSO+
CKSI-
CKSI+
LCD
Display
LCD9_M
LCD8_M
LCD7_M
LCD6_M
LCD5_M
LCD4_M
LCD3_M
LCD2_M
LCD1_M
LCD0_M
LCD9_S
LCD8_S
E6
E5
C6
C5
LCD7_S
In
DP8
CKSI-
CKSI+
CKSO-
CKSO+
DP8
LCD6_S
DP7
DP7
LCD5_S
LCD4_S
LCD3_S
LCD2_S
LCD1_S
LCD0_S
DP6
DP6
2.8V
2.8V
DP5
DP5
1.8V
2.8V
F4
E4
D3
F4
E4
D3
DP4
VDDA
VDDS
VDDP
VDDA
VDDS
VDDP
DP4
DP3
DP3
DP2
DP2
DP1
DP1
C9
.01uµF
C7
1nF
C8
C5
1nF
C2
.01uµF
2.2uµF
Assumptions:
1) 18-bit Unidirectional µController Application
2) Mode 3 Operation (10 Mhz to 20Mhz CKREF)
3) VDDP= (1.65V to 3.6V)
4) REFCLK is a continously running clock with a frequency
greater than /WRITE_ENABLE.
Figure 13. FIN224AC Microcontroller
Flex Circuit Design Guidelines
The serial I/O information is transmitted at a high serial rate. Care must be taken implementing this serial I/O flex
cable. The following best practices should be used when developing the flex cabling or Flex PCB:
■ Keep all four differential wires the same length.
■ Allow no noisy signals over or near differential serial wires. Example: No LVCMOS traces over differential wires.
■ Use only one ground plane or wire over the differential serial wires. Do not run ground over top and bottom.
■ Do not place test points on differential serial wires.
■ Use differential serial wires a minimum of 2cm away from the antenna.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
10
Absolute Maximum Ratings
The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed.
The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics
tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines
the conditions for actual device operation.
Symbol
Parameter
Min.
-0.5
Max.
+4.6
+4.6
Unit
V
VDD
Supply Voltage
ALL input/Output Voltage
CTL Output Short Circuit Duration
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature
-0.5
V
Continuous
-65
TSTG
TJ
+150
+150
+260
°C
°C
°C
TL
Human Body Model, 1.5KΩ, 100pF
All Pins
>2
kV
kV
ESD
S1, S2, CKSO, CKSI, DSO, DSI, VDDA, VDDS, VDDP
(as specified in IEC61000-4-2)
>15
Recommended Operating Conditions
Symbol
Parameter
Min.
2.5
Max.
3.3
Unit
V
VDDA, VDDS Supply Voltage
VDDP
TA
Supply Voltage
Operating Temperature(2)
1.65
-30
3.60
+70
100
V
°C
VDDA-PP
Supply Noise Voltage
mVp-p
Notes:
2. Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired.
The datasheet specification should be met, without exception, to ensure that the system design is reliable over its
power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside
datasheet specifications.
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
11
DC Electrical Characteristics
Over-supply voltage and operating temperature ranges, unless otherwise specified.
Symbol
(3)
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
LVCMOS I/O
VIH
VIL
Input High Voltage
Input Low Voltage
Output High Voltage
0.65 x VDDP
GND
VDDP
0.35 x VDDP
V
V
I
I
OH = 2.0mA VDDP = 3.3±0.30
VDDP = 2.5±-0.20
0.75 x VDDP
VOH
VDDP = 1.8±0.18
Output Low Voltage
Input Current
OL = 2.0mA VDDP = 3.3±0.30
VDDP = 2.5±0.20
0.25 x VDDP
V
VOL
VDDP = 1.8±0.18
IIN
VIN = 0V to 3.6V
-5.0
5.0
µA
DIFFERENTIAL I/O
IODH Output HIGH source current VOS = 1.0V
-1.75
µA
µA
mA
µA
µA
IODL
Output LOW sink current
VOS = 1.0V
VOUT = 0V
0.950
Short-Circuit Output
Current
Driver Enabled
Driver Disabled
IOS
±5
±5
Disabled Output
Leakage Current
CKSO, DSO = 0V to VDDS
S2 = S1 = 0V
±1
IOZ
ITH
ITL
Differential Input Threshold See Figure 6 and Table 2
High Current
50
µA
µA
uA
Differential Input Threshold See Figure 6 and Table 2
Low Current
-50
±5
Disabled Input Leakage
Current
CKSI, DSI = 0V to VDDS
S2 = S1 = 0V
±1
IIZ
IIS
Short-Circuit Input Current Vout =VDDS
mA
V
Input Common Mode
Range
VDDS = 2.775 ±5%
0.5
VDDS-1
VICM
CKSI, DS Internal Receiver VID = 50mV, VIC = 925mV, DIRI = 0
Termination Resistor
100
Ω
RTRM
| CKSI+ – CKSI– | = VID
Notes:
3. Typical values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into the
device and negative values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless
otherwise specified (except ΔVOD and VOD).
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
12
Power Supply Currents
Symbol
Parameter
Test Conditions
Min. Typ.(4) Max. Unit
IDDA1
VDDA Serializer Static Supply Cur-
rent
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 1
450
550
4
µA
IDDA2
IDDS1
IDDS2
IDD_PD
VDDA Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 0
µA
VDDS Serializer Static Supply Cur-
rent
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 1
mA
mA
µA
VDDS Deserializer Static Supply
Current
All DP and Control Inputs at 0V or
NOCKREF, S2 = 0, S1 = 1, DIR = 0
4.5
0.1
VDD Power-Down Supply Current
IDD_PD = IDDA
S1 = S2 = 0 All Inputs at GND or VDD
IDD_SER1 26:1 Dynamic Serializer
Power Supply Current
CKREF = STROBE S2 = 0 2MHz
9
14
9
mA
DIRI = H
S1 = 1
5MHz
IDD_SER1 = IDDA+IDDS+IDDP
S2 = 1 5MHz
S1 = 0
15MHz
17
9
S2 = 1 10MHz
S1 = 1
26MHz
16
5
IDD_DES1 26:1 Dynamic Deserializer
Power Supply Current
CKREF = STROBE S2 = 0 2MHz
mA
mA
DIRI = L
S1 = 1
5MHz
6
IDD_DES1 = IDDA+IDDS+IDDP
S2 = 1 5MHz
S1 = 0
4
15MHz
5
S2 = 1 10MHz
S1 = 1
7
26MHz
11
8
IDD_SER2 26:1 Dynamic Serializer
Power Supply Current
NO CKREF
STROBE Active
CKSI = 15x STROBE
DIRI = H
2MHz
5MHz
8
IDD_SES2 = IDDA+IDDS+IDDP
10MHz
15MHz
10
12
Notes:
4. Typical values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into the
device and negative values refer to the current flowing out of the pins. Voltages are referenced to GROUND unless
otherwise specified (except ΔVOD and VOD).
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
13
AC Electrical Characteristics
Characteristics at recommended over-supply voltage and operating temperature ranges, unless otherwise specified.
(5)
Symbol
Parameter
Test Conditions
Min. Typ.
Max. Unit
Serializer Input Operating Conditions
CKREF = STROBE S2=0 S1=1
200
66
500
200
100.00
CKREF Clock Period
tTCP
See Figure 14
S2=1 S1=0
T
ns
(2MHz – 26MHz)
S2=1S1=1 38.46
CKREF Frequency Relative to
STROBE
CKREF does not = S2=0S1=1 2.25 x
fREF
MHz
STROBE
fSTROBE
tCPWH CKREF Clock High Time
0.2
0.5
0.5
T
T
tCPWL
tCLKT
tSPWH
CKREF Clock Low Time
0.2
LVCMOS Input Transition Time
STROBE Pulse Width HIGH/LOW
See Figure 16
See Figure 16
CKREF x 26
90.0
ns
(Tx4)/26
(Tx22)/26 ns
S2=0S1=1
S2=1S1=0
S2=1S1=1
52
130
260
130
390
676
fMAX
Maximum Serial Data Rate
Mb/s
tSTC
tHTC
DP(n) Setup to STROBE
DP(n) Hold to STROBE
DIRI = 1
2.5
2.0
ns
ns
Serializer AC Electrical Characteristics
Transmitter Clock Input to Clock
Output Delay
CKREF = STROBE
tTCCD
33a+1.5
-50.0
35a+6.5
250.0
ns
ps
tSPOS
CKSO Position Relative to DS(6)
PLL AC Electrical Characteristics
Serializer Phase Lock Loop
tTPLLS0
See Figure 18
200
µs
Stabilization Time
tTPLLD0 PLL Disable Time Loss of Clock
tTPLLD1 PLL Power-Down Time(7)
See Figure 21
See Figure 22
30.0
20.0
µs
ns
Deserializer Input Operating Conditions
Serial Port Setup Time,
tS_DS
1.4
ns
ps
DS-to-CKSI(8)
Serial Port Hold Time,
tH_DS
-250
DS-to-CKS(8)
Deserializer AC Electrical Characteristics
Deserializer Clock Output
tRCOP
See Figure 17
See Figure 17
50.0
T
500.0
ns
(CKP OUT) Period(9)
tRCOL
tRCOH
CKP OUT Low Time
CKP OUT High Time
13a-3
13a-3
13a+3
13a+3
ns
ns
(Rising Edge STROBE)(9) Serial-
izer source STROBE = CKREF
Data Valid to CKP LOW
See Figure 17
(Rising Edge STROBE)
tPDV
8a-6
8a+1
ns
ns
ns
CL = 8pF
See Figure 14
tROLH
(FIN224AC)
Output Rise Time (20% to 80%)
Output Fall Time (20% to 80%)
18
18
CL = 8pF
See Figure 14
tROHL
(FIN224AC)
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
14
Notes:
5. Typical values are given for VDD = 2.775V and TA = 25°C. Positive current values refer to the current flowing into
device and negative values means current flowing out of the pins. Voltages are referenced to GROUND unless
otherwise specified (except DVOD and VOD).
6. Skew is measured from either the rising or falling edge of CKSO clock to the rising or falling edge of data (DSO).
Signals are edge aligned. Both outputs should have identical load conditions for this test to be valid.
7. The power-down time is a function of the CKREF frequency prior to CKREF being stopped HIGH or LOW and the
state of the S1/S2 mode pins. The specific number of clock cycles required for the PLL to be disabled varies
dependent upon the operating mode of the device.
8. Signals are transmitted from the serializer source synchronously. Note that, in some cases, data is transmitted when
the clock remains at a HIGH state. Skew should only be measured when data and clock are transitioning at the same
time. Total measured input skew would be a combination of output skew from the serializer, load variations, and ISI
and jitter effects.
9. (a = (1/f)/13) Rising edge of CKP appears approximately 13 bit times after the falling edge of the CKP output. Falling
edge of CKP occurs approximately eight bit times after a data transition or six bit times after the falling edge of
CKSO. Variation of the data with respect to the CKP signal is due to internal propagation delay differences of the
data and CKP path and propagation delay differences on the various data pins. Note that if the CKREF is not equal
to STROBE for the serializer, the CKP signal does not maintain a 50% duty cycle.The low time of CKP remains 13
bit times.
Control Logic Timing Controls
Symbol
tPHL_DIR
tPLH_DIR
Parameter
Test Conditions
Min. Typ. Max. Units
,
Propagation Delay
DIRI-to-DIRO
DIRI LOW-to-HIGH or HIGH-to-LOW
17.0
25.0
25.0
25.0
2.0
ns
ns
ns
ns
µs
ns
ns
tPLZ, tPHZ Propagation Delay
DIRI LOW-to-HIGH
DIRI HIGH-to-LOW
DIRI-to-DP
tPZL, tPZH Propagation Delay
DIRI-to-DP
tPLZ, tPHZ Deserializer Disable Time: DIRI = 0,
S0 or S1 to DP
S1(2) = 0 and S2(1) = LOW-to-HIGH Figure 23
t
PZL, tPZH Deserializer Enable Time: DIRI = 0,(10)
S0 or S1 to DP
S1(2) = 0 and S2(1) = LOW-to-HIGH Figure 23
tPLZ, tPHZ Serializer Disable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
25.0
65.0
S1(2) = 0 and S2(1) = HIGH-to-LOW Figure 22
tPZL, tPZH Serializer Enable Time:
S0 or S1 to CKSO, DS
DIRI = 1,
S1(2) and S2(1) = LOW-to-HIGH Figure 22
Notes:
10. Deserializer Enable Time includes the time required for internal voltage and current references to stabilize. This time
is significantly less than the PLL Lock Time and therefore does not limit overall system startup time.
Capacitance
Symbol
CIN
Parameter
Capacitance of Input Only Signals, DIRI = 1, S1 = S2 = 0,
CKREF, STROBE, S1, S2, DIRI VDD = 2.5V
Capacitance of Parallel Port Pins DIRI = 1, S1 = S2 = 0,
DP1:12 VDD = 2.5V
Capacitance of Differential I/O Sig- DIRI = 0, S1 = S2 = 0,
Test Conditions
Min. Typ. Max. Units
2.0
2.0
2.0
pF
pF
pF
CIO
CIO-DIFF
nals
VDD = 2.775V
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
15
AC Loading and Waveforms
Setup Time
t
STC
STROBE
DP[1:12]
t
t
ROHL
ROLH
80%
80%
Data
20%
20%
DPn
t
Hold Time
HTC
DPn
STROBE
DP[1:12]
Data
8pF
Setup: MODE0 = “0” or “1”, MODE1 = “1”, SER/DES = “1”
Figure 14. LVCMOS Output Load
and Transition Times
Figure 15. Serial Setup and Hold Time
Data Time
t
PDV
t
t
CLKT
CLKT
90%
90%
CKP
Data
DP[1:12]
10%
10%
t
RCOP
t
TCP
75%
50%
25%
50%
CKREF
V
IH
CKREF
50%
50%
V
IL
t
t
RCOL
RCOH
t
t
CPWL
CPWH
EN_DES = “1”, CKSI and DSI are valid signals
Setup:
Figure 16. LVCMOS Clock Parameters
Figure 17. Deserializer Data Valid Window
Time and Clock Output Parameters
t
TPLS0
V
/V
DD DDA
t
TCCD
S1 or S2
STROBE
V
DD/2
CKREF
CKS0
CKS0-
CKS0+
V
= 0
DIFF
Note: STROBE = CKREF
Note: CKREF Signal is free running.
Figure 18. Serializer PLL Lock Time
Figure 19. Serializer Clock Propagation Delay
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
16
AC Loading and Waveforms (Continued)
t
TPPLD0
CKREF
CKS0
t
RCCD
CKSI-
CKSI+
V
= 0
DIFF
CKP
V
Note: CKREF Signal can be stopped either High or LOW
DD/2
Figure 20. Deserializer Clock Propagation Delay
Figure 21. PLL Loss of Clock Disable Time
t
t
PZL(ZH)
PLZ(HZ)
S1 or S2
t
TPPLD1
DS+,CKS0+
DS+,CKS0-
S1 or S2
CKS0
HIGHZ
Note: CKREF must be active and PLL must be stable
Figure 22. PLL Power-Down Time
Figure 23. Serializer Enable and Disable Time
t
t
PLZ(HZ)
PZL(ZH)
S1 or S2
DP
Note: If S1(2) transitioning then S2(1) must = 0 for test to be valid
Figure 24. Deserializer Enable and Disable Times
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
17
Tape and Reel Specification
BGA Embossed Tape Dimension
Dimensions are in millimeters.
D
P
0
P
2
T
E
F
K
0
W
W
c
B
0
Tc
A
0
D
1
P
1
User Direction of Feed
Package
A0
B0
D
D1
E
F
K0
1.1
P1
8.0
P0
P2
T
TC
W
WC
3.5 x 4.5 TBD TBD 1.55
1.5
1.75
5.5
4.0
2.0
0.3
0.07
12.0 9.3
±0.1 ±0.1 ±0.05 Min. ±0.1 ±0.1 ±0.1 Typ. Typ. ±0/05 Typ. ±0.005 ±0.3 Typ.
Notes:
A0, B0, and K0 dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement
requirements (see sketches A, B, and C).
Shipping Reel Dimensions
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
18
Dimensions are in millimeters.
1.0mm
maximum
10° maximum
Typical component
cavity center line
1.0mm
maximum
B0
Typical component
center line
10° maximum component rotation
Sketch A (Side or Front Sectional View)
Sketch C (Top View)
A0
Component Rotation
Component lateral movement
Sketch B (Top View)
Component Rotation
W1 Measured at Hub
W2 max Measured at Hub
B Min
Dia C
Dia D
min
Dia A
max
Dia N
DETAIL AA
See detail AA
W3
Tape
Dim W3
Width
Dia A
Dim B
Dia C
Dia D
Dim N
Dim W1
Dim W2
14.4 Max.
18.4 Max.
22.4 Max.
(LSL–USL)
8
7.9 ~ 10.4
11.9 ~ 15.4
15.9 ~ 19.4
13.0
+0.5/–0.2
8.4
+2.0/–0
12
330 Max.
1.5 Min.
20.2 Min.
178 Min.
16
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
19
Tape and Reel Specification (Continued)
MLP Embossed Tape Dimension
Dimensions are in millimeters.
D
P
0
P
2
T
E
F
K
0
W
W
c
B
0
Tc
A
0
D
1
P
1
User Direction of Feed
Package
A0
B0
D
D1
E
F
K0
P1
P0
P2
T
TC
W
WC
5 x 5
5.35 5.35
±0.1 ±0.1
1.55
1.5
1.75
5.5
1.4
2.0
0.3
0.07
12
9.3
8 Typ. 4 Typ.
±0.05 Min. ±0.1 ±0.1 ±0.1
±0.05 Typ. ±0.005 ±0.3 Typ.
6 x 6
6.30 6.30
±0.1 ±0.1
Notes:
Ao, Bo, and Ko dimensions are determined with respect to the EIA/JEDEC RS-481 rotational and lateral movement
requirements (see sketches A, B, and C).
Shipping Reel Dimension
Dimensions are in millimeters.
1.0mm
maximum
10° maximum
Typical component
cavity center line
1.0mm
maximum
B0
Typical component
center line
10°maximum component rotation
Sketch A (Side or Front Sectional View)
Sketch C (Top View)
A0
Sketch B (Top View)
Component Rotation
Component lateral movement
Component Rotation
W1 Measured at Hub
W2 max Measured at Hub
B Min
Dia C
Dia D
min
Dia A
max
Dia N
DETAIL AA
See detail AA
W3
Tape
Dim W3
Width
Dia A
Dim B
Dia C
Dia D
Dim N
Dim W1
Dim W2
14.4 Max.
18.4 Max.
22.4 Max.
(LSL–USL)
8
7.9 ~ 10.4
11.9 ~ 15.4
15.9 ~ 19.4
13.0
+0.5/–0.2
8.4
+2.0/–0
12
330 Max.
1.5 Min.
20.2 Min.
178 Min.
16
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
20
Physical Dimensions
Dimensions are in millimeters unless otherwise noted.
2X
0.10
C
3.50
2X
(0.35)
(0.5)
0.10
C
(0.6)
2.5
(0.75)
TERMINAL
A1 CORNER
INDEX AREA
4.50
3.0
0.5
0.5
Ø0.3±0.05
X42
BOTTOM VIEW
0.15
C
C
A B
0.05
0.89±0.082
0.45±0.05
(QA CONTROL VALUE)
1.00 MAX
0.21±0.04
0.10
C
0.08
C
+0.1
0.2
C
0.23±0.05
-0.0
SEATING PLANE
LAND PATTERN
RECOMMENDATION
Figure 25. Pb-Free 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
21
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
(DATUM A)
Figure 26. Pb-Free 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
22
© 2006 Fairchild Semiconductor Corporation
FIN224AC Rev.1.1.2
www.fairchildsemi.com
23
相关型号：
FIN24A
Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
FAIRCHILD
FIN24AGFX
Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
FAIRCHILD
FIN24AMLX
Low Voltage 24-Bit Bi-Directional Serializer/Deserializer with Multiple Frequency Ranges (Preliminary)
FAIRCHILD
©2020 ICPDF网 联系我们和版权申明