RF1K4921196 [FAIRCHILD]
TRANSISTOR | MOSFET | N-CHANNEL | 12V V(BR)DSS | 7A I(D) | SO ; 晶体管| MOSFET | N沟道| 12V V（ BR ） DSS | 7A I（ D） | SO
| 型号： | RF1K4921196 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | TRANSISTOR | MOSFET | N-CHANNEL | 12V V(BR)DSS | 7A I(D) | SO
|
| 文件： | 总8页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF1K49211
Data Sheet
January 2002
7A, 12V, 0.020 Ohm, Logic Level, Single
N-Channel LittleFET™ Power MOSFET
Features
• 7A, 12V
• r = 0.020Ω
The RF1K49211 Single N-Channel power MOSFET is
manufactured using an advanced MegaFET process. This
process, which uses feature sizes approaching those of LSI
integrated circuits, gives optimum utilization of silicon,
resulting in outstanding performance. It was designed for
use in applications such as switching regulators, switching
converters, motor drivers, relay drivers, and low-voltage bus
switches. This product achieves full-rated conduction at a
gate bias in the 3V - 5V range, thereby facilitating true on-off
power control directly from logic level (5V) integrated circuits.
DS(ON)
®
• Temperature Compensating PSPICE Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Formerly developmental type TA49211.
Ordering Information
NC(1)
DRAIN(8)
DRAIN(7)
PART NUMBER
PACKAGE
BRAND
RF1K49211
RF1K49211
MS-012AA
SOURCE(2)
NOTE: When ordering, use the entire part number. For ordering in
tape and reel, add the suffix 96 to the part number, i.e., RF1K4921196.
SOURCE(3)
GATE(4)
DRAIN(6)
DRAIN(5)
Packaging
JEDEC MS-012AA
BRANDING DASH
5
1
2
3
4
©2002 Fairchild Semiconductor Corporation
RF1K49211 Rev. B
RF1K49211
o
Absolute Maximum Ratings
T = 25 C Unless Otherwise Specified
A
RF1K49211
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
12
12
V
V
V
DSS
Drain to Gate Voltage (Rgs = 20KΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
±10
GS
Drain Current
Continuous (Pulse Width = 1s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
7
A
D
Pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
Refer to Peak Current Curve
DM
Pulsed Avalanche Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
Refer to UIS Curve
AS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
2
W
D
o
o
Derate Above 25 C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0.016
W/ C
o
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T , T
J
-55 to 150
C
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
o
300
260
C
C
L
o
pkg
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied
NOTE:
o
o
1. T = 25 C to 125 C.
J
o
Electrical Specifications
T = 25 C, Unless Otherwise Specified
A
PARAMETER
SYMBOL
BV
TEST CONDITIONS
= 250µA, V = 0V, (Figure 13)
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
Gate to Source Threshold Voltage
Zero Gate Voltage Drain Current
I
12
1
-
-
-
-
2
DSS
D
GS
V
V
= V , I = 250µA, (Figure 12)
V
GS(TH)
GS
DS D
o
I
V
V
= 12V,
= 0V
T
T
= 25 C
-
1
µA
µA
nA
Ω
DSS
GSS
DS
GS
A
A
o
= 150 C
-
-
50
100
0.020
250
-
Gate to Source Leakage Current
Drain to Source On Resistance
Turn-On Time
I
V
= ±10V
-
-
GS
r
I
= 7A, V
= 5V, (Figures 9, 11)
7A,
D
-
-
DS(ON)
D
GS
t
V
R
R
= 6V, I
-
-
ns
ON
DD
= 0.86Ω, V
= 5V,
L
GS
Turn-On Delay Time
Rise Time
t
-
50
150
120
160
-
ns
d(ON)
= 25Ω
GS
t
-
-
ns
r
Turn-Off Delay Time
Fall Time
t
-
-
ns
d(OFF)
t
-
-
ns
f
Turn-Off Time
t
-
350
75
45
2.5
ns
OFF
Total Gate Charge
Gate Charge at 5V
Threshold Gate Charge
Q
V
V
V
= 0V to 10V
= 0V to 5V
= 0V to 1V
V
= 9.6V,
7A,
= 1.37Ω
-
60
35
2
nC
nC
nC
g(TOT)
GS
GS
GS
DD
I
D
Q
-
g(5)
R
L
I
= 1.0mA
Q
g(REF)
(Figure15)
-
g(TH)
Input Capacitance
C
V
= 12V, V = 0V,
GS
-
-
-
-
1850
1600
600
-
-
pF
pF
pF
ISS
OSS
RSS
DS
f = 1MHz
(Figure 14)
Output Capacitance
C
C
-
-
Reverse Transfer Capacitance
o
Thermal Resistance Junction to Ambient
R
Pulse Width = 1s
62.5
C/W
θJA
Device mounted on FR-4 material
Source to Drain Diode Specifications
PARAMETERS
Source to Drain Diode Voltage
Reverse Recovery Time
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
1.25
95
UNITS
V
V
I
I
= 7A
-
-
-
-
SD
SD
t
= 7A, dI /dt = 100A/µs
SD
ns
rr
SD
©2002 Fairchild Semiconductor Corporation
RF1K49211 Rev. B
RF1K49211
Typical Performance Curves
1.2
1.0
0.8
8
6
4
0.6
0.4
2
0
0.2
0
75
100
125
150
0
25
50
75
100
125
150
25
50
o
o
T , AMBIENT TEMPERATURE ( C)
T , AMBIENT TEMPERATURE ( C)
A
A
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
10
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
1
0.02
0.01
P
DM
0.1
t
1
t
0.01
2
NOTES:
DUTY FACTOR: D = t /t
1
2
PEAK T = P
J
x Z
x R
+ T
JA A
SINGLE PULSE
0.001
DM
JA
θ
θ
-5
10
-4
-3
-2
10
-1
10
0
1
2
3
10
10
10
t , RECTANGULAR PULSE DURATION (s)
10
10
10
1
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
100
10
300
T
= MAX RATED
o
J
FOR TEMPERATURES
= 25 C
T
A
o
o
T
= 25 C
ABOVE 25 C DERATE PEAK
A
CURRENT AS FOLLOWS:
100
150 - T
A
I = I
25
5ms
10ms
V
= 5V
125
GS
1
0.1
100ms
10
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
1s
DC
OPERATION IN THIS
AREA MAY BE
V
= 12V
LIMITED BY r
DSS(MAX)
DS(ON)
0.01
1
10
-5
-4
-3
-2
10
-1
0
1
0.1
1
10
50
10
10
10
10
10
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
t, PULSE WIDTH (s)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. PEAK CURRENT CAPABILITY
©2002 Fairchild Semiconductor Corporation
RF1K49211 Rev. B
RF1K49211
Typical Performance Curves (Continued)
50
40
30
20
10
50
PULSE DURATION = 80µs
V
= 10V
= 5V
GS
DUTY CYCLE = 0.5% MAX
o
T
= 25 C
V
A
GS
V
= 4V
GS
o
STARTING T = 25 C
J
10
V
= 3V
GS
o
STARTING T = 150 C
J
If R = 0
= (L)(I )/(1.3*RATED BV
V
= 2.5V
GS
t
- V
)
DD
AV
If R ≠ 0
= (L/R)ln[(I *R)/(1.3*RATED BV
AS
DSS
t
- V ) +1]
DD
AV
AS
0.1
DSS
0
1
0
1
2
3
4
5
0.01
1
10
100
t
, TIME IN AVALANCHE (ms)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
AV
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
50
200
150
100
50
V
= 10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DD
o
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
25 C
I
I
I
I
= 15A
D
D
D
D
V
= 10V
DD
40
30
= 7.0A
= 3.5A
= 1.75A
o
-55 C
o
150 C
20
10
0
0
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
V
, GATE TO SOURCE VOLTAGE (V)
V
GS
, GATE TO SOURCE VOLTAGE (V)
GS
FIGURE 8. TRANSFER CHARACTERISTICS
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
350
300
250
200
150
100
50
2.0
V
= 6V, I = 7A, R = 0.86Ω
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
DD
D
L
t
f
V
= 5V, I = 7A
GS
D
t
r
1.5
1.0
0.5
0.0
t
d(OFF)
t
d(ON)
0
0
10
20
30
40
50
-80
-40
0
40
80
120
160
o
R
, GATE TO SOURCE RESISTANCE (Ω)
T , JUNCTION TEMPERATURE ( C)
GS
J
FIGURE 10. SWITCHING TIME vs GATE TO SOURCE
RESISTANCE
FIGURE 11. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
RF1K49211 Rev. B
RF1K49211
Typical Performance Curves (Continued)
1.2
1.2
1.1
1.0
0.9
0.8
V
= V , I = 250µA
I = 250µA
D
GS
DS
D
1.0
0.8
0.6
-80
-40
0
40
80
120
160
-80
-40
0
40
80
120
160
o
o
T , JUNCTION TEMPERATURE ( C)
T , JUNCTION TEMPERATURE ( C)
J
J
FIGURE 12. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 13. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
12
9
5.00
3.75
2.50
3500
V
= 0V, f = 1MHz
GS
ISS
C
C
C
C
= C
+ C
OSS
GS GD
V
= BV
DSS
V
= BV
DSS
DD
DD
3000
2500
2000
1500
1000
500
= C
RSS
OSS
GD
= C
+ C
GD
DS
C
ISS
R
= 1.71Ω
L
I
= 0.75mA
G(REF)
6
V
= 5V
GS
PLATEAU VOLTAGES IN
DESCENDING ORDER:
1.25
0
3
V
V
V
V
= BV
C
DD
DD
DD
DD
DSS
RSS
= 0.75 BV
= 0.50 BV
= 0.25 BV
DSS
DSS
DSS
0
0
I
I
G(REF)
G(REF)
0
2
4
6
8
10
12
t, TIME (µs)
20---------------------
80---------------------
I
I
G(ACT)
G(ACT)
V
, DRAIN TO SOURCE VOLTAGE (V)
DS
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 15. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
FIGURE 14. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Test Circuits and Waveforms
V
DS
BV
DSS
L
t
P
V
DS
I
VARY t TO OBTAIN
P
AS
+
-
V
DD
R
REQUIRED PEAK I
G
AS
V
DD
V
GS
DUT
t
P
I
AS
0V
0
0.01Ω
t
AV
FIGURE 16. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 17. UNCLAMPED ENERGY WAVEFORMS
©2002 Fairchild Semiconductor Corporation
RF1K49211 Rev. B
RF1K49211
Test Circuits and Waveforms (Continued)
t
t
ON
OFF
t
d(OFF)
V
DS
t
d(ON)
t
t
f
r
V
DS
R
L
90%
V
90%
GS
+
V
DD
10%
10%
-
0
0
DUT
R
GS
90%
50%
V
GS
50%
V
GS
PULSE WIDTH
10%
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
FIGURE 18. SWITCHING TIME TEST CIRCUIT
V
DS
V
Q
R
DD
g(TOT)
L
V
DS
V
= 10V
GS
V
GS
Q
+
-
g(5)
V
DD
V
= 5V
V
GS
GS
DUT
V
= 1V
GS
I
0
G(REF)
Q
g(TH)
I
G(REF)
0
FIGURE 20. GATE CHARGE TEST CIRCUIT
FIGURE 21. GATE CHARGE WAVEFORMS
Soldering Precautions
o
The soldering process creates a considerable thermal stress
on any semiconductor component. The melting temperature
of solder is higher than the maximum rated temperature of
the device. The amount of time the device is heated to a high
temperature should be minimized to assure device reliability.
Therefore, the following precautions should always be
observed in order to minimize the thermal stress to which the
devices are subjected.
3. Themaximumtemperaturegradientshouldbelessthan5 C
per second when changing from preheating to soldering.
4. The peak temperature in the soldering process should be
o
at least 30 C higher than the melting point of the solder
chosen.
5. The maximum soldering temperature and time must not
o
exceed 260 C for 10 seconds on the leads and case of
the device.
6. After soldering is complete, the device should be allowed
to cool naturally for at least three minutes, as forced cool-
ing will increase the temperature gradient and may result
in latent failure due to mechanical stress.
1. Always preheat the device.
2. The deltatemperature between the preheatandsoldering
o
should always be less than 100 C. Failure to preheat the
device can result in excessive thermal stress which can
damage the device.
7. During cooling, mechanical stress or shock should be
avoided.
©2002 Fairchild Semiconductor Corporation
RF1K49211 Rev. B
RF1K49211
PSPICE Electrical Model
SUBCKT RF1K49211 2 1 3 ;rev 6/26/96
LDRAIN
DPLCAP
10
DRAIN
2
5
CA 12 8 2.11e-9
CB 15 14 2.99e-9
CIN 6 8 1.30e-9
RLDRAIN
RSLC1
51
DBREAK
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
+
RSLC2
5
51
ESLC
11
-
50
EBREAK 11 7 17 18 15.81
EDS 14 8 5 8 1
EGS 13 8 6 8 1
+
-
17
18
-
DBODY
RDRAIN
6
8
EBREAK
ESG
ESG 6 10 6 8 1
EVTHRES
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
+
16
21
+
-
19
8
MWEAK
LGATE
EVTEMP
+
RGATE
GATE
1
IT 8 17 1
6
-
18
22
MMED
9
20
LDRAIN 2 5 1e-9
LGATE 1 9 1.04e-9
LSOURCE 3 7 2.37e-10
MSTRO
8
RLGATE
LSOURCE
CIN
SOURCE
3
7
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RSOURCE
RLSOURCE
S1A
S2A
RBREAK
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 3.50e-3
RGATE 9 20 1.57
12
15
13
8
14
13
17
18
RVTEMP
19
-
RLDRAIN 2 5 10
RLGATE 1 9 10.4
RLSOURCE 3 7 2.37
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 11.42e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1B
S2B
13
CB
CA
IT
14
+
+
VBAT
6
8
5
8
EGS
EDS
+
-
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*170),3))}
.MODEL DBODYMOD D (IS = 1.36e-12 RS = 1.65e-2 TRS1 = 3.88e-3 TRS2 = -5.45e-6 CJO = 2.95e-9 TT = 2.70e-8 M = 0.43)
.MODEL DBREAKMOD D (RS = 2.75e- 3TRS1 = -5.01e- 4TRS2 = -1.60e-4)
.MODEL DPLCAPMOD D (CJO = 2.40e-9 IS = 1e-30 N = 10 M = 0.55)
.MODEL MMEDMOD NMOS (VTO = 1.6 2KP = 1.5 IS = 1e-3 0N = 1 0TOX = 1L = 1 uW = 1u RG = 1.57)
.MODEL MSTROMOD NMOS (VTO = 2.0 8KP = 98.0 IS = 1e-3 0N = 1 0TOX = 1L = 1 uW = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.40 2KP = 0.06 7IS = 1e-3 0N = 1 0TOX = 1L = 1 uW = 1u RG = 15.7 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 8.51e- 4TC2 = 7.88e-7)
.MODEL RDRAINMOD RES (TC1 = 1.55e- 2TC2 = 5.78e-5)
.MODEL RSLCMOD RES (TC1 =1.02e-4 TC2 = 1.07e-6)
.MODEL RSOURCEMOD RES (TC1 = 0TC2 = 0)
.MODEL RVTHRESMOD RES (TC1 = -2.20e- 3TC2 = -7.29e-6)
.MODEL RVTEMPMOD RES (TC1 = -5.10e- 4TC2 = 8.07e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.1 VOFF = -1.1)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.1 VOFF = -4.1)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF = 2.5)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.5 VOFF = -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
©2002 Fairchild Semiconductor Corporation
RF1K49211 Rev. B
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reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Obsolete
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4
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