MB15E06PV1 [FUJITSU]
Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler; 单串行输入锁相环频率合成片2.5 GHz的预分频器
| 型号： | MB15E06PV1 |
| 厂家： | 
FUJITSU |
| 描述： | Single Serial Input PLL Frequency Synthesizer On-Chip 2.5 GHz Prescaler |
| 文件： | 总23页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21336-2E
ASSP
Single Serial Input
PLL Frequency Synthesizer
On-Chip 2.5 GHz Prescaler
MB15E06
■ DESCRIPTION
The Fujitsu MB15E06 is serial input Phase Locked Loop (PLL) frequency synthesizers with a 2.5 GHz prescaler. A
64/65 or a 128/129 can be selected for the prescaler that enables pulse swallow operation.
The latest BiCMOS process technology is used, resuItantly a supply current is limited as low as 8 mA typ. This op-
erates with a supply voltage of 3.0 V (typ.) .
Furthermore, a super charger circuit is included to get a fast tuning as well as low noise performance. As a result of
this, MB15E06 is ideally suitable for digital mobile communications, such as GPS (Global Positioning System) ,
Wireless LAN, CATV (CAble TeleVision) etc.
■ FEATURES
• High frequency operation : 2.5 GHz max
• Low power supply voltage : VCC = 2.7 to 3.6 V
• Very Low power supply current : ICC = 8.0 mA typ. (VCC = 3 V)
• Power saving function : IPS = 10 µA max.
• Pulse swallow function : 64/65 or 128/129
• Serial input 14-bit programmable reference divider : R = 5 to 16, 383
• Serial input 18-bit programmable divider consisting of:
- Binary 7-bit swallow counter : 0 to 127
- Binary 11-bit programmable counter : 5 to 2, 047
• Wide operating temperature : Ta = −40 to 85 °C
• Plastic 16-pin SSOP package (FPT-16P-M05)
■ PACKAGE
16-pin plastic SSOP
16-pad plastic BCC
(FPT-16P-M05)
(LCC-16P-M06)
MB15E06
■ PIN ASSIGNMENT
(TOP VIEW)
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
OSCIN
OSCOUT
VP
φR
OSCIN φR
φP
1
2
3
4
5
6
16 15 14
OSCOUT
VP
φP
LD/fout
ZC
13
12
11
10
LD/fout
ZC
VCC
VCC
PS
DO
DO
PS
LE
GND
Xfin
GND
Xfin
LE
7
8
9
Data
Data
Clock
fin Clock
fin
(FPT-16P-M05)
(LCC-16P-M06)
2
MB15E06
■ PIN DESCRIPTIONS
Pin No.
Pin Name
I/O
I
Descriptions
Programmable reference divider input.
1 (16)
OSCIN
Oscillator input connection to a TCXO.
2 (1)
3 (2)
4 (3)
OSCOUT
VP
O
Oscillator output.
Power supply voltage input for the charge pump.
Power supply voltage input.
VCC
Charge pump output.
Phase of the charge pump can be reversed by FC input.
5 (4)
DO
O
6 (5)
7 (6)
GND
Xfin
Ground.
I
I
Prescaler complementary input, and should be grounded via a capacitor.
Prescaler input.
8 (7)
fin
Connection with an external VCO should be done with AC coupling.
Clock input for the 19-bit shift register.
Data is shifted into the shift register on the rising edge of the clock. (Open is
prohibited.)
9 (8)
Clock
I
I
Serial data input using binary code.
The last bit of the data is a control bit. (Open is prohibited.)
Control bit = “H” ; Data is transmitted to the programmable reference
counter.
10 (9)
Data
Control bit = “L” ; Data is transmitted to the programmable counter.
Load enable signal input (Open is prohibited.)
11 (10)
12 (11)
LE
PS
I
I
When LE is high, the data in the shift register is transferred to a latch,
according to the control bit in the serial data.
Power saving mode control. This pin must be set at “L” at Power-ON.
(Open is prohibited.)
PS = “H” ; Normal mode
PS = “L” ; Power saving mode
Forced high-impedance control for the charge pump (with internal pull up
resistor.)
ZC = “H” ; Normal Do output.
13 (12)
14 (13)
ZC
I
ZC = “L” ; Do becomes high impedance.
Lock detect signal output (LD) /phase comparator monitoring
output (fout) .
The output signal is selected by LDS bit in the serial data.
LDS = “H” ; outputs fout (fr/fp monitoring output)
LDS = “L” ; outputs LD (“H” at locking, “L” at unlocking.)
LD/fout
O
15 (14)
16 (15)
φP
φR
O
O
Phase comparator output for an external charge pump.
Phase comparator output for an external charge pump.
( ) : for Bcc Package.
3
MB15E06
■ BLOCK DIAGRAM
fr
(16)
1
(15)
16
OSCIN
φR
Crystal
Oscillator
circuit
Phase
comparator
(14)
15
(1)
2
φP
OSCOUT
Lock
detector
SW FC
LDS
Binary 14-bit
reference counter
LD/
fout
(13)
14
(2)
3
LD/fr/fp
selector
14-bit latch
3-bit latch
VP
fp
C
N
T
(12)
13
19-bit shift register
(3)
4
ZC
PS
LE
VCC
7-bit latch
11-bit latch
(11)
12
(4)
5
Intermittent
mode control
(power save)
DO
Binary 11-bit
programmable
counter
Binary 7-bit
swallow counter
(10)
11
(5)
6
GND
Control
1-bit
(9)
10 Data
(6)
7
X fin
MD
Prescaler
64/65,
128/129
(7)
8
(8)
Clock
9
fin
for SSOP Package
( ) for BCC Package
4
MB15E06
■ ABSOLUTE MAXIMUM RAGINGS
Rating
Parameter
Symbol
Unit
Remark
Min.
−0.5
VCC
Max.
+4.0
VCC
VP
V
V
Power supply voltage
+6.0
Output voltage
VO
−0.5
−0.5
−10
−0.5
−55
VCC +0.5
VCC +0.5
+10
V
Input voltage
VI
V
Output current
IO
mA
V
Open drain withstand voltage
Storage temperature
VOOP
Tstg
+7.0
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
2.7
Typ.
Max.
3.6
VCC
VP
VI
3.0
V
V
Power supply voltage
VCC
6.0
Input voltage
GND
−40
VCC
+85
V
Operating temperature
Ta
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15E06
■ ELECTRICAL CHARACTERISTICS
Value
Typ.
Parameter
Symbol
Condition
Unit
Min.
Max.
finIF = 2500 MHz,
fosc = 12 MHz
Power supply current*1
ICC
8.0
mA
Vcccurrent at
PS = “L” and
ZC = “H”
Power saving current*2
Ips
10
µA
Operating frequency
fin
100
3
2500
40
MHz
MHz
Crystal oscillator operating frequency
fOSC
min. 500 mVp−p
50 Ω termination
(Refer to the test
circuit.)
fin
VfinIF
–10
+2
dBm
Input sensitivity
OSCin
VOSC
VIH
VIL
IIH
500
VCC
mVp−p
VCC × 0.7
Data, Clock,
Input voltage
V
LE, PS, ZC
VCC × 0.3
+1.0
+1.0
+1.0
0
−1.0
−1.0
−1.0
−100
0
Data, Clock,
LE, PS
µA
µA
IIL
IIH
Input current
ZC
IIL
Pull up input
IIH
+100
0
OSCin
µA
V
IIL
−100
φP
VOL
VOH
VOL
VDOH
VDOL
Open drain output
0.4
VCC − 0.4
VP − 0.4
–
φR,
LD/fout
V
Output voltage
0.4
–
Do
V
0.4
High impedance
cutoff current
Do
IOFF
1.1
µA
φP
IOL
IOH
IOL
Open drain output
1.0
1.0
mA
−1.0
φR,
LD/fou
mA
mA
VCC = 3.0 V,
Vp = 5 V,
VDOH = 4.0 V
Output current
IDOH
−10.0*2
Do
VCC = 3.0 V,
Vp = 5 V,
IDOL
10.0*2
VDOL = 1.0 V
*1 : Conditions ; VCC = 3.0 V, Ta = 25 °C, in locking state.
*2 : Conditions ; Ta = 25 °C
6
MB15E06
■ FUNCTION DESCRIPTIONS
Pulse Swallow Function
The divide ratio can be calculated using the following equation :
fVCO = [ (M × N) + A] × fOSC ÷ R (A < N)
fVCO : Output frequency of external voltage controlled oscillator (VCO)
N
A
: Preset divide ratio of binary 11-bit programmable counter (5 to 2,047)
: Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127)
fOSC : Output frequency of the reference frequency oscillator
R
: Preset divide ratio of binary 14-bit programmable reference counter (5 to 16,383)
: Preset divide ratio of modules prescaler (64 or 128)
M
Serial Data Input
Serial data is processed using the Data, Clock, and LE pins. Serial data controls the programmable reference
divider and the programmable divider separately.
Binary serial data is entered through the Data pin.
One bit of data is shifted into the shift register on the rising edge of the clock. When the load enable pin is high,
stored data is latched according to the control bit data as follows:
Table.1 Control Bit
Control bit (CNT)
Destination of serial data
17 bit latch (for the programmable reference divider)
18 bit latch (for the programmable divider)
H
L
Shift Register Configuration
Programmable Reference Counter
LSB
Data Flow
MSB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
C
N
T
R
1
R
2
R
3
R
4
R
5
R
6
R
7
R
8
R
9
R
R
R
R
R
10 11 12 13 14 SW FC LDS
CNT
: Control bit
[Table. 1]
R1 to R14 : Divide ratio setting bit for the programmable reference counter (5 to 16,383) [Table. 2]
SW
FC
: Divide ratio setting bit for the prescaler (64/65 or 128/129)
: Phase control bit for the phase comparator
: LD/fout signal select bit
[Table. 5]
[Table. 7]
[Table. 6]
LDS
Note : Start data input with MSB first
7
MB15E06
Programmable Reference Counter
LSB
Data Flow
MSB
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
C
N
T
A
1
A
2
A
3
A
4
A
5
A
6
A
7
N
1
N
2
N
3
N
4
N
5
N
6
N
7
N
8
N
9
N
N
10 11
CNT
: Control bit
[Table. 1]
[Table. 3]
[Table. 4]
N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)
A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)
Note : Start data input with MSB first
Table2. Binary 14-bit Programmable Reference Counter Data Setting
Divide
R
R
R
R
R
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
ratio
(R)
14
13
12
11
10
5
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
1
0
•
6
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : • Divide ratio less than 5 is prohibited.
Table.3 Binary 11-bit Programmable Counter Data Setting
Divide
N
N
N
9
N
8
N
7
N
6
N
5
N
4
N
3
N
2
N
1
ratio
(N)
11
10
5
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
1
1
•
0
1
•
1
0
•
6
•
2047
1
1
1
1
1
1
1
1
1
1
1
Note : • Divide ratio less than 5 is prohibited.
• Divide ratio (N) range = 5 to 2,047
8
MB15E06
Table.4 Binary 7-bit Swallow Counter Data Setting
Divide
A
7
A
6
A
5
A
4
A
3
A
2
A
1
ratio
(A)
0
1
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
0
•
0
1
•
•
127
1
1
1
1
1
1
1
Note : • Divide ratio (A) range = 0 to 127
Table. 5 Prescaler Data Setting
SW
H
Prescaler Divide ratio
64/65
L
128/129
Table. 6 LD/fout Output Select Data Setting
LDS
H
LD/fout output signal
fout signal
LD signal
L
Relation between the FC input and phase characteristics
The FC bit changes the phase characteristics of the phase comparator. Both the internal charge pump output level
(DO) and the phase comparator output (φR, φP) are reversed according to the FC bit. Also, the monitor pin (fOUT)
output is controlled by the FC bit. The relationship between the FC bit and each of DO, φR, and φP is shown below.
Table. 7 FC Bit Data Setting (LDS = “H”)
FC = High
φR
FC = Low
Do
H
φP
L
LD/fout
(fr)
Do
L
φR
H
L
φP
Z*
L
LD/fout
(fp)
fr > fp
fr < fp
fr = fp
L
H
L
L
Z*
Z*
(fr)
H
(fp)
Z*
(fr)
Z*
L
Z*
(fp)
* : High impedance
9
MB15E06
When designing a synthesizer, the FC pin setting depends on the VCO and LPF characteristics.
High
* : When the LPF and VCO characteristics are
(1)
similar to (1) , set FC bit high.
* : WhentheVCOcharacteristicsaresimilar to
(2) , set FC bit low.
VCO
Output
Frequency
(2)
Large
LPF Output Voltage
3. Power Saving Mode (Intermittent Mode Control Circuit)
Setting a PS pin to Low, the IC enters into power saving mode resultatly current sonsumption can be limited to
10 µA (max.) . Setting PS pin to High, power saving mode is released so that the IC works normally.
In addition, the intermittent operation control circuit is included which helps smooth start up from the power
saving mode. In general, the power consumption can be saved by the intermittent operation that powering down
or waking up the synthesizer. Such case, if the PLL is powered up uncontrolled, the resulting phase comparator
output signal is unpredictable due to an undefined phase relation between reference frequency (fr) and compar-
ison frequency (fp) and may in the worst case take longer time for lock up of the loop.
To prevent this, the intermittent operation control circuit enforces a limited error signal output of the phase detector
during power up, thus keeping the loop locked.
During the power saving mode, the corresponding section except for indispensable circuit for the power saving
function stops working, then current consumption is reduced to 10 µA (max.) .
Note : • While the power saving mode is executed, ZC pin should be set at “H” or open. If ZC is set at “L”
during power saving mode, approximately 10 µA current flows.
• PS pin must be set “L” at Power-ON.
• The power saving mode can be released (PS : L → H) 1 µs later after power supply remains stable.
• During the power saving mode, it is possible to input the serial data.
OFF
ON
VCC
≥
tV 1 µs
Clock
Data
LE
≥
tPS 100 ns
PS
(1)
(2)
(3)
(1) PS = L (power saving mode) at Power ON
(2) Set serial data 1 µs later after power supply remains stable (VCC ≥ 2.2 V) .
(3) Release power saving mode (PS : L → H) 100 ns later after setting serial data.
10
MB15E06
Table.8 PS Pin Setting
PS pin
Status
H
L
Normal mode
Power saving mode
Table.9 ZC Pin Setting
ZC pin
Do output
H
L
Normal output
High impedance
11
MB15E06
■ SERIAL DATA INPUT TIMING
≥
≥
≥
≥
t0 100 ns, t1, t2, t4 20 ns, t3, t5 30 ns, t6 100 ns
C:Control bit
(LSB)
(MSB)
Clock
t0
LE
t1
t2
t5
t3
t6
t4
On rising edge of the clock, one bit of the data is transferred into the shift register.
12
MB15E06
■ PHASE COMPARATOR OUTPUT WAVEFORM
fr
fp
tWU
tWL
LD
[FC = "H"]
φP
φR
H
DO
Z
L
[FC = "L"]
φP
φR
H
Z
DO
L
Note : 1. Phase error detection range : −2π to +2π
2. Pulses on Do output signal during locked state are output to prevent dead zone.
3. LD output becomes low when phase is tWU or more. LD output becomes high when phase error is tWL
or less and continues to be so for three cysles or more.
4. tWU and tWL depend on OSCin input frequency.
tWU ≥ 8/fosc (e. g. tWU ≥ 625ns, foscin = 12.8 MHz)
tWL ≤ 16/fosc (e. g. tWL ≤ 1250ns, foscin = 12.8 MHz)
5. LD becomes high during the power saving mode (PS = “L”.)
13
MB15E06
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
VCC = VP = 3 V
1000 pF
0.1 µF
0.1 µF
1000 pF
1000 pF
S • G
S • G
50 Ω
50 Ω
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
VCC
→
Oscilloscope
Controller (setting divide ratio)
Note : SSOP
14
MB15E06
■ TYPICAL CHARACTERISTICS
1. fin Input Sensitivity
Vfin vs. fin
+10
0
Ta = +25 °C
SPEC
−10
−20
−30
−40
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
1000
2000
3000
4000
fin (MHz)
2. OSCin Input Sensitivity
Vfosc vs. fosc
+10
Ta = +25 °C
SPEC
0
−10
−20
−30
−40
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
50
100
fosc (MHz)
15
MB15E06
3. Do Output Current
VOH vs. IOH
Ta = +25 °C
VCC = 3 V
5.0
4.0
3.0
2.0
1.0
0
VP = 5 V
VP = 3 V
0
−5
−10
−15
−20
IOH (mA)
VOL vs. IOL
VP = 5 V
Ta = +25 °C
VCC = 3 V
5.0
4.0
3.0
2.0
1.0
0
VP = 3 V
0
5
10
15
20
IOL (mA)
16
MB15E06
4. fin Input Impedance
1; 10.188 Ω
−36.666 Ω
1 GHz
4
2; 10.731 Ω
1.4438 Ω
3
1.5 GHz
3; 16.474 Ω
31.454 Ω
2 GHz
2
4; 29.314 Ω
50.516 Ω
2.5 GHz
1
5. OSCin Input Impedance
1; 3.516 kΩ
−43.99 kΩ
1 MHz
2;
150.5 Ω
−4.8388 kΩ
10 MHz
3;
30.13 Ω
−2.389 kΩ
20 MHz
3
1
2
4
4; 12.844 Ω
−948.37 Ω
50 MHz
17
MB15E06
■ REFERENCE INFORMATION
•
•
•
•
•
fvco = 1835 MHz
Kv = 87 MHz/v
fr = 200 kHz
fosc = 13 MHz
LPF :
Typical plots measured with the
test circuit are shown below.
Each plot shows lock up time,
phase noise and reference
leakage.
Test Circuit
LPF
S.G
OSCin
fin
Do
15 kΩ
910 Ω
Spectrum
Analyzer
VCO
400 pF
3000 pF
0.03 µF
PLL Lock Up Time = 500 µs
PLL Phase Noise
(1797.6 MHz → 1872.4 MHz, within ± 1kHz)
@ within loop band = 69.4 dBc/H
REF
0.0 dBm ATT 10 dB
∆MKr x : 500.01844 µs
y : −74.8009 MHz
10 dB/
38.00500
MHz
RBW
300 Hz
2.000
kHz/div
VBW
300 Hz
29.99500
MHz
SPAN 50.0 kHz CENTER 1.8350000 GHz
10.1339 µs
1.9903829 ms
PLL Reference Leakage
@ 200 kHz offset = 74.6 dBc
∆MKr x : 500.01844 µs
y : −74.8009 MHz
REF
0.0 dBm ATT 10 dB
250.0000
MHz
10 dB/
50.00000
MHz/div
RBW
0
10 kHz
Hz
VBW
10 kHz
10.1339 µs
1.9903829 ms
SPAN 1.00 MHz CENTER
1.83500 GHz
18
MB15E06
■ APPLICATION EXAMPLE
VP
10 kΩ
12 kΩ
Output
VCO
LPF
12 kΩ
10 kΩ
Lock detect.
From
a controller
φR
φP
ZC
13
LE
11
Data
10
Clock
9
LD/fout
PS
12
16
15
MB15E06
1
2
3
4
5
6
7
8
OSCOUT
OSCIN
VP
GND
fin
DO
Xfin
VCC
1000 pF
1000 pF
0.1 µF
0.1 µF
1000 pF
TCXO
Vp : 5.5 V Max
Note : 1. SSOP-16
2. In case of using a crystal resonator, it is necessary to optimize matching between the crystal
and this LSI, and perform detailed system evaluation. It is recommended to consult with a
supplier of the crystal resonator. (Reference oscillator circuit provides its own bias, feedback
resistor is 100 kΩ (typ) .)
19
MB15E06
■ ORDERING INFORMATION
Part number
Package
Remarks
16-pin Plastic SSOP
(FPT-16P-M05)
MB15E06PFV1
16-pad plastic BCC
(LCC-16P-M06)
MB15E06PV1
20
MB15E06
■ PACKAGE DIMENSION
16-pin Plastic SSOP
(FPT-16P-M05)
* : These dimensions do not include resin protrusion.
1.25 –+00..1200
*
5.00±0.10(.197±.004)
(Mounting height)
.049 +–..000048
0.10(.004)
INDEX
*
4.40±0.10
6.40±0.20
5.40(.213)
NOM
(.173±.004) (.252±.008)
"A"
0.22 –+00..0150
0.15 –+00..0025
Details of "A" part
0.65±0.12
(.0256±.0047)
.009 +–..000024
.006 +–..000012
0.10±0.10(.004±.004)
(STAND OFF)
0
10°
0.50±0.20
(.020±.008)
4.55(.179)REF
C
1994 FUJITSU LIMITED F16013S-2C-4
Dimensions in : mm (inches)
21
MB15E06
16-pad Plastic BCC
(LCC-16P-M06)
4.55±0.10
(.179±.004)
0.80(.031)MAX
Mounting height
3.40(.134)TYP
0.65(.026)
0.325±0.10
(.013±.004)
TYP
0.40±0.10
(.016±.004)
14
9
9
14
0.80(.031)
REF
INDEX AREA
3.40±0.10
(.134±.004)
2.45(.096)
TYP
1.15(.045)
REF
"B"
"A"
0.075±0.025
(.003±.001)
(Stand off)
1.725(.068)
REF
1
6
6
1
Details of "A" part
0.75±0.10
Details of "B" part
0.60±0.10
(.024±.004)
(.030±.004)
0.05(.002)
0.40±0.10
0.60±0.10
(.016±.004)
(.024±.004)
C
1999 FUJITSU LIMITED C16017S-1C-1
Dimensions in : mm (inches)
22
MB15E06
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-8588, Japan
Tel: 81(44) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: 81(44) 754-3329
http://www.fujitsu.co.jp/
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, USA
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Fax: (408) 922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: (800) 866-8608
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
D-63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Any semiconductor devices have an inherent chance of failure.
You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-ede.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan
New Tech Park
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for
export of those products from Japan.
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
http://www.fmap.com.sg/
F9907
FUJITSU LIMITED Printed in Japan
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