概述
数据手册MB15F72SP 概述
Dual Serial Input PLL Frequency Synthesizer 双串行输入锁相环频率合成器
MB15F72SP 数据手册
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PDF下载FUJITSU SEMICONDUCTOR
DATA SHEET
DS04-21363-2E
ASSP
Dual Serial Input
PLL Frequency Synthesizer
MB15F72SP
■ DESCRIPTION
The Fujitsu MB15F72SP is a serial input Phase Locked Loop (PLL) frequency synthesizer with a 1300 MHz and a
350 MHz prescalers. A 64/65 or a 128/129 for the 1300 MHz prescaler, and a 8/9 or a 16/17 for the 350 MHz pres-
caler can be selected for the prescaler that enables pulse swallow operation.
MB15F72SP has the same configuration with MB15F02 or MB15F02L. The BiCMOS process is used , as a result
a supply current is typically 2.7 mA typ. at 2.7 V.The supply voltage range is from 2.4 V to 3.6 V. A refined charge
pump supplies well-balanced output current with 1.5 mA and 6 mA selectable by serial data.
The new package(BCC20) decreases a area of MB15F72SP more than 30 % comparing with the former BCC16
(for dual PLL).
MB15F72SP is ideally suited for wireless mobile communications, such as PDC
■ FEATURES
• High frequency operation:RF synthesizer: 1300 MHz max
:IF synthesizer: 350 MHz max
• Low power supply voltage: VCC = 2.4 to 3.6 V
• Ultra Low power supply current:ICC = 2.7 mA typ. (VCC = Vp = 2.7 V, SWIF = SWRF = 0,
Ta = +25°C, in IF, RF locking state)
• Direct power saving function:Power supply current in power saving mode
Typ. 0.1 µA (VCC = Vp = 2.7 V, Ta = +25°C)
Max. 10 µA (VCC = Vp = 2.7 V)
(Continued)
■ PACKAGES
20-pin plastic TSSOP
20-pad plastic BCC
(FPT-20P-M06)
(LCC-20P-M04)
MB15F72SP
(Continued)
• Software selectable charge pump current: 1.5 mA/6.0 mA (typ.)
• Dual modulus prescaler: 1300 MHz prescaler (64/65 or 128/129 )/350 MHz prescaler (8/9 or 16/17)
• 23 bit shift resister
• Serial input 14-bit programmable reference divider: R = 3 to 16,383
• Serial input programmable divider consisting of:
- Binary 7-bit swallow counter: 0 to 127
- Binary 11-bit programmable counter: 3 to 2,047
• On–chip phase control for phase comparator
• Built-in digital locking detector circuit to detect PLL locking and unlocking.
• Operating temperature: Ta = –40°C to +85°C
• Sireal data format compatible with MB15F02SL
• Small package BCC20 (3.4 mm × 3.6mm × 0.8mm)
■ PIN ASSIGNMENTS
(TSSOP-20)
TOP VIEW
(BCC-20)
TOP VIEW
OSCIN
GND
Data
Clock
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
Clock
Data
OSCIN
GND
finIF
LE
LE
finIF
1
2
3
4
5
6
20 19 18 17 16
finRF
finRF
XfinIF
GNDIF
VCCIF
PSIF
XfinIF
15
14
13
12
XfinRF
GNDRF
VCCRF
XfinRF
GNDRF
VCCRF
PSRF
VpRF
DoRF
GNDIF
VCCIF
PSIF
VpIF
10
9
PSRF
VpIF
8
11
7
DoIF
DoIF
DoRF
VpRF
LD/fout 10
LD/fout
(FPT-20P-M06)
(LCC-20P-M04)
2
MB15F72SP
■ PIN DESCRIPTION
Pin no.
Pin name I/O
Descriptions
TSSOP BCC
The programmable reference divider input. TCXO should be connected with a
AC coupling capacitor.
1
2
3
19
20
1
OSCIN
GND
finIF
I
Ground for OSC input buffer and the shift register circuit.
Prescaler input pin for the IF-PLL.
Connection to an external VCO should be via AC coupling.
I
I
Prescaler complimentary input pin for the IF-PLL section.
This pin should be grounded via a capacitor.
4
5
2
3
XfinIF
GNDIF
Ground for the IF-PLL section.
Power supply voltage input pin for the IF-PLL section(except for the charge
pump circuit), the OSC input buffer and the shift register circuit.
When power is OFF, latched data of IF-PLL is lost.
6
7
4
5
VCCIF
PSIF
Power saving mode control for the IF-PLL section. This pin must be set at “L”
Power-ON. (Open is prohibited.)
I
PSIF = “H” ; Normal mode / PSIF = “L” ; Power saving mode
8
9
6
7
VpIF
DOIF
Power supply voltage input pin for the IF-PLL charge pump.
Charge pump output for the IF-PLL section.
Phase characteristics of the phase detector can be reversed by FCbit.
O
O
O
Lock detect signal output (LD)/phase comparator monitoring
output (fout).The output signal is selected by LDS bit in the serial data.
LDS bit = “H” ; outputs fout signal / LDS bit = “L” ; outputs LD signal
10
8
LD/fout
Charge pump output for the RF-PLL section.
Phase characterstics of the phase detector can be reversed by FCbitt.
11
12
9
DORF
VpRF
10
Power supply voltage input pin for the RF-PLL charge pump.
Power saving mode control for the RF-PLL section. This pin must be set at “L”
Power-ON. (Open is prohibited.)
13
11
PSRF
I
PSRF = “H” ; Normal mode / PSRF = “L” ; Power saving mode
Power supply voltage input pin for the RF-PLL section (except for the charge
pump circuit).
14
15
16
12
13
14
VCCRF
GNDRF
XfinRF
Ground for the RF-PLL section.
Prescaler complimentary input pin for the RF-PLL section.
This pin should be grounded via a capacitor.
I
I
Prescaler input pin for the RF-PLL.
Connection to an external VCO should be via AC coupling.
17
18
15
16
finRF
LE
Load enable signal input(with the schmitt trigger circuit).
When LE is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in a serial data.
I
Serial data input(with the schmitt trigger circuit).
A data is transferred to the corresponding latch(IF-ref. counter, IF-prog. counter,
RF-ref. counter, RF-prog. counter) according to the control bit in a serial data.
19
20
17
18
Data
I
I
Clock input for the 23-bit shift register (with the schmitt trigger circuit).
One bit of data is shifted into the shift register on a rising edge of the clock.
Clock
3
MB15F72SP
■ BLOCK DIAGRAM
VpIF
( )
8 6
VCCIF
GNDIF
5
(
)
(
)
4
6
3
Intermittent
mode control
(IF-PLL)
7 bit latch
Binary 7-bit
swallow counter
(IF-PLL)
3 bit latch
11 bit latch
PSIF
7
5
(
)
fpIF
Phase
comp.
(IF-PLL)
Charge
pump
(IF-PLL)
Binary 11-bit pro-
grammable
counter(IF-PLL)
Current
Switch
9
7
DoIF
LDS SWIF FCIF
(
)
finIF
3
1
4
2
Prescaler
(IF-PLL)
(8/9, 16/17
Lock Det.
(IF-PLL)
(
)
)
XfinIF
(
2 bit latch
14 bit latch
1 bit latch
LDIF
Binary 14-bit pro-
grammable ref.
counter(IF-PLL)
C/P setting
counter
T1
T2
frIF
OSCIN
1
( )
19
Selector
AND
frRF
LD
frIF
frRF
fpIF
fpRF
Binary 14-bit pro-
grammable ref.
counter(RF-PLL))
C/P setting
counter
T1
T2
10
LD/
OR
(
)
fout
8
14 bit latch
1 bit latch
2 bit latch
(
)
)
15
Prescaler
(RF-PLL)
(64/65, 128/129)
finRF 17
Lock Det.
(RF-PLL)
XfinRF 16
(
14
Phase
comp.
(RF-PLL)
Charge
pump
(RF-PLL)
Current
Switch
Binary 11-bit pro-
grammable
counter (RF-PLL)
Binary 7-bit
swallow counter
(RF-PLL)
11
DoRF
LDS SWRF FCRF
Intermittent
mode control
(RF-PLL)
(
)
9
PSRF 13
fpRF
( )
11
3 bit latch
7 bit latch
11 bit latch
Schmitt
circuit
LE 18
Latch selector
(
)
)
16
(
17
Schmitt
circuit
C
N
1
C
N
2
Data 19
23-bit shift register
Schmitt
circuit
Clock 20
(
)
18
2
(
)
(
12
)
14
15
(
)
12
(10)
20
13
VCCRF
GNDRF
GND
VpRF
O : TSSOP
( ) : BCC
4
MB15F72SP
■ ABSOLUTE MAXIMUM RATINGS
Rating
Parameter
Symbol
Unit
Min.
−0.5
VCC
Max.
4.0
VCC
Vp
V
V
Power supply voltage
Input voltage
4.0
VI
−0.5
GND
GND
−55
VCC + 0.5
VCC
V
V
LD/fout
VO
Output voltage
DoIF, DoRF
VDO
Tstg
Vp
V
Storage temperature
+125
°C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■ RECOMMENDED OPERATING CONDITIONS
Value
Parameter
Symbol
Unit
Remark
Min.
2.4
Typ.
2.7
Max.
3.6
VCC
Vp
VI
V
V
VCCRF = VCCIF
Power supply voltage
VCC
2.7
3.6
Input voltage
GND
−40
VCC
+85
V
Operating temperature
Ta
°C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
5
MB15F72SP
■ ELECTRICAL CHARACTERISTICS
(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)
Value
Unit
Sym-
Parameter
bol
Condition
Min.
Typ.
Max.
ICCIF *1 IF PLL
1.1
mA
mA
Power supply current
*2
ICCRF
IPSIF
RF PLL
1.6
PSIF = PSRF = “L”
0.1 *8
0.1 *8
10
10
µA
Power saving current
Operating frequency
IPSRF PSIF = PSRF = “L”
finIF IF PLL
µA
*3
finIF
50
100
3
350
1300
40
MHz
MHz
MHz
dBm
dBm
VP − P
*3
finRF
finRF RF PLL
OSCIN
finIF
fOSC
PfinIF IF PLL, 50 Ω system
PfinRF RF PLL, 50 Ω system
VOSC
−15
−15
0.5
+2
Input sensitivity
finRF
+2
OSCIN
VCC
Data,
LE,
Clock
“H” level input voltage
“L” level input voltage
VIH
VIL
Schmitt trigger input
Schmitt trigger input
0.7 VCC + 0.4
V
V
0.3 VCC − 0.4
“H” level input voltage
“L” level input voltage
VIH
0.7 VCC
V
V
PSIF,
PSRF
VIL
0.3 VCC
Data,
LE,
Clock,
PSIF,
PSRF
*4
“H” level input current
“L” level input current
IIH
−1.0
−1.0
+1.0
µA
µA
*4
IIL
+1.0
“H” level input current
“L” level input current
IIH
0
+100
µA
µA
OSCIN
*4
IIL
−100
0
VCC = Vp = 2.7 V,
IOH = −1 mA
“H” level output voltage
“L” level output voltage
“H” level output voltage
VOH
VOL
VCC − 0.4
Vp − 0.4
V
V
V
LD/fout
VCC = Vp = 2.7 V, IOL = 1 mA
0.4
VCC = Vp = 2.7 V,
IDOH = −0.5 mA
VDOH
DoIF,
DoRF
VCC = Vp = 2.7 V,
IDOL = 0.5 mA
“L” level output voltage
VDOL
0.4
V
High impedance
cutoff current
DoIF,
DoRF
VCC = Vp = 2.7 V
VOFF = 0.5 V to Vp − 0.5 V
IOFF
2.5
nA
*4
VCC = Vp = 2.7 V
VCC = Vp = 2.7 V
“H” level output current
“L” level output current
IOH
−1.0
mA
mA
LD/fout
IOL
1.0
(Continued)
6
MB15F72SP
(Continued)
(VCC = 2.4 V to 3.6 V, Ta = −40 °C to +85 °C)
Value
Unit
Parameter
Symbol
Condition
VCC = Vp = 2.7 V,
VDOH = Vp/2,
Ta = +25 °C
Min.
Typ.
Max.
CS bit = “H”
CS bit = “L”
CS bit = “H”
CS bit = “L”
−6.0
mA
mA
mA
mA
“H” level output
current
DoIF
DoRF
*4
IDOH
−1.5
6.0
VCC = Vp = 2.7 V,
VDOL = Vp/2,
Ta = +25 °C
“L” level output
current
DoIF
DoRF
IDOL
1.5
*5
IDOL/IDOH IDOMT
vs. VDO IDOVD
VDO = Vp / 2
3
%
%
*6
*7
Charge pump
current rate
0.5 V ≤ VDO ≤ Vp − 0.5 V
10
−40 °C ≤ Ta ≤ +85 °C,
VDO = Vp / 2
vs.Ta
IDOTA
10
%
*1 : finIF = 270 MHz, fosc = 12.8 MHz, VCCIF = VpIF = 2.7 V, SWIF = 0, Ta = +25°C, in locking state.
*2 : finRF = 910 MHz, fosc = 12.8 MHz, VCCRF = VpRF = 2.7 V, SWRF = 0, Ta = +25°C, in locking state.
*3 : AC coupling. 1000pF capacitor is connected under the condition of min. operating frequency.
*4 : The symbol “–” (minus) means direction of current flow.
*5 : VCC = Vp = 2.7 V, Ta = +25°C
(||I3| – |I4||)/[(|I3| + |I4|)/2] × 100(%)
*6 : VCC = Vp = 2.7 V, Ta = +25°C (Applied to each IDOL, IDOH)
[(||I2| – |I1||)/2]/[(|I1| + |I2|)/2] × 100(%)
*7 : VCC = Vp = 2.7 V, Ta = +25°C (Applied to each IDOL, IDOH)
[||IDO(+85°C)| –|IDO(–40°C)||/2]/[|IDO(+85°C)| + |IDO(–40°C)|/2] × 100(%)
*8 : fosc = 12.8 MHz, VCCRF = VpRF = VCCIF = 2.7 V, Ta = +25°C
I1
I3
I4
I2
IDOL
IDOH
I1
Vp/2
Vp − 0.5 Vp
0.5
Charge pump output voltage (V)
7
MB15F72SP
■ FUNCTIONAL DESCRIPTION
1. Pulse swallow function :
fVCO = [(P × N) + A] × fOSC ÷ R
fVCO : Output frequency of external voltage controlled oscillator (VCO)
P : Preset divide ratio of dual modulus prescaler (8 or 16 for IF-PLL, 64 or 128 for RF-PLL)
N : Preset divide ratio of binary 11-bit programmable counter (3 to 2,047)
A : Preset divide ratio of binary 7-bit swallow counter (0 ≤ A ≤ 127, A < N)
fOSC : Reference oscillation frequency (OSCIN input frequency)
R : Preset divide ratio of binary 14-bit programmable reference counter (3 to 16,383)
2. Serial Data Input
Serial data is entered using three pins, Data pin, Clock pin, and LE pin. Programmable dividers of IF/RF-PLL sec-
tions, and programmable reference dividers of IF/RF-PLL sections are controlled individually.
Serial data of binary data is entered through Data pin.
On a rising edge of Clock, one bit of serial data is transferred into the shift register. On a rising edge of load enable
signal, the data stored in the shift register is transferred to one of latch of them depending upon the control bit data
setting.
The programmable The programmable
The programmable
The programmable
reference counter
for the IF-PLL
reference counter counter and the swallow counter and the swallow
for the RF-PLL
counter for the IF-PLL
counter for the RF-PLL
CN1
CN2
0
0
1
0
0
1
1
1
(1) Shift Register Configuration
• Programmable Reference Counter
(LSB)
(MSB)
Data Flow
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CN1 CN2 T1 T2 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 CS
X
X
X
X
CS
R1 to R14 : Divide ratio setting bits for the programmable reference counter (3 to 16,383)
T1, T2 : Test purpose bit
CN1, CN2 : Control bit
: Charge pump currnet select bit
X
: Dummy bits (Set “0” or “1”)
Note : Data input with MSB first.
8
MB15F72SP
• Programmable Counter
(LSB)
(MSB)
Data Flow
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SWIF/ FCIF/
SWRF FCRF
CN1 CN2 LDS
A1 A2 A3 A4 A5 A6 A7 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11
A1 to A7
: Divide ratio setting bits for the swallow counter (0 to 127)
N1 to N11 : Divide ratio setting bits for the programmable counter (3 to 2,047)
LDS : LD/fout signal select bit
SWIF/SWRF : Divide ratio setting bit for the prescaler (IF : SWIF,RF : SWRF)
FCIF/FCRF : Phase control bit for the phase detector (IF: FCIF, RF: FCRF)
CN1, CN2 : Control bit
Note: Data input with MSB first.
(2) Data setting
• Binary 14-bit Programmable Reference Counter Data Setting (R1 to R14)
Divide ratio
R14 R13 R12 R11 R10 R9
R8
R7
R6
R5
R4
R3 R2
R1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
0
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
• Binary 11-bit Programmable Counter Data Setting (N1 to N11)
Divide ratio
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
•
0
•
0
•
0
•
0
•
0
•
0
•
0
•
1
•
0
•
0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2047
1
1
1
1
1
1
1
1
1
1
1
Note : Divide ratio less than 3 is prohibited.
• Binary 7-bit Swallow Counter Data Setting (A1 to A7)
Divide ratio
A7
A6
A5
A4
A3
A2
A1
0
0
0
0
0
0
0
0
1
0
•
0
•
0
•
0
•
0
•
0
•
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
127
1
1
1
1
1
1
1
9
MB15F72SP
• Prescaler Data Setting (SW)
Divide ratio
SW = “1”
8/9
SW = “0”
16/17
Prescaler divide ratio IF-PLL
Prescaler divide ratio RF-PLL
64/65
128/129
• Charge Pump CurrentSetting (CS)
• LD/fout Output Select Data Setting (LDS)
Current value
±6.0 mA
CS
1
LD/fout output signal
fout signal
LDS
1
0
±1.5 mA
0
LD signal
• Test Purpose Bit Setting (T1, T2)
LD/fout pin state
Outputs frIF.
T1
T2
0
0
Outputs frRF.
Outputs fpIF.
Outputs fpRF.
1
0
1
0
1
1
• Phase Comparator Phase Switching Data Setting (FCIF, FCRF)
FCIF = “1” FCRF = “1” FCIF = “0” FCRF = “0”
Phase comparator input
DoIF
DoRF
DoIF
DoRF
fr > fp
fr < fp
H
L
L
H
Z
fr = fp
Z
Z : High-impedance
Depending upon the VCO and LPF polarity, FC bit should be set.
High
(1)
(1) VCO polarity FC = “1”
(2) VCO polarity FC = “0”
VCO Output
Frequency
(2)
Max.
LPF Output voltage
Note : Give attention to the polarity for using active type LPF.
10
MB15F72SP
3. Power Saving Mode (Intermittent Mode Control Circuit)
Status
PSIF/PSRF pins
Normal mode
H
L
Power saving mode
The intermittent mode control circuit reduces the PLL power consumption.
By setting the PS pins low, the device enters into the power saving mode, reducing the current consumption.
See the Electrical Characteristics chart for the specific value.
The phase detector output, Do, becomes high impedance.
For the dual PLL, the lock detector, LD, is as shown in the LD Output Logic table.
Setting the PS pins high, releases the power saving mode, and the device works normally.
The intermittent mode control circuit also ensures a smooth startup when the device returns to normal operation.
When the PLL is returned to normal operation, the phase comparator output signal is unpredictable. This is
because of the unknown relationship between the comparison frequency (fp) and the reference frequency (fr)
which can cause a major change in the comparator output, resulting in a VCO frequency jump and an increase
in lockup time.
To prevent a major VCO frequency jump, the intermittent mode control circuit limits the magnitude of the error
signal from the phase detector when it returns to normal operation.
Notes •When power (VCC) is first applied, the device must be in standby mode, PSIF = PSRF = Low, for at least 1 µs.
•PS pins must be set at “L” for Power-ON.
OFF
ON
VCC
tV ≥ 1 µs
Clock
Data
LE
PSIF
PSRF
tPS ≥ 100 ns
(1)
(2)
(3)
(1) PS IF = PSRF = “L” (power saving mode) at Power-ON
(2) Set serial data 1 µs later after power supply remains stable (VCC > 2.2 V).
(3) Release power saving mode (PS IF, PSRF : “L” → “H”) 100 ns later after setting serial data.
11
MB15F72SP
4. SERIAL DATA INPUT TIMING
Frequency multiplier setting is performed through a serial interface using the Data pin, Clock pin, and LE pin.
Setting data is read into the shift register at the rise of the clock signal, and transferred to a latch at the rise of
the LE signal. The following diagram shows the data input timing.
2nd data
1st data
Invalid data
Control bit
Data
MSB
LSB
Clock
t1
t2
t3
t6
t7
LE
t4
t5
Parameter
Min. Typ. Max. Unit
Parameter
Min. Typ. Max. Unit
t1
t2
t3
t4
20
20
30
30
ns
ns
ns
ns
t5
t6
t7
100
20
ns
ns
ns
100
Note : LE should be “L” when the data is transferred into the shift register.
12
MB15F72SP
■ PHASE COMPARATOR OUTPUT WAVEFORM
frIF/frRF
fpIF/fpRF
tWU
tWL
LD
(FC bit = “1”)
H
DoIF/DoRF
Z
L
(FC bit = “0”)
H
DoIF/DoRF
Z
L
• LD Output Logic
IF-PLL section
RF-PLL section
Locking state/Power saving state
Unlocking state
LD output
Locking state/Power saving state
Locking state/Power saving state
Unlocking state
H
L
L
L
Locking state/Power saving state
Unlocking state
Unlocking state
Notes:•Phase error detection range = –2π to +2π
•Pulses on DoIF/DoRF signals are output to prevent dead zone during locking state.
•LD output becomes low when phase error is tWU or more.
•LD output becomes high when phase error is tWL or less and continues to be so for three cycles or more.
•tWU and tWL depend on OSCIN input frequency as follows.
tWU > 2/fosc : e.g. tWU > 156.3 ns when fosc = 12.8 MHz
tWU < 4/fosc : e.g. tWL < 312.5 ns when fosc = 12.8 MHz
13
MB15F72SP
■ TEST CIRCUIT (for Measuring Input Sensitivity fin/OSCIN)
fout
Oscilloscope
1000 pF
VCCIF
VpIF
1000 pF
S.G.
50 Ω
0.1 µF
0.1 µF
1000 pF
S.G.
LD/
fout
50 Ω
DoIF
9
VpIF
8
PSIF
VCCIF
6
GNDIF XfinIF
finIF
GND
OSCIN
10
7
5
4
3
2
1
11
12
13
14
15
16
17
18
19
20
XfinRF
finRF
VpRF
PSRF
VCCRF
DoRF
GNDRF
LE
Data
Clock
1000 pF
Controller
(divide ratio setting)
1000 pF
VpRF
VCCRF
S.G.
50 Ω
0.1 µF
0.1 µF
Note : Terminal number shows that of TSSOP-20.
14
MB15F72SP
■ TYPICAL CHARACTERISTICS
1. fin input sensitivity
RF-PLL input sensitivity - Input frequency
Ta = +25 °C
10
5
0
−5
SPEC
−10
−15
−20
−25
−30
−35
−40
−45
−50
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
200
400
600
800
1000
1200
1400
1600
1800
2000
Input frequency finRF (MHz)
IF-PLL input sensitivity - Input frequency
Ta = +25 °C
10
5
0
−5
SPEC
−10
−15
−20
−25
−30
−35
−40
−45
−50
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
Input frequency finIF (MHz)
15
MB15F72SP
2. OSCIN input sensitivity
Input sensitivity vs Input frequency
Ta = +25 °C
10
SPEC
0
−10
−20
−30
−40
−50
−60
VCC = 2.4 V
VCC = 2.7 V
VCC = 3.0 V
VCC = 3.6 V
0
20
40
60
80
100
120
140
160
180
200
220
Input frequency fOSC (MHz)
16
MB15F72SP
3. RF-PLL Do output current
• 1.5 mA mode
IDO - VDO
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
0.0
IDOH
−10.0
0.0
1.0
2.0
2.7
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO - VDO
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
0.0
IDOH
−10.0
0.0
1.0
2.0
2.7
Charge pump output voltage VDO (V)
17
MB15F72SP
4. IF-PLL Do output current
• 1.5 mA mode
IDO − VDO
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
IDOH
0.0
−10.0
2.7
0.0
1.0
2.0
Charge pump output voltage VDO (V)
• 6.0 mA mode
IDO − VDO
10.0
Ta = +25 °C
VCC = Vp = 2.7 V
IDOL
0.0
IDOH
−10.0
1.0
2.0
2.7
0.0
Charge pump output voltage VDO (V)
18
MB15F72SP
5. fin input impedance
finRF input impedance
VCC = 2.7 V
1 : 266.06 Ω
−661.69 Ω
100 MHz
2 : 21.406 Ω
−146.27 Ω
500 MHz
3 : 11.1 Ω
−62.982 Ω
1 GHz
4 : 10.35 Ω
−38.861 Ω
1.3 GHz
1
2
4
3
START 100.000 000 MHz
STOP 1 500.000 000 MHz
finIF input impedance
VCC = 2.7 V
1 : 712.91 Ω
−967.81 Ω
50 MHz
2 : 251.59 Ω
−650.97 Ω
100 MHz
3 : 40.648 Ω
−241.14 Ω
300 MHz
4 : 20.391 Ω
−141.98 Ω
500 MHz
1
2
4
3
START 50.000 000 MHz
STOP 500.000 000 MHz
19
MB15F72SP
6. OSCIN input impedance
OSCIN input impedance
VCC = 2.7 V
1 :10.693 kΩ
−11.664 kΩ
3 MHz
2 :1.8725 kΩ
−6.3285 kΩ
10 MHz
3 : 124.25 Ω
−1.6726 kΩ
40 MHz
4
1
2
4 : 31.188 Ω
−664.28 Ω
100 MHz
3
START 3.000 000 MHz
STOP 100.000 000 MHz
20
MB15F72SP
■ REFERENCE INFORMATION
(for Lock-up Time, Phase Noise and Reference Leakage)
Test Circuit
fVCO = 680 MHz
KV = 50 MHz/V
fr = 25 kHz
fOSC = 14.4 MHz
LPF
VCC = 3.0 V
VVCO = 2.2 V
Ta = + 25 °C
CP : 6 mA mode
S.G.
OSCIN
LPF
DO
fin
1.0 kΩ
Spectrum
Analyzer
VCO
2.2 kΩ
4700 pF
2200 pF
0.047 pF
• PLL Reference Leakage
ATTEN 10 dB
VAVG 72 ∆MKR −73.67 dB
10 dB/ 25.0 kHz
RL
0 dBm
∆MKR
25.0 kHz
−73.67 dB
CENTER 680.0000 MHz
RBW 1.0 kHz VBW 1.0 kHz
SPAN 200.0 kHz
SWP 500 ms
• PLL Phase Noise
ATTEN 10 dB
VAVG 23 ∆MKR −55.00 dB
10 dB/ 5.37 kHz
RL
0 dBm
∆MKR
5.37 kHz
−55.00 dB
CENTER 680.0000 MHz
RBW 100 Hz VBW 100 Hz
SPAN 20.00 kHz
SWP 1.60 s
(Continued)
21
MB15F72SP
(Continued)
• PLL Lock Up time
• PLL Lock Up time
680 MHz→755 MHz within±1 kHz
Lch→Hch 1.244 ms
755 MHz→680 MHz within ± 1 kHz
Hch→Lch 1.133 ms
680.004000 MHz
755.004250 MHz
755.000250 MHz
680.000000 MHz
754.996250 MHz
679.996000 MHz
−822 µs
4.178 ms
1.000 ms/div
9.178 ms
−822 µs
4.178 ms
1.000 ms/div
9.178 ms
855.00 MHz
755.00 MHz
780.00 MHz
680.00 MHz
655.00 MHz
580.00 MHz
−822 µs
4.178 ms
9.178 ms
−822 µs
4.178 ms
1.000 ms/div
9.178 ms
1.000 ms/div
22
MB15F72SP
■ APPLICATION EXAMPLE
OUTPUT
VCO
2.7 V
LPF
2.7 V
1000 pF
from controller
1000 pF
0.1 µF
0.1 µF
Clock
20
Data
19
LE
18
XfinRF GNDRF
16 15
PSRF
13
VpRF
DoRF
11
finRF
17
VCCRF
14
12
MB15F72SP
1
2
3
4
5
6
7
8
9
10
finIF
XfinIF
VCCIF
GNDIF
DoIF
LD/fout
PSIF
VpIF
GND
OSCIN
Lock Det.
2.7 V
2.7 V
1000 pF
1000 pF
1000 pF
0.1 µF
0.1 µF
TCXO
OUTPUT
VCO
LPF
Notes : • Clock, Data, LE : Schmitt trigger circuit is provided(insert a pull-down or pull-up registor to
prevent oscillation when open-circuit in the input).
• Terminal number shows that of TSSOP-20.
23
MB15F72SP
■ USAGE PRECAUTIONS
(1) VCCRF, VpRF, VCCIF and VpIF must equal equal voltage.
Even if either RF-PLL or IF-PLL is not used, power must be supplied to both VCCRF, VpRF, VCCIF and VpIF to
keep them equal. It is recommended that the non-use PLL is controlled by power saving function.
(2) To protect against damage by electrostatic discharge, note the following handling precautions:
-Store and transport devices in conductive containers.
-Use properly grounded workstations, tools, and equipment.
-Turn off power before inserting or removing this device into or from a socket.
-Protect leads with conductive sheet, when transporting a board mounted device.
■ ORDERING INFORMATION
Part number
MB15F72SPPFT
MB15F72SPPV
Package
Remarks
20-pin plastic TSSOP
(FPT-20P-M06)
20-pad plastic BCC
(LCC-20P-M04)
24
MB15F72SP
■ PACKAGE DIMENSIONS
20-pin plastic TSSOP
(FPT-20P-M06)
Note 1 ) * : These dimensions do not include resin protrusion.
Note 2 ) Pins width and pins thickness include plating thickness.
*
6.50±0.10(.256±.004)
0.17±0.05
(.007±.002)
20
11
*
4.40±0.10 6.40±0.20
(.173±.004) (.252±.008)
INDEX
Details of "A" part
1.05±0.05
(.041±.002)
(Mounting height)
1
10
LEAD No.
"A"
0.65(.026)
0.24±0.08
(.009±.003)
0~8°
M
0.13(.005)
0.07 +–00..0073 .003 –+..000031
(0.50(.020))
(Stand off)
0.25(.010)
0.45/0.75
(.018/.030)
0.10(.004)
Dimensions in mm (inches)
(Continued)
C
1999 FUJITSU LIMITED F20026S-2C-2
25
MB15F72SP
(Continued)
20-pad plastic BCC
(LCC-20P-M04)
3.00(.118)TYP
0.25±0.10
3.60±0.10(.142±.004)
0.80(.031)MAX
(Mounting height)
(.010±.004)
16
11
11
16
0.50(.020)
TYP
0.25±0.10
(.010±.004)
INDEX AREA
3.40±0.10
(.134±.004)
2.70(.106)
TYP
"D"
"A"
"B"
"C"
1
6
6
1
0.50(.020)
TYP
2.80(.110)REF
0.085±0.04
(.003±.002)
(Stand off)
0.05(.002)
Details of "A" part
Details of "B" part
Details of "C" part
Details of "D" part
0.50±0.10
0.50±0.10
0.50±0.10
0.30±0.10
(.020±.004)
(.020±.004)
(.020±.004)
(.012±.004)
C0.20(.008)
0.60±0.10
(.024±.004)
0.30±0.10
(.012±.004)
0.60±0.10
(.024±.004)
0.40±0.10
(.016±.004)
Dimensions in mm (inches)
C
26
MB15F72SP
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
All Rights Reserved.
Corporate Global Business Support Division
Electronic Devices
The contents of this document are subject to change without
notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
KAWASAKI PLANT, 4-1-1, Kamikodanaka,
Nakahara-ku, Kawasaki-shi,
Kanagawa 211-8588, Japan
Tel: +81-44-754-3763
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications,
and are not intended to be incorporated in devices for actual use.
Also, FUJITSU is unable to assume responsibility for
Fax: +81-44-754-3329
http://www.fujitsu.co.jp/
infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, USA
Tel: +1-408-922-9000
The contents of this document may not be reproduced or copied
without the permission of FUJITSU LIMITED.
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipments, industrial, communications, and
measurement equipments, personal or household devices, etc.).
CAUTION:
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded
(such as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTRONICS EUROPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE LTD
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
Fax: +65-281-0220
http://www.fmap.com.sg/
F0002
FUJITSU LIMITED Printed in Japan
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