MB89P915PF-101 [FUJITSU]
8-bit Proprietary Microcontroller; 8位微控制器专有
| 型号： | MB89P915PF-101 |
| 厂家： | 
FUJITSU |
| 描述： | 8-bit Proprietary Microcontroller |
| 文件： | 总53页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-12521-3E
8-bit Proprietary Microcontroller
CMOS
F2MC-8L MB89910 Series
MB89913/915/P915/PV910
■ DESCRIPTION
The MB89910 series has been developed as a general-purpose version of the F2MC*-8L family consisting of
proprietary 8-bit, single-chip microcontrollers.
In addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as
dual-clock control system, five operating speed control stages, timers, a serial interface, an A/D converter, a
buzzer output, a low-voltage detection reset, high-voltage driver, a watch prescaler, and external interrupts.
The MB89910 series is applicable to a wide range of applications from consumer products to industrial
equipments.
*: F2MC stands for FUJITSU Flexible Microcontroller.
■ FEATURES
• Minimum execution time: 0.50 µs/8.0 MHz oscillation
• Interrupt processing time: 4.50 µs/8.0 MHz oscillation
• F2MC-8L family CPU core
Multiplication and division instructions
16-bit arithmetic operations
Test and branch instructions
Instruction set optimized for controllers
Bit manipulation instructions, etc.
• Dual-clock control system
(Continued)
■ PACKAGE
48-pin Plastic SH-DIP
48-pin Plastic QFP
64-pin Ceramic MDIP
(FPT-48P-M15)
(DIP-48P-M01)
(MDP-64C-P02)
MB89910 Series
(Continued)
• High-voltage ports (built-in a pull-down resistor capable)
8 ports for large current
10 ports for small current
• 8-bit PWM timer: 1 channel
• 16-bit timer/counter: 1 channel
• 21-bit timebase timer
• 8-bit serial I/O: 1 channel
• 8-bit A/D converter: 8 channels
• External interrupt
Edge detection function
Two channels, including one of which voltage can be applied from –0.3 to +7.0 V
• Low-voltage detection reset (excluding the MB89PV910)
• Low-power consumption modes (subclock mode, watch mode, sleep mode, and stop mode)
• Reset output and power-on reset function
• Watch prescaler
2
MB89910 Series
■ PRODUCT LINEUP
Partnumber
Parameter
MB89915
MB89913
MB89P915
MB89PV910
Classification
ROM size
Piggyback/
One-time PROM evaluation product
Mass production product
(mask ROM product)
product
(for evaluation and
development)
8 K × 8 bits
16 K × 8 bits
(internal mask
ROM)
16 K × 8 bits
32K × 8 bits
(internal mask
ROM)
(internal PROM, (Piggyback)
programmable with (External ROM)
general-purpose
EPROM
programmer)
RAM size
256 × 8 bits
512 × 8 bits
1 K × 8 bits
CPU functions
Number of instructions:
Instruction bit length:
Instruction length:
136
8 bits
1 to 3 bytes
1, 8, 16 bits
Data bit length:
Minimum execution time:
0.50 µs/8.0 MHz to 8.00 µs/8.0 MHz, or
61 µs/32.768 kHz
Interrupt processing time: 4.5 µs/8.0 MHz to 72.0 µs/8.0 MHz, or
549.3 µs/32.768 kHz
Note: The above times depend on the gear
function.
Ports
High-voltage output ports (P-ch open-drain):
8 (P10 to P17 for large current)
10 (P20 to P27 and P50 to P51 for small current)
13 (P00 to P07, P34 to P37, and P40)
I/O ports (CMOS):
I/O ports (N-ch open-drain): 6 (P30 to P33, P41, P42)
Input ports (CMOS):
Total:
2 (P60 and P61 also serve as a subclock pin)
39
Timebase timer
(Timer 1)
Capable of generating four different intervals at 8.0-MHz oscillation: 0.26, 0.51, 1.02,
and 524.0 ms
8-bit PWM timer (Timer 2) 8-bit timer operation (square wave output capable. Operation clock: 1, 2, 8, or 16
instruction cycles)
8-bit resolution PWM operation (Conversion cycle: 128 µs to 2.0 ms at 8.0 MHz)
16-bit timer/counter
(Timer 3)
16-bit timer operation (operating clock: 1 instruction cycle)
16-bit event counter operation (Rising/falling/both edges selectable)
8-bit serial I/O
8 bits
LSB first/MSB first selectable
Transfer clock (external, 4/8/16 instruction cycles)
8-bit A/D converter
8-bit resolution × 8 channels
A/D conversion mode (conversion time of 22.0 µs/8.0 MHz)
Sense mode (conversion time of 6.0 µs/8.0 MHz)
Continuous activation enabled by external clock or internal clock
Reference voltage input (AVR) is provided.
(Continued)
3
MB89910 Series
(Continued)
Partnumber
MB89915
MB89913
MB89P915
MB89PPV910
Parameter
External interrupt
2 independent channels (edge selection, interrupt vector, factor flag)
Rising/ falling/both edges selectable
Built-in analog noise canceller
Used also for wake-up stop/sleep modes.
(Edge detection is also permitted in stop mode.)
Low-voltage detection
reset
Continuous operation
(detection power supply voltage of 4.0±0.3 V, 3.6±0.3 V or
3.3±0.3 V)
Not available
Intermittent operation
(Activated for each watch interrupt under the dual-clock sys-
tem)
Low-power consumption
(Standby mode)
Sleep mode, stop mode, and watch mode
CMOS
Process
Operating voltage*
3.8 V to 5.5 V
4.5 V to 5.5 V
EPROM for use
MBM27C256A-
20CZ
* : Varies with conditions such as the operating frequency. (See section “■ Electrical Characteristics.”)
In the case of the MB89PV910, the voltage varies with the ICE or the EPROM to be connected.
■ PACKAGE AND CORRESPONDING PRODUCTS
MB89913
Package
MB89915
MB89PV910
MB89P915
DIP-48P-M01
FPT-48P-M15
MDP-64C-P02
×
×
1
*
2
×
*
: Available
×: Not available
*1: Under examination for development
*2: Available by conversion from MDIP-64 to SH-DIP-48
64SD-48SD-8L2: For conversion (MDP-64C-P02) → DIP-48P-M01
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Note: For more information about each package, see section “■ Package Dimensions.”
4
MB89910 Series
■ DIFFERENCES AMONG PRODUCTS
1. Memory Size
Before evaluating using the piggyback product, verify its differences from the product that will actually be used.
Take particular care on the following points:
• The stack area, etc., is set at the upper limit of the RAM.
2. Current Consumption
• In the case of the MB89PV910, add the current consumed by the EPROM which is connected to the top socket.
• When operated at low speed, the product with an OTPROM (one-time PROM) or an EPROM will consume
more current than the product with a mask ROM.
However, the current consumption in sleep/stop modes is the same. (For more information, see sections
“■ Electrical Characteristics” and “■ Example Characteristics.”)
3. Mask Options
Functions that can be selected as options and how to designate these options vary by the product.
Before using options check section “■ Mask Options.”
Take particular care on the following points:
• A pull-down resistor for P10 to P17, P20 to P27, and for P50 to P51 cannot be set for the MB89P915 and
MB89PV910. The MB89915 and MB89913 allow a pull-down resistor to be set for individual pins. Such pins
on the MB89P915 and MB89PV910 are fixed to have no pull-down resistor.
• The low-voltage detection reset cannot be used on the MB89PV910. The voltage to be detected by the low-
voltage detection reset is set by using a register for the MB89P915 and by using a mask option for the MB89915
and MB89913. If the detection voltage has been set to a lower value than the operating voltage, however, use
the gear function to operate the device with the faster clock at a lower speed, or operate the device with the
slower clock. Note that the results of operation are unpredictable if the device is attempted to operate at a
lower voltage than the operating voltage with the faster clock put in top gear.
5
MB89910 Series
■ PIN ASSIGNMENT
(Top view)
1
2
3
4
5
6
7
8
VCC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
AVSS
AVR
P10
P11
P12
P13
P14
P15
P16
P17
VFDP
P20
P21
P22
P23
P24
P25
P26
P27
P50
P51/BZ1
TEST
X1
P37/AN7
P36/AN6
P35/AN5
P34/AN4
P33/AN3
P32/AN2
P31/AN1
P30/AN0
P07/SCK
P06/SO
P05/SI
P04/PWO
P03/EC
P02/ADST
P01/BZ2
P00
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P61/X1A
P60/X0A
P42
P41/INT1
P40/INT0
RST
X0
VSS
(DIP-48P-M01)
(Top view)
P33/AN3
P32/AN2
P31/AN1
P30/AN0
P07/SCK
P06/SO
P05/SI
P04/PWO
P03/EC
P02/ADST
P01/BZ2
P00
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
P15
P16
P17
VFDP
P20
P21
P22
P23
P24
P25
P26
P27
Under examination
for development
10
11
12
(FPT-48P-M15)
6
MB89910 Series
(Top view)
VCC
1
2
3
4
5
6
7
8
AVSS
AVR
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P10
P11
P12
P13
P14
P15
P16
P17
VFDP
P20
P21
P22
P23
P24
P25
P26
P27
P50
P51/BZ1
TEST
X1
65
66
67
68
69
70
71
72
73
74
75
76
77
78
VCC
A14
A13
A8
VPP
A12
A7
A6
A5
A4
A3
A2
A1
92
91
90
89
88
87
86
85
84
83
82
81
80
79
P37/AN7
P36/AN6
P35/AN5
P34/AN4
P33/AN3
P32/AN2
P31/AN1
P30/AN0
P07/SCK
P06/SO
P05/SI
P04/PWO
P03/EC
P02/ADST
P01/BZ2
P00
A9
A11
OE
A10
CE
O8
O7
O6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A0
O1
O2
O3
VSS
O5
O4
P61/X1A
P60/X0A
P42
P41/INT1
P40/INT0
RST
X0
VSS
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
VSS
(MDP-64C-P02)
7
MB89910 Series
■ PIN DESCRIPTION
Pin no.
Circuit
type
Pin name
Function
SH-
QFP*2
MDIP*3
DIP*1
26
27
20
20
21
14
42
43
20
X0
A
I
Main clock crystal oscillator pins
X1
X0A/P60
These pins can select either general-purpose CMOS
inputs or subclock oscillator pins by the mask options.
When these pins are used as a general-purpose input
pin, the pin is a hysteresis input with a built-in noise
canceller.
19
24
13
18
19
24
X1A/P61
RST
C
Reset I/O pin
This pin is an N-ch open-drain output type with pull-up
resistor and a hysteresis input type. “L” is output from
this pin by an internal source. The internal circuit is
initialized by the input of “L”. This pin is with a noise
canceller.
18
17
16
12
11
10
18
17
16
P00
D
D
D
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller.
P01/BZ2
P02/ADST
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller. Also serves as a buzzer output.
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller. Also serves as the external activation
pin for the A/D converter.
15
14
9
8
15
14
P03/EC
D
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller. Also serves as the external clock input
for the 16-bit timer/counter.
P04/PWO
D
D
D
G
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller. Also serves as the PWM output for
the 8-bit PWM timer.
13,
12
7,
6
13,
12
P05/SI,
P06/SO
General-purpose CMOS I/O ports
These port inputs are a hysteresis input, with a built-in
noise canceller. Also serve as serial data outputs for
the 8-bit serial interface.
11
5
11
P07/SCK
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in
noise canceller. Also serves as the serial transfer
clock output for the 8-bit serial interface.
47 to 40 41 to 34 63 to 56 P10 to P17
P-ch high-voltage open-drain output ports for large
current
(Continued)
*1: DIP-48P-M01
*2: FPT-48P-M15
*3: MDP-64C-P02
8
MB89910 Series
(Continued)
Pin no.
QFP*2
Circuit
type
Pin name
Function
SH-
MDIP*3
DIP*1
38 to 31 32 to 25 54 to 47 P20 to P27
G
H
P-ch high-voltage open-drain output ports for small
current
10 to 7
6 to 3
4 to 1
10 to 7 P30/AN0 to
P33/AN3
General-purpose N-ch open-drain I/O ports
These port inputs are a hysteresis input, each with a
built-in noise canceller. Although the pins are also
serve as an analog inputs, an analog input does not
pass through their noise cancellers.
48 to 45
6 to 3
P34/AN4 to
P37/AN7
F
General-purpose CMOS I/O ports
These port inputs are a hysteresis input, each with a
built-in noise canceller. Although the pins are also serve
as an analog inputs, an analog input does not pass
through their noise cancellers.
23
22
21
17
16
15
23
22
21
P40/INT0
P41/INT1
P42
D
E
E
General-purpose CMOS I/O port
This port input is a hysteresis input, with a built-in noise
canceller. Also serves as an external interrupt. External
interrupt input passes through the noise canceller.
General-purpose N-ch open-drain I/O port
This port input is a hysteresis input, with a built-in noise
canceller. Also serves as an external interrupt. External
interrupt input passes through the noise canceller.
General-purpose N-ch open-drain I/O port
This port input is a hysteresis input, with a built-in noise
canceller.
30
29
24
23
46
45
P50
G
G
P-ch high-voltage open-drain output ports for small
current
P51/BZ1
P-ch high-voltage open-drain output port for small
current
Also serves as a buzzer output.
28
39
22
33
44
55
TEST
VFDP
B
Operating mode selection pin
Usually, connect to VSS directly. On the product with an
EPROM, the pin is the VPP pin.
—
Voltage supply pin connected to a pull-down resistor for
ports 1, 2, and 5 In products without a pull-down
resistor, in the MB89P915, and in the MB89PV910, this
pin should be left open.
(Continued)
*1: IP-48P-M01
*2: FPT-48P-M15
*3: MDP-64C-P02
9
MB89910 Series
(Continued)
Pin no.
Circuit
type
Pin name
Function
SH-
QFP*2
MDIP*3
DIP*1
48
25
1
42
19
43
64
32,41
1
VCC
VSS
—
—
—
Power supply pin
Power supply (GND) pin
AVSS
A/D converter power supply pin
Use this pin at the same voltage as VSS.
2
44
2
AVR
—
A/D converter reference voltage input pin
*1: IP-48P-M01
*2: FPT-48P-M15
*3: MDP-64C-P02
10
MB89910 Series
• External EPROM pins (MDIP only)
Pin no.
Pin name
I/O
Function
MDIP*
65
VPP
O
O
“H” level output pin
Address output pins
66
67
68
69
70
71
72
73
74
A12
A7
A6
A5
A4
A3
A2
A1
A0
75
76
77
O1
O2
O3
I
Data input pins
78
VSS
O
I
Power supply (GND) pin
Data input pins
79
80
81
82
83
O4
O5
O6
O7
O8
84
CE
O
ROM chip enable pin
Outputs “H” during standby.
85
86
A10
OE
O
O
Address output pin
ROM output enable pin
Outputs “L” at all times.
87
88
89
A11
A9
A8
O
Address output pin
90
91
92
A13
A14
VCC
O
O
O
EPROM power supply pin
* : MDP-64C-P02
11
MB89910 Series
■ I/O CIRCUIT TYPE
Type
Circuit
Remarks
A
• Main clock
X1
X0
At an oscillation feedback resistor of approximately
1 MΩ/5.0 V
N-ch
P-ch
Main clock control signal
B
C
• At an output pull-up resistor (P-ch) of approximately
50 kΩ/5.0 V
• CMOS hysteresis input (with a noise canceller)
R
P-ch
N-ch
Hysteresis input (with a noise canceller)
D
• CMOS I/O
• CMOS hysteresis input (with a noise canceller)
P-ch
N-ch
Hysteresis input (with a noise canceller)
E
• N-ch open-drain I/O
• CMOS hysteresis input (with a noise canceller)
N-ch
Hysteresis input (with a noise canceller)
(Continued)
12
MB89910 Series
(Continued)
Type
Circuit
Remarks
F
• CMOS output
P-ch
• CMOS hysteresis input (with a noise canceller
excluding analog inputs)
N-ch
Port
Hysteresis input (with a noise canceller)
Analog input
G
• P-ch high-voltage open-drain output
• At an output pull-down resistor of approximately
100 kΩ/5.0 V
P-ch
VFDP
H
• N-ch open-drain output
• CMOS hysteresis input (with a noise canceller
excluding analog inputs)
N-ch
Hysteresis input (with a noise canceller)
Analog input
I
• Subclock
Port
The oscillation feedback resistor is built only in the
MB89PV910.
• CMOS hysteresis input (with a noise canceller)
when no subclock is being used
Hysteresis input (with a noise canceller)
X1A
X0A
N-ch
P-ch
Subclock control signal
Port
Hysteresis input (with a noise canceller)
13
MB89910 Series
■ HANDLING DEVICES
1. Preventing Latchup
Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins
other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum
Ratings” in section “■ Electrical Characteristics” is applied between VCC and VSS.
When latchup occurs, power supply current increases rapidly and might thermally damage elements. When
using, take great care not to exceed the absolute maximum ratings.
Also, take care to prevent the analog power supply (AVCC and AVR) and analog input from exceeding the digital
power supply (VCC) when the analog system power supply is turned on and off.
2. Treatment of Unused Input Pins
Leaving unused input pins open could cause malfunctions. They should be connected to a pull-up or pull-down
resistor.
3. Treatment of Power Supply Pins on Microcontrollers with A/D and D/A Converters
Connect to be AVCC = DAVC = VCC and AVSS = AVR = VSS even if the A/D and D/A converters are not in use.
4. Treatment of N.C. Pins
Be sure to leave (internally connected) N.C. pins open.
5. Power Supply Voltage Fluctuations
Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage
couldcausemalfunctions, evenifitoccurswithintheratedrange. StabilizingvoltagesuppliedtotheICistherefore
important. As stabilization guidelines, it is recommended to control power so that VCC ripple fluctuations (P-P
value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient
fluctuationratewillbelessthan0.1V/msatthetimeofamomentaryfluctuationsuchaswhenpowerisswitched.
6. Precautions when Using an External Clock
When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and
wake-up from stop mode.
14
MB89910 Series
■ PROGRAMMING TO EPROM ON THE MB89P915
The MB89P915 is an OTPROM version of the MP89910 series.
1. Features
• 16-Kbyte PROM on chip
2. Memory Space
Memory space in each mode such as 16-Kbyte PROM mode is diagrammed below.
EPROM mode
(Corresponding addresses on the EPROM programmer)
MB89P915
I/O
0000H
0080H
RAM
0280H
8000H
Not available
0000H
Not available
(Read value FFH)
Free space
(Read value FFH)
4000H
C000H
Program area
(PROM)
Program area
(PROM)
16 KB
16 KB
FFFFH
7FFFH
3. Programming to the EPROM
Since the MB89P915 requires a special method for programming to its PROM, the types of general-purpose
EPROM programmers applicable to the MB89P915 are limited. Programming to the PROM on the MB89P915
requires an EPROM programmer applicable to the MB89P915 and a dedicated adapter.
When the operating ROM area for a single chip is 16 Kbytes (C000H to FFFFH) the PROM can be programmed
as follows:
• Programming procedure
(1) Set the EPROM programmer to the MB89P195.
(2) Load program data into the EPROM programmer at 4000H to 7FFFH. (note that addresses 0C000H to 0FFFFH
in the operation mode correspond to 4000H to 7FFFH in EPROM mode.)
(3) Program with the EPROM programmer.
15
MB89910 Series
4. Recommended Screening Conditions
High-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked
OTPROM microcomputer program.
Program, verify
Aging
+150°C, 48 Hrs.
Data verification
Assembly
5. Programming Yield
All bits cannot be programmed at Fujitsu shipping test to a blanked OTPROM microcomputer, due to its nature.
For this reason, a programming yield of 100% cannot be assured at all times.
6. EPROM Programmer Socket Adapter and Recommended Programmer Manufacturer
Recommended programmer manufac-
turer
and programmer name
Compatible socket adapter
Part no.
Package
Data I/O Co., Ltd.
Sun Hayato Co., Ltd.
UNISITE
(ver.5.0 or
later)
3900
(ver.2.8 or
later)
2900
(ver.3.8 or
later)
MB89P915P-SH SH-DIP-48 ROM-48QF2-28DP-8L
Recommended
Inquiry: Sun Hayato Co., Ltd.: TEL: (81)-3-3986-0403
FAX: (81)-3-5396-9106
Data I/O Co., Ltd.: TEL: USA/ASIA (1)-206-881-6444
EUROPE (49)-8-985-8580
16
MB89910 Series
■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE
1. EPROM for Use
MBM27C256A-20CZ
2. Programming Socket Adapter
Any special programming adapter is not required since the package for the EPROM to be used is DIP-28.
3. Memory Space
EPROM memory space and the memory space on the MB89PV910 are diagrammed below.
MB89PV910
0000H
I/O
0080H
RAM
0480H
Not available
MBM27C256A-20CZ
0000H
8000H
Program area
(EPROM)
32 KB
Program area
32 KB
FFFFH
7FFFH
4. Programming to the EPROM
(1) Set the EPROM programmer to the MBM27C256A-20CZ.
(2) Load program data into the EPROM programmer at 0000H to 7FFFH. (note that addresses 08000H to 0FFFFH
in the operation mode correspond to 0000H to 7FFFH in the EPROM mode.)
(3) Program with the EPROM programmer.
17
MB89910 Series
■ BLOCK DIAGRAM
Timebase timer
Main clock
oscillator
X0
X1
Reset circuit
(Watchdog timer)
RST
VFDP
Clock controller
8
8
High-voltage output
P10 to P17
P20 to P27
port 1
X0A/P60
X1A/P61
Subclock oscillator
(32.768 kHz)
High-voltage output
port 2
CMOS input port
High-voltage output
port 5
P50
P51/BZ1
Watch prescaler
Buzzer output
P01/BZ2
P02/ADST
Low-voltage
detection reset
CMOS I/O port
P00
N-ch open-drain I/O port
P07/SCK
P06/SO
P05/SI
P30/AN0 to
P33/AN3
8-bit serial I/O
4
4
8-bit A/D
converter
AVR
AVSS
8-bit PWM timer
P04/PWO
P03/EC
P34/AN4 to
P37/AN7
16-bit timer/counter
CMOS I/O port
RAM
N-ch open-drain output port
P42
F2MC-8L
CPU
P41/INT1
External interrupt
CMOS I/O port
P40/INT0
ROM
Other pins
VCC, VSS, TEST
18
MB89910 Series
■ CPU CORE
1. Memory Space
The microcontrollers of the MB89910 series offer a memory space of 64 Kbytes for storing all of I/O, data, and
program areas. The I/O area is located the lowest address. The data area is provided immediately above the I/
O area. The data area can be divided into register, stack, and direct areas according to the application. The
program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of
interrupt reset vectors and vector call instructions toward the highest address within the program area.
• Memory Space
MB89P915
MB89915
MB89PV910
I / O
MB89913
I / O
0000 H
0080 H
0000 H
0080 H
0100 H
0000 H
0080 H
I / O
RAM
1 KB
RAM
512 B
0100 H
0200 H
0100 H
0180 H
Register
Register
Register
0200 H
0280 H
0480 H
8000 H
Not available
Not available
Not available
C000 H
External ROM
32 KB
E000 H
FFFF H
ROM*
16 KB
ROM
8 KB
FFFF H
FFFF H
*: This is an internal PROM on the MB89P915.
19
MB89910 Series
2. Registers
The F2MC-8L family has two types of registers; dedicated registers in the CPU and general-purpose registers
in the memory. The following registers are provided:
Program counter (PC):
Accumulator (A):
A 16-bit register for indicating instruction storage positions
A 16-bit temporary register for storing arithmetic operations, etc. When the
instruction is an 8-bit data processing instruction, the lower byte is used.
Temporary accumulator (T): A 16-bit register which performs arithmetic operations with the accumulator
Whentheinstructionisan8-bitdataprocessinginstruction, thelowerbyteisused.
Index register (IX):
Extra pointer (EP):
Stack pointer (SP):
Program status (PS):
A 16-bit register for index modification
A 16-bit pointer for indicating a memory address
A 16-bit register for indicating a stack area
A 16-bit register for storing a register pointer, a condition code
16 bits
PC
Initial value
FFFDH
: Program counter
: Accumulator
A
T
Indeterminate
: Temporary accumulator Indeterminate
IX
: Index register
: Extra pointer
: Stack pointer
: Program status
Indeterminate
Indeterminate
Indeterminate
EP
SP
PS
I-flag = 0, IL1, 0 = 11
The other bit values are indeterminate.
The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for
use as a condition code register (CCR). (See the diagram below.)
• Structure of the Program Status Register
15
14
13
12
11
10
9
8
7
6
I
5
4
3
2
Z
1
0
PS
RP
Vacancy Vacancy Vacancy
H
IL1, 0
N
V
C
RP
CCR
20
MB89910 Series
The RP indicates the address of the register bank currently in use. The relationship between the pointer contents
and the actual address is based on the conversion rule illustrated below.
• Rule for Conversion of Actual Addresses of the General-purpose Register Area
Lower OP codes
RP
“0” “0” “0” “0” “0” “0” “0” “1” R4 R3 R2 R1 R0 b2 b1 b0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
Generated addresses A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and
bits for control of CPU operations at the time of an interrupt.
H-flag: Set to ‘1’ when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. Cleared
to ‘0’ otherwise. This flag is for decimal adjustment instructions.
I-flag: Interruptisenabledwhenthisflagissetto‘1’. Interruptisdisabledwhentheflagisclearedto‘0’. Cleared
to ‘0’ at the reset.
IL1, 0: Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is
higher than the value indicated by this bit.
IL1
0
IL0
0
Interrupt level
High-low
High
1
0
1
1
0
2
3
1
1
Low
N-flag: Set to ‘1’ if the MSB becomes to ‘1’ as the result of an arithmetic operation. Cleared to ‘0’ when the bit
is cleared to ‘0’.
Z-flag: Set to ‘1’ when an arithmetic operation results in 0. Cleared to ‘0’ otherwise.
V-flag: Set to ‘1’ if the complement on 2 overflows as a result of an arithmetic operation. Cleared to to ‘0’ if the
overflow does not occur.
C-flag: Set to ‘1’ when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to
‘0’ otherwise. Set to the shift-out value in the case of a shift instruction.
21
MB89910 Series
The following general-purpose registers are provided:
General-purpose registers: An 8-bit resister for storing data
The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains
eight registers and up to a total of 32 banks can be used on the MB89915. The bank currently in use is indicated
by the register bank pointer (RP).
• Register Bank Configuration
This address = 0100H + 8 × (RP)
R 0
R 1
R 2
R 3
R 4
R 5
R 6
R 7
32 banks
Memory area
22
MB89910 Series
■ I/O MAP
Address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Read/write
(R/W)
Register name
PDR0
Register description
Port 0 data register
(W)
DDR0
Port 0 data direction register
Vacancy
Vacancy
Vacancy
Vacancy
Vacancy
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(W)
SYCC
STBC
WDTC
TBCR
WPCR
PDR3
DDR3
BUZR
EIC
System clock control register
Standby control register
Watchdog timer control register
Time-base timer control register
Watch prescaler control register
Port 3 data register
Port 3 direction register
Buzzer register
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R)
External interrupt control register
Port 1 data register
PDR1
PDR2
PDR5
PDR6
PDR4
DDR4
COMR
CNTR
TMCR
TCHR
TCLR
Port 2 data register
Port 5 data register
Port 6 data register
(R/W)
(W)
Port 4 data register
Port 4 direction register
PWM compare register
PWM control register
16-bit timer control register
16-bit timer control register (H)
16-bit timer control register (L)
Vacancy
(W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
(R/W)
SMR
SDR
Serial mode register
Serial data register
ADC1
ADC2
A/D converter control register 1
A/D converter control register 2
(Continued)
23
MB89910 Series
(Continued)
Address
20H
Read/write
Register name
Register description
A/D converter data register
(R/W)
ADCD
21H
Vacancy
22H
(W)
PCR
Port input control register
Low-voltage detection reset control register
Vacancy
23H
(R/W)
LVRC
24H to 7BH
7CH
(W)
(W)
(W)
ILR1
ILR2
ILR3
Interrupt level setting register 1
Interrupt level setting register 2
Interrupt level setting register 3
Vacancy
7DH
7EH
7FH
Note: Do not use vacancies.
24
MB89910 Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
AVR ≤ VCC + 0.3*1
Parameter
Min.
Max.
VCC
AVR
VSS – 0.3
VSS + 7.0
V
Power supply voltage
VPP
– 0.6
13.0
VCC + 0.3
VCC + 0.3
7.0
V
V
V
V
VFDP
VI1
VCC – 40
VSS – 0.3
VSS – 0.3
Except P41*2
P41
Input voltage
VI2
Except P10 to P17,
VO1
VSS – 0.3
VCC + 0.3
VCC + 0.3
–120
V
V
P20 to P27, P50, P51*2
Output voltage
P10 to P17, P20 to P27
P50, P51
VO2
VCC – 40.0
“H” level total maximum output
current
∑IOH
∑IOHAV
mA
mA
“H” level total average output
current
Average value (operating
current × operating rate)
–90
–12
–20
–36
mA P00 to P07, P34 to P37, P40
mA P20 to P27, P50, P51
mA P10 to P17
“H” level maximum output current IOH
P00 to P07, P34 to P37, P40
mA Average value (operating
current × operating rate)
–6
P20 to P27, P50, P51
mA Average value (operating
current × operating rate)
“H” level average output current
IOHAV
–10
–20
P10 to P17
mA Average value (operating
current × operating rate)
“L” level total maximum output
current
∑IOL
36
20
mA
“L” level total average output
current
Average value (operating
mA
∑IOLAV
current × operating rate)
“L” level maximum output current IOL
“L” level average output current
10
4
mA
P00 to P07, P30 to P37,
P40 to P47
IOLAV
mA
(Continued)
25
MB89910 Series
(Continued)
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
—
Max.
440
mW SH-DIP: DIP-48-M01
Power consumption
PD
—
360
mW QFP: FPT-48-M15
Operating temperature
Storage temperature
TA
–40
–55
+85
°C
°C
Tstg
+150
*1: Take care so that AVR does not exceed VCC + 0.3 V and VCC does not exceed VCC, such as when power is turned
on.
*2: VI and VO must not exceed VCC + 0.3 V.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, tem-
perature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V)
Value
Symbol
Unit
Remarks
Parameter
Min.
Max.
Normal operation assurance
range*(MB89PV910)
4.5*
5.5*
V
Normal operation assurance
range*(MB89P915/915/913)
3.8*
2.7
1.5
5.5*
5.5
5.5
V
V
V
Power supply voltage
VCC
Watch mode, sub-RUN mode
Retains the RAM state in stop
mode
A/D converter reference
input voltage
AVR
0.0
VCC
V
High-voltage pull-down
resistor supply voltage
VFDP
TA
VCC – 35.0
–40
VCC + 0.3
+85
V
Operating temperature
°C
* : These values vary with the operating frequency, instruction cycle, and analog assurance range. See Figure 1
and “5. A/D Converter Electrical Characteristics.”
26
MB89910 Series
Figure 1 Operating Voltage vs. Main Clock Operating Frequency
6
5
Operation assurance range
4
3
2
1
2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0
Main clock operating frequency (at an instruction cycle of 4/FCH) (MHz)
(µs)
2.0 1.3 1.0 0.8 0.66 0.57 0.5 0.44 0.4
Minimum execution time (instruction cycle)
Figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/FCH.
Since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the
operating speed is switched using a gear.
WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All
the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
27
MB89910 Series
3. DC Characteristics
(AVR = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61
VCC +
0.3
“H” level
input voltage
VIHS
—
0.8 VCC
—
V
X0, RST
X1, TEST
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61
VSS −
0.3
“L” level
input voltage
VILS
—
—
0.2 VCC
V
X0, RST
X1, TEST
VSS −
0.3
VCC +
0.3
P30 to P33,
P42
Open-drain
output pin
application
voltage
VD1
VD2
—
—
—
—
V
V
VSS −
0.3
P41
7.0
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61
Excluding
P30 to P33 and
P41, P42
VOH1
IOH = –2.0 mA
IOH = –10 mA
2.4
—
—
V
“H” level
output voltage
P20 to P27,
P50, P51
VOH2
VOH3
3.0
3.0
—
—
—
—
V
V
P10 to P17 IOH = –20 mA
P00 to P07,
P30 to P37,
IOL = 1.8 mA
P40 to P42,
P60, P61
VOL1
VOL2
ILI1
—
—
—
—
—
—
0.4
0.6
±5
V
V
“L” level
output voltage
RST,
IOL = 4.0 mA
0 < VI < VCC
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61
Input leakage
current
µA
VFDP = VCC –
35.0 V
P20 to P27,
P50, P51
ILO1
VI = VFDP
—
—
25
—
—
50
–10
–20
100
µA
µA
kΩ
Output leakage
current
VFDP = VCC –
35.0 V
ILO2
P10 to P17 VI = VFDP
Pull-up
resistance
RPULL
RST,
VIN = 0.0 V
Assuming the
pull-down
resistor option
selected
P10 to P17,
P20 to P27, VIN = 5.0 V
P50, P51
Pull-down
resistance
RPD
50
100
150
kΩ
(Continued)
28
MB89910 Series
(Continued)
(AVR = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
FCH = 8 MHz
—
10.0
18.0
mA MB89P915
VCC = 5.0 V
*2
ICC1
tinst = 0.5 µs
MB89913/
mA
when A/D conversion
is stopped
—
—
—
9
15
6.0
2.4
915/PV910
FCH = 8 MHz
VCC = 3.8 V
tinst*2 = 8.0 µs
when A/D conversion
is stopped
3.0
1.8
mA MB89P915
ICC2
MB89913/
mA
915/PV910
FCH = 8 MHz
VCC = 5.0 V
*2
tinst = 0.5 µs
ICS1
—
—
3
7
mA
when A/D
conversion is
stopped
Power supply
current*1
FCH = 8 MHz
VCC = 3.8 V
*2
When low-
voltage
tinst = 8.0 µs
ICS2
1.2
1.8
mA
when A/D
conversion is
stopped
detection reset
operation is
enabled, ILVD is
added to each
power supply
current.
VCC
—
—
1.2
60
3.6
mA MB89P915
FCL = 32 kHz
VCC = 3.0 V
Subclock mode
ICSB
MB89913/
µA
180
915/PV910
FCL = 32 kHz
VCC = 3.0 V
Subclock sleep mode
ICS3
—
—
32
4
64
20
µA
µA
FCL = 32 kHz
VCC = 3.0 V
• Watch mode
• Main clock stop
mode at dual- clock
system
ICCT
FCH = 8 MHz
TA = +25°C
VCC = 5.0 V
ICCA
—
12.5
22.5
mA
*2
tinst = 0.5 µs
when A/D conversion
is activated
(Continued)
29
MB89910 Series
(Continued)
(AVR = VCC = +5.0 V, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Sym-
bol
Parameter
Pin name
Condition
Unit
Remarks
Min.
Typ.
Max.
FCL = 32.678 kHz,
VCC = 3.0 V
TA = +25°C,
• Subclock stop
mode
ICCH
—
—
10
µA
• Main clock stop
mode at single
clock system
Power supply
current*1
VCC
VCC = 5.0 V
TA = +25°C,
• Subclock stop
mode
• Main clock stop
mode at single
clock system
When low-
voltage
Power
consumption
µA of low-voltage
detection
ILVD
—
—
60
120
—
detection reset
operation is
enabled, ILVD is
added to each
power supply
current.
reset
FCH = 8 MHz,
TA = +25°C,
when A/D conversion
is activated
IR
AVR
200
µA
FCH = 8 MHz,
TA = +25°C,
when A/D conversion
is stopped
IRH
AVR
—
—
—
10
—
µA
Other than
Input
capacitance
CIN
AVSS, AVR, f = 1 MHz
VCC, and VSS
10
pF
*1: The power supply current is measured at external clock.
*2: For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
30
MB89910 Series
4. AC Characteristics
(1) Reset Timing
(AVR = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Condition
Unit
Remarks
Parameter
Min.
48 tXCYL
30
Typ.
—
Max.
—
RST “L” pulse width
RST noise limit width
tZLZH
tZLNC
—
—
ns
ns
50
80
Note: tXCYL is the oscillation period (1/FCH) to input to the X0.
tZLZH
tZLNC
RST
0.2 VCC
0.2 VCC
(2) Power-on Reset
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol Condition
Unit
Remarks
Parameter
Min.
—
Max.
50
Power supply rising time
Power supply cut-off time
tR
—
—
ms
ms
Power-on reset function only
Due to repeated operations
tOFF
1
—
Note: Make sure that power supply rises within the selected oscillation stabilization time.
If power supply voltage needs to be varied in the course of operation, a smooth voltage rise is
recommended.
tOFF
tR
2.0 V
0.2 V
VCC
0.2 V
0.2 V
31
MB89910 Series
(3) Clock Timing
(AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Typ.
—
Symbol Pin name Condition
Unit
Remarks
Parameter
Min.
2
Max.
8
FCH
X0, X1
—
—
—
—
MHz
kHz
ns
Clock frequency
FCL
X0A, X1A
X0, X1
—
32.768
—
—
tXCYL
tLXCYL
125
—
500
—
Clock cycle time
X0A, X1A
30.5
µs
PWH
PWL
X0
—
—
—
30
—
—
—
15.2
—
—
—
10
ns
Input clock pulse width
External clock
PWHL
PWLL
X0A
µs
tCR
tCF
Input clock rising/falling time
X0, X0A
ns External clock
• X0 and X1 Timing and Conditions
tXCYL
tCF
PWH
PWL
tCR
0.8 VCC
0.8 VCC
X 0
0.2 VCC
0.2 VCC
0.2 VCC
• Main Clock Conditions
When a crystal
or
ceramic resonator is used
When an external clock is used
X0
X1
X0
X1
Open
C 0
C 1
32
MB89910 Series
• X0A and X1A Timing and Conditions
tLXCYL
PWLL
PWHL
tCR
tCF
0.8 VCC
0.8 VCC
X0A
0.2 VCC
0.2 VCC
0.2 VCC
• Subclock Conditions
When a crystal
or
When a crystal
or
ceramic resonator is used
ceramic resonator is used
When an external clock is used
MB89PV910
MB89913/915/P915
X0A
X1A
X0A
X1A
X0A
X1A
Open
RF
RD
C0
C1
C0
C1
(4) Instruction Cycle
Parameter
Symbol
Value (typical)
Unit
Remarks
Operation at FCH = 8 MHz;
(4/FCH)tinst = 0.5 µs
4/FCH, 8/FCH, 16/FCH, 32/FCH
2/FCL
µs
Instruction cycle
(minimum execution time)
tinst
Operation at FCL = 32.768 kHz;
(4/FCH)tinst = 61.036 µs
µs
Note: When operating at 8 MHz, the cycle varies with the execution time.
33
MB89910 Series
(5) Low-voltage Detection Reset
(AVSS = VSS 0.0 V, TA = –40°C to +85°C)
Value
Min.
Symbol
Condition
Unit
Remarks
Parameter
Max.
3.60
3.90
4.40
3.80
4.10
4.60
—
VDL1
VDL2
VDL3
VDH1
VDH2
VDH3
∆V
—
—
—
—
—
—
—
—
—
—
—
3.00
3.30
3.70
3.10
3.40
3.80
0.10
0.3
V
V
Detection voltage at power
supply voltage fall
VDH and VDL are set for
the MB89913/915 by
mask options and for
the MB89P915 by a
register.
V
V
Detection voltage at power
supply voltage rise
V
V
Hysteresis width
V
Reset insensitive time
Reset sensitive width
Reset detection delay time
Voltage regulation (V∆/t∆)
tL
—
µs
ns
µs
V/µs
tLW
16 tXCYL
—
—
tD
2.0
VCR
—
0.10
Power supply voltage
t ∆
VCC
VDH
V ∆
∆ V
VDL
tOSC
tD
tOSC
tD
RUN
RESET
tOSC oscillation stabilization time 218 = 32.8 ms (FCH = 8 MHz)
Power supply voltage
VCC
t LW or less
t L or less
VDH
VDL
t
t
RUN
RESET
Reset not applied
Reset applied
34
MB89910 Series
(6) Serial I/O Timing
Parameter
(AVR = VCC = +5.0 V±10%, AVSS = VSS= 0.0 V, TA = –40°C to +85°C)
Value
Symbol Pin name
Condition
Unit Remarks
Min.
2 tinst*
–200
Max.
—
Serial clock cycle time
SCK ↓ → SO time
tSCYC
tSLOV
tIVSH
tSHIX
tSHSL
tSLSH
tSLOV
tIVSH
tSHIX
SCK
µs
ns
µs
µs
µs
µs
ns
µs
µs
SCK, SO
SI, SCK
SCK, SI
SCK
200
—
Internal shift
clock mode
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
1 tinst*
1 tinst*
0
SCK ↑ → valid SI hold time
Serial clock “H” pulse width
Serial clock “L” pulse width
SCK ↓ → SO time
—
—
SCK
—
External shift
clock mode
SCK, SO
SI, SCK
SCK, SI
200
—
Valid SI → SCK ↑
1/2 tinst*
1/2 tinst*
SCK ↑ → valid SI hold time
—
* : For information on tinst, see “(4) Instruction Cycle.”
35
MB89910 Series
• Internal Shift Clock Mode
tSCYC
SCK
2.4 V
0.8 V
0.8 V
tSLOV
2.4 V
0.8 V
SO
tIVSH
tSHIX
SI
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
• External Shift Clock Mode
tSLSH
tSHSL
SCK
0.8 VCC
0.8 VCC
0.2 VCC
0.2 VCC
tSLOV
SO
2.4 V
0.8 V
tIVSH
0.8 VCC
0.2 VCC
tSHIX
0.8 VCC
0.2 VCC
SI
36
MB89910 Series
(7) Peripheral Input Timing
Parameter
(AVR = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
tILIH
tIHIL
Pin name
Condition
Unit Remarks
Min.
Max.
Peripheral input “H” level pulse
width
EC, ADST
INT0, INT1
2 tinst*
—
µs
µs
—
Peripheral input “L” level pulse
width
EC, ADST
INT0, INT1
2 tinst*
—
* : For information on tinst, see “(4) Instruction Cycle.”
tIHIL
tILIH
INT0, INT1
EC
0.8 VCC
0.8 VCC
ADST
0.2 VCC
0.2 VCC
(8) Peripheral input noise limit width
(AVR = VCC = +5.0 V±10%, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Symbol
Pin name
Unit
Remarks
Parameter
Min.
Typ. Max.
MB89PV910
MB89P915
7
15
30
30
60
ns
ns
ns
ns
ns
ns
ns
ns
Peripheral input “H” level
noise limit width 1
All inputs excluding
INT1 and INT0
tIHNC1
MB89913/
915
15
7
MB89PV910
MB89P915
15
30
Peripheral input “L” level
noise limit width 1
All inputs excluding
INT1 and INT0
tILNC1
tIHNC2
tILNC2
MB89913/
915
15
30
50
30
50
30
60
MB89PV910
MB89P915
50
100
250
100
250
Peripheral input “H” level
noise limit width 2
INT1, INT0
INT1, INT0
MB89913/
915
100
50
MB89PV910
MB89P915
Peripheral input “L” level
noise limit width 2
MB89913/
915
100
Note: The minimum rating is always cancelled, while values equal to or greater than maximum ratings are not
cancelled.
P00 to P07,
P30 to P37,
P40 to P42,
P60, P61,
SCK, SI, EC
INT0, INT1
ADST
tIHNC1
tIHNC2
tILNC1
tILNC2
0.8 VCC
0.2 VCC
0.8 VCC
0.2 VCC
37
MB89910 Series
5. A/D Converter Electrical Characteristics
(VCC = +3.8 V to +5.5 V, F = 8 MHz, AVSS = VSS = 0.0 V, TA = –40°C to +85°C)
Value
Typ.
—
Sym-
bol
Remar
ks
Parameter
Resolution
Pin name
Condition
Unit
Min.
—
Max.
8
bit
Total error
—
—
±3.0
±1.0
LSB
LSB
—
—
Linearity error
—
—
Differential linearity
error
—
—
±0.9
LSB
mV
AN0 to
AN7
AVSS – 1.5
LSB
AVSS +0.5
LSB
AVSS + 2.5
LSB
Zero transition voltage
VOT
—
AN0 to
AN7
Full-scale transition
voltage
AVR – 3.5
LSB
AVR – 1.5
LSB
AVR +0.5
LSB
VFST
mV
LSB
µs
Interchannel disparity
—
—
—
—
1.0
—
A/D mode conversion
time
44 tinst*
—
—
Sense mode
conversion time
12 tinst*
—
—
µs
Analog port input
current
AN0 to
AN7
AVR = VCC = 5.0
V
IAIN
—
IR
—
10
µA
AN0 to
AN7
Analog input voltage
Reference voltage
0.0
3.4
—
—
—
AVR
AVCC
—
V
V
—
AVR
AVR
Reference voltage
supply current
AVR = 5.0 V
200
µA
* : For information on tinst, see “(4) Instruction Cycle” in “4. AC Characteristics.”
6. A/D Converter Glossary
• Resolution
Analog changes that are identifiable with the A/D converter
When the number of bits is 8, analog voltage can be divided into 28 = 256.
• Linearity error (unit: LSB)
The deviation of the straight line drawn connecting the zero transition point (“0000 0000 ” ↔ “0000 0001”) with
the full-scale transition point (“1111 1111 ” ↔ “1111 1110”) from actual conversion characteristics
• Differential linearity error (unit: LSB)
The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value
• Total error (unit: LSB)
The difference between theoretical and actual conversion values
38
MB89910 Series
Digital output
Theoretical conversion value
Actual conversion value
1111 1111
1111 1110
•
•
(1 LSB × N + VOT)
•
•
•
AVR
256
1 LSB =
•
•
•
VNT – (1 LSB × N + VOT)
Linearity error =
1 LSB
•
•
•
•
V( N + 1 ) T – VNT
– 1
Differential linearity error =
Total error =
1 LSB
Linearity error
VNT – (1 LSB × N + 0.5 LSB)
1 LSB
•
0000 0010
0000 0001
0000 0000
VOT
VNT V(N + 1)T
VFST
Analog input
7. Notes on Using A/D Converter
• Input impedance of the analog input pins
The A/D converter used for the MB89910 series contains a sample hold circuit as illustrated below to fetch
analog input voltage into the sample hold capacitor for eight instruction cycles after activating A/D conversion.
For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage
might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output
impedance of the external circuit low. If a higher accurancy is required, set the output impedance in this series
to 2 kΩ or less.
Note that if the impedance cannot be kept low output impedance, it is recommended either to use the software
to continuously activate the A/D converter for simulating longer sampling time or to connect an external
capacitor of approx. 0.1 µF to the analog input pin.
Sample hold circuit
• Analog Input Equivalent Circuit
.
C = 33 pF
.
Analog input pin
Comparator
If the output
impedance of external
circuit is high, it is
recommended to
connect an external
capacitor of approx.
0.1 µF.
.
R = 6 kΩ
.
Close for 8 instruction cycles after activating
A/D conversion.
Analog channel selector
• Error
The smaller the | AVR – AVSS |, the greater the error would become relatively.
39
MB89910 Series
■ EXAMPLE CHARACTERISTICS
(1) “L” Level Output Voltage
(2) “H” Level Output Voltage
VOL vs. IOL
VCC – VOH vs. IOH
VCC – VOH (V)
1.0
VOL (V)
VCC = 2.5 V
TA = +25°C
TA = +25°C
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
VCC = 2.5 V
VCC = 3.0 V
0.5
VCC = 3.0 V
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.4
0.3
0.2
0.1
0.0
VCC = 4.0 V
VCC = 5.0 V
VCC = 6.0 V
0.0
–0.5 –1.0 –1.5 –2.0 –2.5 –3.0
IOH (mA)
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
(3) “H” Level Input Voltage/“L” Level Input Voltage (Hysteresis Input)
CMOS hysteresis input
VIN (V)
5.0
TA = +25°C
4.5
4.0
3.5
VIHS
3.0
2.5
VILS
2.0
1.5
1.0
0.5
0.0
0
1
2
3
4
5
6
7
VCC (V)
VIHS: Threshold when input voltage in hysteresis characteristics is set to “H” level
VILS: Threshold when input voltage in hysteresis characteristics is set to “L” level
40
MB89910 Series
(4) Power Supply Current (External Clock)
ICC1 vs. VCC, ICC2 vs. VCC
ICC1,ICC2 (mA)
ICS1 vs. VCC, ICS2 vs. VCC
ICS, ICS2 (mA)
FCH = 8 MHz
FCH = 8 MHz
TA = +25°C
16
4.0
3.0
2.0
TA = +25°C
14
Divide by 4 (ICC1)
Divide by 4 (ICS1)
Divide by 64 (ICS2)
12
10
8
6
Divide by 64 (ICC2)
4
1.0
0
2
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
5.0
6.0
7.0
VCC (V)
VCC (V)
ICSB vs. VCC
ICS3 vs. VCC
ICSB (µA)
ICS3 (µA)
50
200
180
160
140
120
100
80
TA = +25°C
TA = +25°C
40
30
20
10
60
40
20
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
5.0
6.0
7.0
VCC (V)
VCC (V)
(Continued)
41
MB89910 Series
(Continued)
ICCT vs. VCC
ICCH vs. VCC
ICCT (µA)
ICCH (µA)
36
32
28
1.8
TA = +25°C
TA = +25°C
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
24
20
16
12
8
4
0
0
2.0
3.0
4.0
5.0
6.0
7.0
2.0
3.0
4.0
5.0
6.0
7.0
VCC (V)
VCC (V)
(5) Pull-up Resistance
RPULL vs. VCC
RPULL (kΩ)
1,000
500
100
50
TA = +85°C
TA = +25°C
TA = –40°C
10
1
2
3
4
5
6
7
VCC (V)
42
MB89910 Series
■ INSTRUCTIONS
Execution instructions can be divided into the following four groups:
• Transfer
• Arithmetic operation
• Branch
• Others
Table 1 lists symbols used for notation of instructions.
Table 1 Instruction Symbols
Symbol
dir
Meaning
Direct address (8 bits)
off
Offset (8 bits)
ext
Extended address (16 bits)
Vector table number (3 bits)
Immediate data (8 bits)
Immediate data (16 bits)
Bit direct address (8:3 bits)
Branch relative address (8 bits)
#vct
#d8
#d16
dir: b
rel
@
Register indirect (Example: @A, @IX, @EP)
A
Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)
Upper 8 bits of accumulator A (8 bits)
AH
AL
Lower 8 bits of accumulator A (8 bits)
Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the
instruction in use.)
T
TH
TL
IX
Upper 8 bits of temporary accumulator T (8 bits)
Lower 8 bits of temporary accumulator T (8 bits)
Index register IX (16 bits)
(Continued)
43
MB89910 Series
(Continued)
Symbol
Meaning
EP
PC
SP
PS
dr
Extra pointer EP (16 bits)
Program counter PC (16 bits)
Stack pointer SP (16 bits)
Program status PS (16 bits)
Accumulator A or index register IX (16 bits)
Condition code register CCR (8 bits)
Register bank pointer RP (5 bits)
CCR
RP
Ri
General-purpose register Ri (8 bits, i = 0 to 7)
Indicates that the very × is the immediate data.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
×
Indicates that the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
( × )
(( × ))
The address indicated by the contents of × is the target of accessing.
(Whether its length is 8 or 16 bits is determined by the instruction in use.)
Columns indicate the following:
Mnemonic:
~:
Assembler notation of an instruction
Number of instructions
Number of bytes
#:
Operation:
TL, TH, AH:
Operation of an instruction
A content change when each of the TL, TH, and AH instructions is executed. Symbols in
the column indicate the following:
• “–” indicates no change.
• dH is the 8 upper bits of operation description data.
• AL and AH must become the contents of AL and AH immediately before the instruction
is executed.
• 00 becomes 00.
N, Z, V, C:
OP code:
An instruction of which the corresponding flag will change. If + is written in this column,
the relevant instruction will change its corresponding flag.
Code of an instruction. If an instruction is more than one code, it is written according to
the following rule:
Example: 48 to 4F ← This indicates 48, 49, ... 4F.
44
MB89910 Series
Table 2 Transfer Instructions (48 instructions)
Mnemonic
MOV dir,A
MOV @IX +off,A
MOV ext,A
MOV @EP,A
MOV Ri,A
MOV A,#d8
MOV A,dir
MOV A,@IX +off
MOV A,ext
MOV A,@A
MOV A,@EP
MOV A,Ri
MOV dir,#d8
MOV @IX +off,#d8
MOV @EP,#d8
MOV Ri,#d8
MOVW dir,A
MOVW @IX +off,A
~
#
Operation
TL
TH AH NZVC OP code
3
4
4
3
3
2
3
4
4
3
3
3
4
5
4
4
4
5
2
2
3
1
1
2
2
2
3
1
1
1
3
3
2
2
2
2
(dir) ← (A)
–
–
–
–
–
AL
AL
AL
AL
AL
AL
AL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
45
46
61
( (IX) +off ) ← (A)
(ext) ← (A)
( (EP) ) ← (A)
47
(Ri) ← (A)
(A) ← d8
(A) ← (dir)
48 to 4F
04
05
06
60
92
(A) ← ( (IX) +off)
(A) ← (ext)
(A) ← ( (A) )
(A) ← ( (EP) )
07
(A) ← (Ri)
(dir) ← d8
08 to 0F
85
86
87
88 to 8F
D5
( (IX) +off ) ← d8
( (EP) ) ← d8
–
–
–
–
(Ri) ← d8
(dir) ← (AH),(dir + 1) ← (AL)
( (IX) +off) ← (AH),
( (IX) +off + 1) ← (AL)
(ext) ← (AH), (ext + 1) ← (AL)
( (EP) ) ← (AH),( (EP) + 1) ← (AL)
(EP) ← (A)
–
D6
MOVW ext,A
MOVW @EP,A
MOVW EP,A
MOVW A,#d16
MOVW A,dir
MOVW A,@IX +off
5
4
2
3
4
5
3
1
1
3
2
2
–
–
–
AL
AL
AL
–
–
–
AH
AH
AH
–
–
–
dH
dH
dH
– – – –
– – – –
– – – –
+ + – –
+ + – –
+ + – –
D4
D7
E3
E4
C5
C6
(A) ← d16
(AH) ← (dir), (AL) ← (dir + 1)
(AH) ← ( (IX) +off),
(AL) ← ( (IX) +off + 1)
(AH) ← (ext), (AL) ← (ext + 1)
(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)
MOVW A,ext
MOVW A,@A
MOVW A,@EP
MOVW A,EP
MOVW EP,#d16
MOVW IX,A
MOVW A,IX
MOVW SP,A
MOVW A,SP
MOV @A,T
MOVW @A,T
MOVW IX,#d16
MOVW A,PS
MOVW PS,A
MOVW SP,#d16
SWAP
5
4
4
2
3
2
2
2
2
3
4
3
2
2
3
2
4
4
2
3
3
3
3
2
3
1
1
1
3
1
1
1
1
1
1
3
1
1
3
1
2
2
1
1
1
1
1
1
AL
AL
AH
AH
AH
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
dH
dH
dH
–
–
dH
–
dH
–
–
–
dH
–
–
AL
–
–
–
dH
dH
dH
dH
dH
+ + – –
+ + – –
+ + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
+ + + +
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
C4
93
C7
F3
E7
E2
F2
E1
F1
82
83
E6
70
71
E5
10
(AH) ← ( (EP) ), (AL) ← ( (EP) + 1) AL
(A) ← (EP)
(EP) ← d16
(IX) ← (A)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
AL
AL
–
(A) ← (IX)
(SP) ← (A)
(A) ← (SP)
( (A) ) ← (T)
( (A) ) ← (TH),( (A) + 1) ← (TL)
(IX) ← d16
(A) ← (PS)
(PS) ← (A)
(SP) ← d16
(AH) ↔ (AL)
(dir): b ← 1
(dir): b ← 0
(AL) ↔ (TL)
(A) ↔ (T)
SETB dir: b
CLRB dir: b
XCH A,T
A8 to AF
A0 to A7
42
–
AH
–
–
–
XCHW A,T
43
F7
F6
F5
XCHW A,EP
XCHW A,IX
XCHW A,SP
MOVW A,PC
(A) ↔ (EP)
(A) ↔ (IX)
(A) ↔ (SP)
(A) ← (PC)
–
–
–
–
F0
Notes: • During byte transfer to A, T ← A is restricted to low bytes.
• Operands in more than one operand instruction must be stored in the order in which their mnemonics
are written. (Reverse arrangement of F2MC-8 family)
45
MB89910 Series
Table 3 Arithmetic Operation Instructions (62 instructions)
Mnemonic
ADDC A,Ri
ADDC A,#d8
ADDC A,dir
ADDC A,@IX +off
ADDC A,@EP
ADDCW A
ADDC A
SUBC A,Ri
SUBC A,#d8
SUBC A,dir
SUBC A,@IX +off
SUBC A,@EP
SUBCW A
SUBC A
INC Ri
INCW EP
INCW IX
INCW A
DEC Ri
DECW EP
DECW IX
DECW A
MULU A
DIVU A
~
#
Operation
(A) ← (A) + (Ri) + C
TL
TH AH NZVC OP code
3
2
3
4
3
3
2
3
2
3
4
3
3
2
4
3
3
3
4
3
3
3
19
21
3
3
3
2
3
2
1
2
2
2
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dL
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
00
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
dH
–
–
–
–
dH
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + –
– – – –
– – – –
+ + – –
+ + + –
– – – –
– – – –
+ + – –
– – – –
– – – –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + – +
28 to 2F
24
(A) ← (A) + d8 + C
(A) ← (A) + (dir) + C
(A) ← (A) + ( (IX) +off) + C
(A) ← (A) + ( (EP) ) + C
(A) ← (A) + (T) + C
(AL) ← (AL) + (TL) + C
(A) ← (A) − (Ri) − C
(A) ← (A) − d8 − C
(A) ← (A) − (dir) − C
(A) ← (A) − ( (IX) +off) − C
(A) ← (A) − ( (EP) ) − C
(A) ← (T) − (A) − C
(AL) ← (TL) − (AL) − C
(Ri) ← (Ri) + 1
(EP) ← (EP) + 1
(IX) ← (IX) + 1
(A) ← (A) + 1
(Ri) ← (Ri) − 1
(EP) ← (EP) − 1
(IX) ← (IX) − 1
(A) ← (A) − 1
25
26
27
23
22
38 to 3F
34
35
36
37
33
32
C8 to CF
C3
C2
C0
D8 to DF
D3
–
D2
D0
01
11
63
73
53
12
dH
dH
00
dH
dH
dH
–
(A) ← (AL) × (TL)
(A) ← (T) / (AL),MOD → (T)
(A) ← (A) (T)
(A) ← (A) (T)
(A) ← (A) (T)
ANDW A
ORW A
XORW A
CMP A
CMPW A
RORC A
(TL) − (AL)
(T) − (A)
–
–
13
03
→
→
A
C
←
C ← A
ROLC A
2
1
–
–
–
+ + – +
02
(A) − d8
(A) − (dir)
(A) − ( (EP) )
(A) − ( (IX) +off)
(A) − (Ri)
CMP A,#d8
CMP A,dir
CMP A,@EP
CMP A,@IX +off
CMP A,Ri
DAA
2
3
3
4
3
2
2
2
2
3
3
4
3
2
2
3
2
2
1
2
1
1
1
1
2
2
1
2
1
1
2
2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + + +
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
14
15
17
16
18 to 1F
84
Decimal adjust for addition
Decimal adjust for subtraction
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
DAS
XOR A
94
52
54
55
57
56
XOR A,#d8
XOR A,dir
XOR A,@EP
XOR A,@IX +off
XOR A,Ri
AND A
58 to 5F
62
AND A,#d8
AND A,dir
64
65
(A) ← (AL) (dir)
(Continued)
46
MB89910 Series
(Continued)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
AND A,@EP
AND A,@IX +off
AND A,Ri
OR A
OR A,#d8
3
4
3
2
2
3
3
4
3
5
4
5
4
3
3
1
2
1
1
2
2
1
2
1
3
2
3
2
1
1
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(A) ← (AL) (TL)
(A) ← (AL) d8
(A) ← (AL) (dir)
(A) ← (AL) ( (EP) )
(A) ← (AL) ( (IX) +off)
(A) ← (AL) (Ri)
(dir) – d8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + R –
+ + + +
+ + + +
+ + + +
+ + + +
– – – –
– – – –
67
66
68 to 6F
72
74
75
77
76
OR A,dir
OR A,@EP
OR A,@IX +off
OR A,Ri
CMP dir,#d8
CMP @EP,#d8
CMP @IX +off,#d8
CMP Ri,#d8
INCW SP
78 to 7F
95
97
96
98 to 9F
C1
( (EP) ) – d8
( (IX) + off) – d8
(Ri) – d8
(SP) ← (SP) + 1
(SP) ← (SP) – 1
DECW SP
D1
Table 4 Branch Instructions (17 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
BZ/BEQ rel
BNZ/BNE rel
BC/BLO rel
BNC/BHS rel
BN rel
BP rel
BLT rel
3
3
3
3
3
3
3
3
5
5
2
3
6
6
3
4
6
2
2
2
2
2
2
2
2
3
3
1
3
1
3
1
1
1
If Z = 1 then PC ← PC + rel
If Z = 0 then PC ← PC + rel
If C = 1 then PC ← PC + rel
If C = 0 then PC ← PC + rel
If N = 1 then PC ← PC + rel
If N = 0 then PC ← PC + rel
If V N = 1 then PC ← PC + rel
If V N = 0 then PC ← PC + reI
If (dir: b) = 0 then PC ← PC + rel
If (dir: b) = 1 then PC ← PC + rel
(PC) ← (A)
(PC) ← ext
Vector call
Subroutine call
(PC) ← (A),(A) ← (PC) + 1
Return from subrountine
Return form interrupt
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
– + – –
– + – –
– – – –
– – – –
– – – –
– – – –
– – – –
– – – –
Restore
FD
FC
F9
F8
FB
FA
FF
FE
BGE rel
BBC dir: b,rel
BBS dir: b,rel
JMP @A
JMP ext
CALLV #vct
CALL ext
XCHW A,PC
RET
B0 to B7
B8 to BF
E0
21
E8 to EF
31
F4
20
30
RETI
–
Table 5 Other Instructions (9 instructions)
Mnemonic
~
#
Operation
TL
TH AH NZVC OP code
PUSHW A
POPW A
PUSHW IX
POPW IX
NOP
CLRC
SETC
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
dH
–
–
–
–
–
–
–
– – – –
– – – –
– – – –
– – – –
– – – –
– – – R
– – – S
– – – –
– – – –
40
50
41
51
00
81
91
80
90
CLRI
SETI
47
MB89910 Series
■ INSTRUCTION MAP
48
MB89910 Series
■ MASK OPTIONS
MB89PV910
–101 –102
Setting not Setting not
MB89P915
MB89913
Part number
MB89915
–101
–102
No.
Specify when
Setting not Setting not
Specifying procedure
possible
possible ordering masking possible
possible
Selection either single or
dual clock
Single-clock mode
Dual-clock mode
1
2
Single clock Dual clock
Selectable
Single clock Dual clock
Pull-down resistors
P17 to P10
All pins fixed to without
pull-down resistor
Can be selected
per pin.
All pins fixed to without
pull-down resistor
P27 to P20
P51, P50
Voltage to be detected for low-
voltage detection reset
3.3 ± 0.3 V
3
Cannot be used.
Selectable
Can be set by register.
3.6 ± 0.3 V
4.0 ± 0.3 V
■ ORDERING INFORMATION
Part number
Package
Remarks
MB89913P-SH
MB89915P-SH
MB89P915P-101-SH
MB89P915P-102-SH
48-pin Plastic SH-DIP
(DIP-48P-M01)
MB89913PF
MB89915PF
MB89P915PF-101
MB89P915PF-102
48-pin Plastic QFP
(FPT-48P-M15)
MB89PV910C-101-ES-SH
MB89PV910C-102-ES-SH
64-pin Ceramic MDIP
(MDP-64C-P02)
49
MB89910 Series
■ PACKAGE DIMENSIONS
48-pin Plastic SH-DIP
(DIP-48P-M01)
43.69–+00..3200
1.720 +–..001028
INDEX-1
INDEX-2
13.80±0.25
(.543±.010)
0.51(.020)MIN
5.25(.207)
MAX
0.25±0.05
(.010±.002)
3.00(.118)
MIN
1.00–+00.50
.039 –+0.020
0.45±0.10
(.018±.004)
15.24(.600)
TYP
15°MAX
1.778±0.18
(.070±.007)
1.778(.070)
MAX
40.894(1.610)REF
C
Dimensions in mm (inches)
1994 FUJITSU LIMITED D48002S-3C-3
50
MB89910 Series
(Continued)
48-pin Plastic QFP
(FPT-48P-M15)
15.30±0.40SQ
(.602±.016)
2.70(.106)MAX
12.00+–00..1300 SQ
.472+–..001024
0.05(.002)MIN
(STAND OFF)
36
25
Details of "A" part
0.15(.006)
37
24
8.80
(.346)
REF
13.60±0.40
(.535±.016)
0.20(.008)
0.15(.006)MAX
0.50(.020)MAX
INDEX
"A"
48
13
Details of "B" part
1
12
LEAD No.
0.80(.0315)TYP
0.15–+00..0015
.006+–..0000024
0.30±0.06
(.012±.002)
M
0.16(.006)
0~10°
0.85±0.30
(.033±.012)
"B"
0.10(.004)
C
Dimensions in mm (inches)
1994 FUJITSU LIMITED F48025S-1C-1
51
MB89910 Series
(Continued)
64-pin Ceramic MDIP
(MDP-64C-P02)
0°~9°
56.90±0.64
(2.240±.025)
15.24(.600)
TYP
18.75±0.30
(.738±.012)
19.05±0.30
(.750±.012)
INDEX AREA
2.54±0.25
(.100±.010)
0.25±0.05
(.010±.002)
33.02(1.300)REF
1.27±0.25
(.050±.010)
10.16(.400)MAX
0.46–+00..0183
0.90±0.13
(.035±.005)
3.43±0.38
(.135±.015)
1.778±0.25
(.070±.010)
.018+–..000035
55.12(2.170)REF
C
Dimensions in mm (inches)
1994 FUJITSU LIMITED M64002SC-1-4
52
MB89910 Series
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
KAWASAKI PLANT, 4-1-1, Kamikodanaka
Nakahara-ku, Kawasaki-shi
Kanagawa 211-88, Japan
Tel: (044) 754-3763
All Rights Reserved.
The contents of this document are subject to change without
notice. Customers are advised to consult with FUJITSU sales
representatives before ordering.
Fax: (044) 754-3329
The information and circuit diagrams in this document presented
as examples of semiconductor device applications, and are not
intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the
use of this information or circuit diagrams.
North and South America
FUJITSU MICROELECTRONICS, INC.
Semiconductor Division
3545 North First Street
San Jose, CA 95134-1804, U.S.A.
Tel: (408) 922-9000
FUJITSU semiconductor devices are intended for use in
standard applications (computers, office automation and other
office equipment, industrial, communications, and measurement
equipment, personal or household devices, etc.).
CAUTION:
Customers considering the use of our products in special
applications where failure or abnormal operation may directly
affect human lives or cause physical injury or property damage,
or where extremely high levels of reliability are demanded (such
as aerospace systems, atomic energy controls, sea floor
repeaters, vehicle operating controls, medical devices for life
support, etc.) are requested to consult with FUJITSU sales
representatives before such use. The company will not be
responsible for damages arising from such use without prior
approval.
Fax: (408) 432-9044/9045
Europe
FUJITSU MIKROELEKTRONIK GmbH
Am Siebenstein 6-10
63303 Dreieich-Buchschlag
Germany
Tel: (06103) 690-0
Fax: (06103) 690-122
Asia Pacific
FUJITSU MICROELECTRONICS ASIA PTE. LIMITED
#05-08, 151 Lorong Chuan
New Tech Park
Singapore 556741
Tel: (65) 281-0770
Fax: (65) 281-0220
Any semiconductor devices have inherently a certain rate of
failure. You must protect against injury, damage or loss from
such failures by incorporating safety design measures into your
facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required
for export of those products from Japan.
F9703
FUJITSU LIMITED Printed in Japan
53
相关型号：
MB89P945PF
Microcontroller, 8-Bit, OTPROM, F2MC-8L CPU, 8MHz, CMOS, PQFP48, 12 X 12 MM, 2.70 MM HEIGHT, 0.80 MM PITCH, PLASTIC, QFP-48
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