MB89P935APFV_技术文档

FUJITSU SEMICONDUCTOR

DATA SHEET

DS07-12541-2E

8-bit Proprietary Microcontroller

CMOS

F²MC-8L MB89930A Series

MB89935A/935B/P935A/PV930A

■ DESCRIPTION

The MB89930A series is a line of single-chip microcontrollers. In addition to a compact instruction set, the

microcontrollers contain a variety of peripheral functions such, timers, a serial interface, an A/D converter and an

external interrupt.

■ FEATURES

• MB89600 Series CPU core

• Maximum memory space : 64 Kbytes

• Minimum execution time : 0.4 µs/10 MHz

• Interrupt processing time : 3.6 µs/10 MHz

• I/O ports : max. 21channels

• 21-bit timebase timer

• 8-bit PWM timer

• 8/16-bit capture timer/counter

• 10-bit A/D converter : 8 channels

• UART

• 8-bit serial I/O

• External interrupt 1 : 3 channels

• External interrupt 2 : 8 channels

• Wild Register : 2 bytes

(Continued)

■ PACKAGE

30-pin plastic SSOP

48-pin ceramic MQFP

(FPT-30P-M02)

(MQP-48C-P01)

MB89930A Series

(Continued)

• Low-power consumption modes ( sleep mode, and stop mode)

• SSOP-30 and MQFP-48 package

• CMOS Technology

■ PRODUCT LINEUP

Part number

MB89935A MB89935B

MB89P935A

MB89PV930A

Parameter

Mass production product

(mask ROM product)

One-time PROM product

(for small-scale production)

Piggyback/evaluation product

(for development)

Classification

16 K × 8 bits

(internal mask ROM)

16 K × 8 bits

(internal PROM)

32 K × 8 bits

(external EPROM)

ROM size

RAM size

512 × 8 bits

Number of instructions :

Instruction bit length :

Instruction length :

Data bit length :

Minimum execution time : 0.4 µs to 6.4 µs (10 MHz)

Interrupt processing time : 3.6 µs to 57.6 µs (10 MHz)

136

8 bits

1 to 3 bytes

1, 8, 16 bits

CPU functions

Ports

General-purpose I/O ports (CMOS) : 21 (also serve as peripherals )

(4 ports are also an N-ch open-drain type.)

21-bit time

base timer

21-bit Interrupt cycle : 0.82 ms, 3.3 ms, 26.2 ms, or 419.4 ms with 10-MHz main clock

Watching timer

Reset generation cycle : 419.4 ms minimum with 10-MHz main clock

8-bit interval timer operation (square output capable, operating clock cycle :

0.4 µs , 3.2 µs, 6.4 µs, 25.6 µs)

8-bit resolution PWM operation (conversion cycle : 102.4 µs to 26.84 ms)

Count clock selectable between 8-bit and 16-bit timer/counter outputs

8-bit PWM timer

8-bit capture timer/counter × 1 channel + 8-bit timer or

16-bit capture timer/counter × 1 channel

Capable of event count operation and square wave output using external clock input with

8-bit timer 0 or 16-bit counter

8/16-bit capture,

timer/counter

UART

Transfer data length : 6/7/8 bits

8 bits LSB first/MSB first selectable

One clock selectable from four operation clocks

(one external shift clock, three internal shift clocks : 0.8 µs, 6.4 µs, 25.6 µs)

8-bit Serial I/O

12-bit PPG timer

Output frequency : Pulse width and cycle selectable

3 channels (Interrupt vector, request flag, request output enabled)

Edge selectable (Rising edge, falling edge, or both edges)

Also available for resetting stop/sleep mode (Edge detectable even in stop mode)

External interrupt 1

(wake-up function)

External interrupt 2

(wake-up function)

1 channel with 8 inputs (Independent L-level interrupt and input enable)

Also available for resetting stop/sleep mode (Level detectable even in stop mode)

(Continued)

2

MB89930A Series

(Continued)

Part number

MB89935A

MB89935B

MB89P935A

MB89PV930A

Parameter

10-bit precision × 8 channels

10-bit A/D converter

A/D conversion function (Conversion time : 15.2 µs/10 MHz)

Continuous activation by 8/16-bit timer/counter output or time-base timer counter

Wild Register

Standby mode

8-bit × 2

Sleep mode, and Stop mode

*Power supply

Voltage

2.2 V to 5.5 V

3.0 V to 5.5 V

2.7 V to 5.5 V

* : The minimum operating voltage varies with the operating frequency, the function, and the connected ICE.

■ PACKAGE AND CORRESPONDING PRODUCTS

Package

MB89935A

MB89935B

MB89P935A

MB89PV930A

FPT-30P-M02

MQP-48C-P01

×*

×

: Available

× : Not available

* : Adapter for 48-pin to 30-pin conversion (manufactured by Sun Hayato Co., Ltd.)

Part number : 48QF-30SOP-8L

Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403

■ DIFFERENCES AMONG PRODUCTS

1. Memory Size

Before evaluating using the piggyback product, verify its differences from the product that will actually be used.

2. Current Consumption

In the case of the MB89PV930A, add the current consumed by the EPROM which is connected to the top socket.

3. Mask Options

Functions that can be selected as options and how to designate these options vary by the product. Before using

options check section “■ MASK OPTIONS” Take particular care on the following points :

Options are fixed on the MB89PV930A and MB89P935A.

4. Difference between MB89935A and MB89935B

MB89935B is different from MB89935A in that the internal circuit and oscillator have been changed and the

radiated noise and current consumption while oscillation is active is reduced. For details of the characteristics

of current consumption, see “■ EXAMPLE CHARACTERISTICS”.

3

MB89930A Series

■ PIN ASSIGNMENT

(TOP VIEW)

P04/INT24

P05/INT25

P06/INT26

P07/INT27

MOD0

1

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

VCC

2

P03/INT23/AN7

P02/INT22/AN6

P01/INT21/AN5

P00/INT20/AN4

P43/AN3

3

4

5

MOD1

6

RST

7

P42/AN2

X0

8

P41/AN1

X1

9

P40/AN0

VSS

10

11

12

13

14

15

AVSS

P37/BZ/PPG

P36/INT12

P35/INT11

P34/TO/INT10

P33/EC

P50/PWM

P30/UCK/SCK

P31/UO/SO

P32/UI/SI

C

(FPT-30P-M02)

(Continued)

4

MB89930A Series

(Continued)

(TOP VIEW)

P34/TO/INT10

P33/EC

1

36

35

34

33

32

31

30

29

28

27

26

25

N.C.

2

P36/INT12

P37/BZ/PPG

X1

P32/UI/SI

3

69

70

71

72

73

74

75

76

60

59

58

57

56

55

54

53

P31/UO/SO

P30/UCK/SCK

P40/AN0

4

5

X0

6

RST

P41/AN1

7

MOD1

P42/AN2

8

MOD0

P43/AN3

9

P07/INT27

P06/INT26

P05/INT25

P04/INT24

P00/INT20/AN4

P01/INT21/AN5

P02/INT22/AN6

10

11

12

(MQP-48C-P01)

Pin no.

49

Pin name

Pin no.

Pin name

N.C.

A2

Pin no.

65

Pin name

O4

Pin no.

Pin name

OE

V^PP

A12

A7

57

58

59

60

61

62

63

64

73

74

75

76

77

78

79

80

50

66

O5

N.C.

A11

A9

51

A1

67

O6

52

A6

A0

68

O7

53

A5

O1

69

O8

A8

54

A4

O2

70

CE

A13

A14

VCC

55

A3

O3

71

A10

N.C.

56

N.C.

V^SS

72

N.C. : Internally connected. Do not use.

5

MB89930A Series

■ PIN DESCRIPTION

Pin No.

Pin name

Circuit

type

Function

SSOP*¹MQFP*²

8

9

32

33

X0

X1

Pins for connecting the crystal resonator for the main clock.

To use an eternal clock, input the signal to X0 and leave X1

open.

A

B

5

6

29

30

MOD0

MOD1

Memory access mode setting input pins.

Connect the pin directly to Vss.

Reset I/O pin.

This pin serves as an N-channel open-drain output with pull-

up resistor and a hysteresis input as well. The pin outputs the

“L” signal (optionally) in response to an internal reset request.

Also, it initializes the

7

31

RST

C

internal circuit upon input of the “L” signal.

General-purpose CMOS I/O ports.

P00/INT20/AN4

to P03/INT23/AN7

These pins also serve as an input (wake-up input) of external

interrupt 2 or as an A/D converter analog input. The input of

external interrupt 2 is a hysteresis input.

26 to 29 10 to 13

1 to 4 25 to 28

G

D

General-purpose CMOS I/O ports.

P04/INT24 to

P07/INT27

These pins also serve as an input (wake-up input) of external

interrupt 2. The input of external interrupt 2 is a hysteresis in-

put.

General-purpose CMOS I/O ports.

19

18

17

5

4

3

P30/UCK/SCK

P31/UO/SO

P32/UI/SI

D

E

D

This pin also serves as the clock I/O pin for the UART or 8-bit

serial I/O. The resource is a hysteresis input.

General-purpose CMOS I/O ports.

This pin also serves as the data output pin for the UART or 8-

bit serial I/O.

General-purpose CMOS I/O ports.

This pin also serves as the data input pin for the UART or 8-bit

serial I/O. The resource is a hysteresis input.

General-purpose CMOS I/O ports.

This pin also serves as the external clock input pin for the 8/

16-bit capture timer/counter. The resource is a hysteresis in-

put.

15

2

P33/EC

D

General-purpose CMOS I/O ports.

This pin also serves as the output pin for the 8/16-bit capture

timer/counter or as the input pin for external interrupt 1. The

resource is a hysteresis input.

14

1

P34/TO/INT10

D

General-purpose CMOS I/O ports.

These pins also serve as the input pin for external

interrupt 1. The resource is a hysteresis input.

P35/INT11,

P36/INT12

13, 12

48, 35

(Continued)

*1 : FPT-30P-M02

*2 : MQP-48C-P01

6

MB89930A Series

(Continued)

Pin No.

SSOP*¹MQFP*²

Circuit

type

Pin name

Function

General-purpose CMOS I/O ports.

11

20

34

24

P37/BZ/PPG

E

F

This pin also serves as the buzzer output pin or the 12-bit pro-

grammable pulse generator output.

General-purpose CMOS I/O ports.

This pin also serves as the 8-bit PWM output pin. The pin is a

hysteresis input.

P50/PWM

General-purpose CMOS I/O ports. These pins can also be

used as N-channel open-drain ports.

The pins also serve as A/D converter analog input pins.

P40/AN0 to

P43/AN3

22 to 25

6 to 9

30

10

18

42

V^CC

V^SS

Power supply pin

Power (GND) pin

Power supply pin for the A-D converter.

Apply equal potential to this pin and the VSS pin.

21

16

14

AV^SS

C

Capacitance pin for regulating the power supply.

Connect an external ceramic capacitor of about 0.1 µF.

15,16,17

19,20,21

22,23,36

37,38,39

40,41,43

44,45,46

47

Internally connected pins

Be sure to leave them open.

N.C.

*1 : FPT-30P-M02

*2 : MQP-48C-P01

7

MB89930A Series

■ EXTERNAL EPROM PIN DESCRIPTION (MB89PV930A only)

Pin No.

Pin name

I/O

Function

49

V^PP

O

“H” level output pin

50

51

52

53

54

55

58

59

60

A12

A7

A6

A5

A4

A3

A2

A1

A0

O

Address output pins

61

62

63

O1

O2

O3

I

Data input pins

64

V^SS

O

Power supply (GND) pin

Data input pins

65

66

67

68

69

O4

O5

O6

O7

O8

I

ROM chip enable pin

Outputs “H” during standby.

70

71

73

CE

A10

OE

O

Address output pin

ROM output enable pin

Outputs “L” at all times.

75

76

77

78

79

A11

A9

A8

A13

A14

O

Address output pins

80

VCC

EPROM power supply pin

56

57

72

74

Internally connected pins

Be sure to leave them open.

N.C.

8

MB89930A Series

■ I/O CIRCUIT TYPE

Type

Circuit

Remarks

• Crystal oscillation type

X1

X0

A

Standby control signal

• Hysteresis input

B

C

• At an output pull-up resister (P-ch) of approx-

imately 50 kΩ/5.0 V

• Hysteresis input

P-ch

N-ch

• CMOS output

• CMOS input

• Hysteresis input (Resource input)

• Pull-up resistor optional

P-ch

N-ch

D

(Continued)

9

MB89930A Series

(Continued)

Type

Circuit

Remarks

• CMOS output

• CMOS input

• Pull-up resistor optional

P-ch

E

N-ch

• CMOS output

• CMOS input

• Analog input

• N-ch open-drain output available

P-ch

N-ch

open-drain control

F

Analog input

A/D enable

P-ch

• CMOS output

• CMOS input

• Hysteresis input (Resouce input)

• Analog input

P-ch

N-ch

G

Analog input

A/D enable

10

MB89930A Series

■ HANDLING DEVICES

1. Preventing Latchup

Latchup may occur on CMOS ICs if voltage higher than VCC or lower than VSS is applied to input and output pins

other than medium- and high-voltage pins or if higher than the voltage which shows on “1. Absolute Maximum

Ratings” in section “■ ELECTRICAL CHARACTERISTICS” is applied between VCC and VSS.

When latchup occurs, power supply current increases rapidly and might thermally damage elements. When

using, take great care not to exceed the absolute maximum ratings.

Also, take care to prevent the analog input from exceeding the digital power supply (V^CC) when the analog system

power supply is turned on and off.

2. Treatment of Unused Input Pins

Leaving unused input terminals open may lead to permanent damage due to malfunction and latchup; pull up

or pull down the terminals through the resistors of 2 kΩ or more.

Make the unused I/O terminal in a state of output and leave it open and if it is in an input state, handle it with

the same procedure as the input terminals.

3. Treatment of N.C. Pins

Be sure to leave (internally connected) N.C. pins open.

4. Power Supply Voltage Fluctuations

Although VCC power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage

could cause malfunctions, even if it occurs within the rated range. Stabilizing voltage supplied to the IC is therefore

important. As stabilization guidelines, it is recommended to control power so that V^CCripple fluctuations (P-P

value) will be less than 10% of the standard VCC value at the commercial frequency (50 to 60 Hz) and the transient

fluctuation rate will be less than 0.1 V/ms at the time of a momentary fluctuation such as when power is switched.

5. Treatment of Power Supply Pins on Microcontrollers with A/D Converters

Connect to be AVSS = VSS even if the A/D converters are not in use.

6. Precautions when Using an External Clock

When an external clock is used, oscillation stabilization time is required even for power-on reset (optional) and

wake-up from stop mode.

7. About the Wild Register Function

No wild register can be debugged on the MB89PV930A. For the operation check, test the MB89P935A installed

on a target system.

8. Program Execution in RAM

When the MB89PV930A is used, no program can be executed in RAM.

11

MB89930A Series

■ PROGRAMMING TO THE EPROM WITH PIGGYBACK/EVALUATION DEVICE

1. EPROM for Use

MBM27C256A-20TVM

2. Programming Socket Adapter

To program to the PROM using an EPROM programmer, use the socket adapter (manufacturer : Sun Hayato

Co., Ltd.) listed below.

Package

Compatible socket part number

LCC-32

ROM-32LC-28DP-S

Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403

FAX (81) -3-5396-9106

3. Memory Space.

Normal operating mode

Address

0000H

I/O

0080H

RAM 512 B

0280H

Corresponding adresses on the

ROM programmer

Not available

Address

0000H

8000H

PROM 32 KB

EPROM 32 KB

FFFFH

7FFFH

4. Programming to the EPROM

(1) Set the EPROM programmer to the MBM27C256A.

(2) Load program data into the EPROM programmer at 0000H to 7FFFH.

(3) Program to 0000^Hto 7FFFH with the EPROM programmer.

12

MB89930A Series

■ PROGRAMMING TO THE OTPROM WITH MB89P935A

1. Memory Space

Normal operating mode

Address

0000H

I/O

0080H

RAM 512 B

0280H

Corresponding adresses on the

ROM programmer

Not available

Address

C000H

PROM 16 KB

FFFFH

2. Programming to the OTPROM

To program to the OTPROM using an EPROM programmer AF200 (manufacturer : Yokogawa Digital Computer

Corp.) .

Inquiry : Yokogawa Digital Computer Corp. : TEL (81) -42-333-6224

Note : Programming to the OTPROM with MB89P935A is serial programming mode only.

3. Programming Adaptor for OTPROM

To program to the OTPROM using an EPROM programmer AF200, use the programming adapter (manufacturer

: Sun Hayato Co., Ltd.) listed below.

Adaptor socket : ROM3-FPT30M02-8L

Inquiry : Sun Hayato Co., Ltd. : TEL (81) -3-3986-0403

FAX (81) -3-5396-9106

13

MB89930A Series

■ BLOCK DIAGRAM

X0

X1

Main clock

oscillator

Timebase timer

Clock controller

Reset circuit

CMOS I/O port

8 bit PWM

RST

P50 / PWM

CMOS I/O port

UART prescaler

UART

External

interrupt2

(wake-up)

P04 / INT24

to

4

8

4

P07 / INT27

P30 / UCK / SCK

P31 / UO / SO

P32 / UI / SI

P00 / INT20 / AN4

to

P03 / INT23 / AN7

8 bit

serial I/O

10 bit A/D

Converter

AVSS

P33 / EC

8/16 bit

capture timer/

counter

4

P34 / TO / INT10

P40 / AN0

to

4

P43 / AN3

3

2

P35 / INT11

to

Exernal

interrupt 1

CMOS I/O port

(N-ch OD)

P36 / INT12

512 byte RAM

F²MC - 8 L CPU

16 Kbyte ROM

Wild register

12 bit PPG

P37 / BZ / PPG

Other pins

Buzzer output

VCC, VSS, MOD1, MOD0, C

CMOS I/O port

14

MB89930A Series

■ CPU CORE

1. Memory Space

The microcontrollers of the MB89930A series offer a memory space of 64 Kbytes for storing all of I/O, data, and

program areas. The I/O area is located at the lowest address. The data area is provided immediately above the

I/O area. The data area can be divided into register, stack, and direct areas according to the application. The

program area is located at exactly the opposite end, that is, near the highest address. Provide the tables of

interrupt reset vectors and vector call instructions toward the highest address within the program area. The

memory space of the MB89930A series is structured as illustrated below.

• Memory Space

MB89935A/B

I/O

MB89P935A

I/O

MB89PV930A

I/O

0000H

0080H

0000H

0080H

0000H

0080H

RAM 512 B

0100H

0200H

0280H

0200H

0280H

0200H

0280H

Not available

ROM 16 KB

Not available

PROM 16 KB

8000H

FFFFH

C000H

FFFFH

C000H

FFFFH

External EPROM

32 KB

15

MB89930A Series

2. Registers

The MB89930A series has two types of registers; dedicated registers in the CPU and general-purpose registers

in the memory. The following dedicated registers are provided :

Program counter (PC) :

A 16-bit register for indicating instruction storage positions

Accumulator (A) :

A 16-bit temporary register for storing arithmetic operations, etc. When the

instruction is an 8-bit data processing instruction, the lower byte is used.

Temporary accumulator (T) : A 16-bit register which performs arithmetic operations with the accumulator

When the instruction is an 8-bit data processing instruction, the lower byte is

used.

Index register (IX) :

Extra pointer (EP) :

Stack pointer (SP) :

Program status (PS) :

A 16-bit register for index modification

A 16-bit pointer for indicating a memory address

A 16-bit register for indicating a stack area

A 16-bit register for storing a register pointer, a condition code

Initial value

16 bit

: Program counter

: Accumulator

FFFD^H

PC

A

Indeterminate

: Temporary accumulator

: Index register

Indeterminate

T

IX

: Extra pointer

EP

SP

: Stack pointer

I-flag = 0, IL1, 0 = 11

The other bit values are indeterminate.

: Program status

RP

CCR

PS

The PS can further be divided into higher 8 bits for use as a register bank pointer (RP) and the lower 8 bits for

use as a condition code register (CCR) . (See the diagram below.)

• Structure of the Program Status Register

RP

CCR

CCR initial value

X011XXXXB

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

R4 R3 R2 R1 R0 IL1 IL0

−

H

I

N

Z

PS

C

V

H-flag

I-flag

IL1,0

N-flag

Z-flag

V-flag

C-flag

× : Undefined

16

MB89930A Series

The RP indicates the address of the register bank currently in use. The relationship between the pointer contents

and the actual address is based on the conversion rule illustrated below.

• Rule for Conversion of Actual Addresses of the General-purpose Register Area

RP

R4 R3 R2 R1 R0 b2

A7 A6 A5 A4 A3 A2 A1 A0

Low OP codes

"0" "0" "0" "0" "0" "0" "0" "1"

A15 A14 A13 A12 A11 A10 A9 A8

b1 b0

Generated addresses

The CCR consists of bits indicating the results of arithmetic operations and the contents of transfer data and

bits for control of CPU operations at the time of an interrupt.

H-flag : Set to “1” when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation.

Cleared to “0” otherwise. This flag is for decimal adjustment instructions.

I-flag : Interrupt is enabled when this flag is set to “1”. Interrupt is disabled when the flag is cleared to “0”.

Cleared to “0” at the reset.

IL1, 0 : Indicates the level of the interrupt currently allowed. Processes an interrupt only if its request level is

higher than the value indicated by this bit.

IL1

0

IL0

0

Interrupt level

High-low

High

1

0

1

0

2

3

1

Low = no interrupt

N-flag : Set to “1” if the MSB becomes to “1” as the result of an arithmetic operation. Cleared to “0” when the

bit is cleared to “0”.

Z-flag : Set to “1” when an arithmetic operation results in 0. Cleared otherwise.

V-flag : Set to “1” if the complement on 2 overflows as a result of an arithmetic operation. Cleared to “0” if the

overflow does not occur.

C-flag : Set to “1” when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. Cleared to

“0” otherwise. Set to the shift-out value in the case of a shift instruction.

17

MB89930A Series

The following general-purpose registers are provided :

General-purpose registers : An 8-bit register for storing data

The general-purpose registers are 8 bits and located in the register banks of the memory. One bank contains

eight registers and up to a total of 16 banks can be used on the MB89930A series. The bank currently in use is

indicated by the register bank pointer (RP) ..

• Register Bank Configuraiton

This address = 0100H + 8 × (RP)

R0

R1

R2

R3

R4

R5

R6

R7

16 banks

Memory area

18

MB89930A Series

■ I/O MAP

Address

0000^H

Register name

PDR0

Register description

Port 0 data register

Port 0 data direction register

Vacancy

Read/write

Initial value

R/W

W

X X X X X X X X

0 0 0 0 0 0 0 0

0001^H

DDR0

0002H to 00006H

0007^H

SYCC

STBC

WDTC

TBTC

System clock control register

Standby control register

Watchdog timer control register

Timebase timer control register

Vacancy

R/W

W

1 - - MM1 0 0

0 0 0 1 0 - - -

0 - - - X X X X

0 0 - - - 0 0 0

0008^H

0009H

000A^H

000B^H

000CH

000D^H

000EH

000F^H

0010H

R/W

PDR3

DDR3

RSFR

PDR4

DDR4

OUT4

PDR5

DDR5

RCR21

RCR22

RCR23

RCR24

BZCR

TCCR

TCR1

TCR0

TDR1

TDR0

TCPH

TCPL

TCR2

Port 3 data register

R/W

W

X X X X X X X X

0 0 0 0 0 0 0 0

X X X X - - - -

- - - - X X X X

- - - - 0 0 0 0

- - - - - - - X

- - - - - - - 0

0 0 0 0 0 0 0 0

- - 0 0 0 0 0 0

0 - 0 0 0 0 0 0

- - 0 0 0 0 0 0

- - - - - 0 0 0

0 0 0 0 0 0 0 0

0 0 0 - 0 0 0 0

X X X X X X X X

- - - - - - 0 0

Port 3 data direction register

Reset flag register

R

Port 4 data register

R/W

R

Port 4 data direction register

Port 4 output format register

Port 5 data register

0011H

0012^H

0013H

Port 5 data direction register

12-bit PPG control register 1

12-bit PPG control register 2

12-bit PPG control register 3

12-bit PPG control register 4

Buzzer register

0014^H

0015H

0016H

0017^H

0018H

0019H

Capture control register

Timer 1 control register

Timer 0 control register

Timer 1 data register

001A^H

001BH

001CH

001DH

001E^H

001FH

0020H

Timer 0 data register

Capture data register H

Capture data register L

Timer output control register

Vacancy

R

R/W

0021^H

0022H

CNTR

COMR

EIC1

PWM control register

R/W

W

0 - 0 0 0 0 0 0

X X X X X X X X

0 0 0 0 0 0 0 0

(Continued)

0023H

PWM compare register

External interrupt 1 Control register 1

00024^H

R/W

19

MB89930A Series

Address

0025^H

0026^H

0027^H

0028H

0029^H

002A^H

Register name

Register description

Read/write

Initial value

EIC2

External interrupt 1 Control register 2

R/W

- - - - 0 0 0 0

Vacancy

SMC

SRC

Serial mode control register

Serial rate control register

Serial status and data register

Serial input data register

Serial output data register

Clock division selection register

Vacancy

R/W

R

0 0 0 0 0 - 0 0

- - 0 1 1 0 0 0

0 0 1 0 0 - 1 X

X X X X X X X X

- - - - 0 0 1 0

SSD

SIDR

SODR

UPC

002B^H

W

002C^H

002DH to 0002FH

0030H

R/W

ADC1

ADC2

ADDH

ADDL

ADEN

A/D converter control register 1

A/D converter control register 2

A/D converter data register H

A/D converter data register L

A/D enable register

R/W

- 0 0 0 0 0 0 0

- 0 0 0 0 0 0 1

- - - - - - X X

X X X X X X X X

0 0 0 0 0 0 0 0

0031H

0032^H

0033H

0034H

0035^H

Vacancy

0036H

EIE2

EIF2

External interrupt 2 control register1

External interrupt 2 control register2

Vacancy

R/W

0 0 0 0 0 0 0 0

- - - - - - - 0

0037^H

0038H

0039H

SMR

SDR

Serial mode register

R/W

0 0 0 0 0 0 0 0

X X X X X X X X

- - - - - - - 0

003A^H

Serial data register

003BH

SSEL

Serial function switching register

Vacancy

003CH to 003FH

0040^H

WRARH0

WRARL0

WRDR0

WRARH1

WRARL1

WRDR1

WREN

Upper-address setting register

Lower-address setting register

Data setting register 0

R/W

X X X X X X X X

X X X X X X 0 0

- - - - - - 0 0

0041^H

0042H

0043H

Upper-address setting register

Lower-address setting register

Data setting register 1

0044^H

0045H

0046H

Address comparison EN registor

Wild-register data test register

Vacancy

0047^H

WROR

0048H to 006FH

0070H

PUL0

Port-0 pull-up setting register

R/W

0 0 0 0 0 0 0 0

(Continued)

20

MB89930A Series

(Continued)

Address

Register name

PUL3

Register description

Port-3 pull-up setting register

Port-5 pull-up setting register

Vacancy

Read/write

R/W

Initial value

0071^H

0072^H

0 0 0 0 0 0 0 0

- - - - - - - 0

PUL5

R/W

0073^Hto 007AH

007BH

ILR1

ILR2

ILR3

ILR4

ITR

Interrupt level setting register1

Interrupt level setting register2

Interrupt level setting register3

Interrupt level setting register4

Interrupt test register

W

1 1 1 1 1 1 1 1

007C^H

007D^H

007EH

007F^H

Not available - - - - - - 0 0

- : Unused, X : Undefined, M : Set using the mask option

Note : Do not use vacancies.

21

MB89930A Series

■ ELECTRICAL CHARACTERISTICS

1. Absolute Maximum Ratings

Value

Symbol

Unit

Remarks

Parameter

Min.

Max.

Power supply voltage

V^CC

VI

VSS − 0.3 VSS + 6.0

V

Input voltage

VSS − 0.3 VCC + 0.3

Output voltage

V^O

VSS − 0.3 VCC + 6.0

IOL1

IOL2

20

10

mA Pins P40 to P43

“L” level maximum output current

“L” level average output current

mA Pins excluding P40 to P43

Average value (operating

mA

I^OLAV

4

current × operating rate)

“L” level total maximum output current

“H” level maximum output current

ΣIOL

100

mA

I^OH

−10

Average value (operating

mA

“H” level average output current

IOHAV

−2

current × operating rate)

“H” level total maximum output current

Power consumption

ΣIOH

Pd

−50

mA

mW

°C

200

Operating temperature

Ta

−40

−55

+85

Storage temperature

Tstg

+150

°C

WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,

temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.

22

MB89930A Series

2. Recommended Operating Conditions

Value

Symbol

Unit

Remarks

Parameter

Min.

2.2

Max.

5.5

Normal operation assurance range

MB89935A/B

V

Power supply voltage

V^CC

1.5

6.0

Retains the RAMstate in stop mode

P00 to P07, P30 to P37, P40 to P43, P50,

UI/SI

V^IH

VIHS

V^IL

0.7 VCC

VCC + 0.3

“H” level input voltage

“L” level input voltage

MOD0/1, RST, EC, INT20 to INT27,

UCK/SCK, INT10 to INT12

0.8 VCC

VSS − 0.3

VCC + 0.3

0.3 VCC

0.2 VCC

V

P00 to P07, P30 to P37, P40 to P43,

P50, UI/SI

MOD0/1, RST, EC, INT20 to INT27,

UCK/SCK, INT10 to INT12

V^ILS

Open-drain output pin

application voltage

V^D

Ta

VSS − 0.3

−40

VCC + 0.3

+85

V

P40 to P43

Operating temperature

°C

6

5

4

3

2

1

Analog accuracy assurance range

Operation assurance range

: Area is assured only for the MB89935A/B

0

1

2

3

4

5

6

7

8

9

10

Operating Frequency (MHz)

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the

semiconductor device. All of the device’s electrical characteristics are warranted when the device is

operated within these ranges.

Always use semiconductor devices within their recommended operating condition ranges. Operation

outside these ranges may adversely affect reliability and could result in device failure.

No warranty is made with respect to uses, operating conditions, or combinations not represented on

the data sheet. Users considering application outside the listed conditions are advised to contact their

FUJITSU representatives beforehand.

23

MB89930A Series

3. DC Characteristics

(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, FCH = 10 MHz (External clock) , Ta = −40 °C to +85 °C)

Value

Typ.

Sym-

bol

Parameter

Pin name

P00 to P07,

Condition

Unit Remarks

Min.

Max.

V^IH

V^IHS

V^IL

P30 to P37, P40 to P43,

P50 , UI/SI

0.7 VCC

VCC + 0.3

V

“H” level input

voltage

RST, MOD0/1,

UCK/SCK, EC,

INT20 to INT27,

INT10 to INT12

0.8 VCC

V^SS− 0.3

VCC + 0.3

0.3 VCC

0.2 VCC

V

P00 to P07,

P30 to P37, P40 to P43,

P50 , UI/SI

“L” level input

voltage

RST, MOD0/1,

UCK/SCK, EC,

INT20 to INT27,

INT10 to INT12

V^ILS

Open-drain

output pin

application

voltage

VD

P40 to P43

VSS − 0.3

VCC + 0.3

V

“H” level

output voltage

P00 to P07, P30 to P37,

P40 to P43, P50

V^OH

I^OH= −4.0 mA

2.4

P00 to P07, P30 to P37,

P50, RST

V^OL1

IOL = 4.0 mA

0.4

V

“L” level

output voltage

VOL2 P40 to P43

IOL = 12.0 mA

P00 to P07, P30 to P37,

P40 to P43, P50 ,

MOD0/1

Without

µA pull-up

resistor

Input leakage

current

I^LI

0.45 V < VI < VCC

VI = 0.0 V

±5

Pull-up

resistance

P00 to P07, P30 to P37,

P40 to P43, P50

RPULL

25

50

8

100

12

9

kΩ

MB89935A/

mA

B

When A/D

converter stops

Normal operation

mode

(External clock,

highest gear

MB89P935

6

mA

A

I^CC

MB89935A/

10

8

15

12

6

mA

B

Power supply

current

When A/D

converter starts

speed)

VCC

MB89P935

mA

A

MB89935A/

Sleep mode

(External clock,

highest gear

speed)

4

mA

B

When A/D

converter stops

I^CCS

MB89P935

3

5

mA

A

(Continued)

24

MB89930A Series

(Continued)

(VCC = 5.0 V ± 10%, AVSS = VSS = 0.0 V, FCH = 10 MHz (External clock) , Ta = −40 °C to +85 °C)

Value

Sym-

bol

Parameter

Pin name

Condition

Unit Remarks

Typ.

Min.

Max.

MB89935A/

B

1

µA

Stop mode

I^CCHVCC Ta = +25 °C

(External clock)

Power supply

current

When A/D

converter stops

MB89P935

A

10

µA

Input

capacitance

Other than AVSS, VCC,

VSS

MB89P935

C^IN

10

pF

A

25

MB89930A Series

4. AC Characteristics

(1) Reset Timing

(AV^SS= VSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Symbol

Condition

Unit

Remarks

Parameter

RST “L” pulse width

Min.

Max.

tZLZH

16 tHCYL

ns

t^HCYL: 1 oscillating clock cycle time

tZLZH

RST

0.2 VCC

Note : When the power-on reset option is not on, leave the external reset on until oscillation becomes stable.

(2) Power-on Reset

(AV^SS= VSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Symbol Condition

Unit

Remarks

Parameter

Min.

Max.

Power supply rising time

Power supply cutoff time

t^R

50

ms

t^OFF

1

ms Due to repeated operations

tR

tOFF

2.0 V

0.2 V

VCC

Note : The supply voltage must be set to the minimum value required for operation within the prescribed default

oscillation settling time.

26

MB89930A Series

(3) Clock Timing

(AV^SS= VSS = 0.0 V, Ta = –40°C to +85°C)

Value

Symbol Condition

Unit

Remarks

Parameter

Min.

1

Max.

10

Clock frequency

Clock cycle time

F^CH

MHz

ns

t^XCYL

100

1000

tWH

tWL

Input clock pulse width

20

ns

t^CR

tCF

Input clock rising/falling time

10

• X0 and X1 Timing and Conditions

tXCYL

tWH

tWL

tCR

tCF

X0

0.8 VCC

0.2 VCC

• Main Clock Conditions

When a crystal or ceramic

resonator is used

When an exernal

clock is used

X0

X1

X0

X1

open

(4) Instruction Cycle.

Symbol

Value (typical)

Unit

Remarks

Parameter

Instruction cycle

(minimum execution time)

tINST = 0.4 µs when operating

at FCH = 10 MHz (4/FCH)

t^INST

4/FCH, 8/FCH, 16/FCH, 64/FCH µs

27

MB89930A Series

(5) Recommended Resonator Manufactures

• Sample application of ceramic resonator

X0

X1

R

C1

C2

Frequency

(MHz)

Resonator

manufacturer

Resonator

C¹

C²

R

CSTS0400MG06

CSTCC4.00MG0H6

CSTS0800MG06

CSTCC8.00MG0H6

CST10.0MTW

4.00

Built-in

330 Ω

8.00

Not required

Murata

Mfg. Co., Ltd.

8.00

10.00

CSTCC10.0MG0H6

Inquiry : Murata Mfg. Co., Ltd.

• Murata Electronics North America, Inc. : TEL1-404-436-1300

• Murata Europe Management GmbH : TEL 49-911-66870

• Murata Electronics Singapore (Pte.) : TEL 65-758-4233

28

MB89930A Series

(6) Peripheral Input Timing

Parameter

(V^CC= 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Symbol

Pin name

Unit

Remarks

Min.

Max.

Peripheral input “H” pulse width

Peripheral input “L” pulse width

t^ILIH

t^IHIL

2 t^INST*

2 tINST*

µs

INT10 to INT12,

INT20 to INT27, EC

* : For information on t^INSTsee “ (4) Instruction Cycle”.

tIHIL

tILIH

INT10 to INT12,

INT20 to INT27, EC

0.8 VCC

0.2 VCC

(V^CC= 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Symbol

Pin name

Unit Remarks

Parameter

Min.

Typ.

15

Max.

23

Peripheral input “H” noise limit

Peripheral input “L” noise limit

t^IHNC

t^ILNC

7

ns

INT10 to INT12, EC

15

23

tIHNC

tILNC

0.8 VCC

INT10 to INT12, EC

0.2 VCC

29

MB89930A Series

(7) UART, Serial I/O Timing

(V^CC= 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Symbol

Pin name

Condition

Unit Remarks

Parameter

Min.

2 tINST*

−200

Max.

Serial clock cycle time

t^SCYC

t^SLOV

t^IVSH

tSHIX

t^SHSL

t^SLSH

tSLOV

t^IVSH

tSHIX

UCK/SCK

UCK/SCK, SO

UCK/SCK, SI

UCK/SCK

µs

ns

µs

ns

µs

UCK/SCK ↓ → SO time

Valid SI → UCK/SCK↑

200

Internalshift

clock mode

1/2 tINST*

tINST*

UCK/SCK ↑ → Valid SI hold time

Serial clock “H” pulse width

Serial clock “L” pulse width

UCK/SCK ↓ → SO time

Valid SI → UCK/SCK

UCK/SCK

tINST*

External

UCK/SCK, SO shift clock

0

200

mode

UCK/SCK, SI

1/2 tINST*

UCK/SCK ↑ → Valid SI hold time

UCK/SCK, SI

* : For information on t^inst, see “ (4) Instruction Cycle”.

• Internal Shift Clock Mode

tSCYC

2.4 V

UCK/SCK

SO

0.8 V

tSLOV

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

SI

• External Shift Clock Mode

tSLSH

tSHSL

0.8 VCC

UCK/SCK

SO

0.2 VCC

tSLOV

2.4 V

0.8 V

tIVSH

tSHIX

0.8 VCC 0.8 VCC

0.2 VCC 0.2 VCC

SI

30

MB89930A Series

5. A/D Converter

(1) A/D Converter Electrical Characteristics

(V^CC= 5.0 V ± 10%, AVSS = VSS = 0.0 V, Ta = −40 °C to +85 °C)

Value

Parameter

Symbol

Unit Remarks

Min.

Typ.

Max.

10

Resolution

Total error

bit

LSB

V

−5.0

−3.0

−2.5

+5.0

+3.0

+2.5

Linearity error

Differential linearity error

Zero transition voltage

Full-scale transition voltage

A/D mode conversion time

Analog port input current

Analog input voltage range

V^OT

AVSS − 3.5 LSB AVSS + 0.5 LSB AVSS + 4.5 LSB

V^FST

VCC − 6.5 LSB VCC − 1.5 LSB VCC + 2.0 LSB

V

38 tINST*

µs

IAIN

10

µA

V

0

VCC

* : For information on t^inst, see “ (4) Instruction Cycle” in “4. AC Characteristics.”

(2) A/D Converter Glossary

• Resolution

Analog changes that are identifiable with the A/D converter

When the number of bits is 10, analog voltage can be divided into 2¹⁰= 1024.

• Linearity error (unit : LSB)

The deviation of the straight line connecting the zero transition point (“00 0000 0000” ↔ “00 0000 0001”) with

the full-scale transition point (“11 1111 1111” ↔ “11 1111 1110”) from actual conversion characteristics

• Differential linearity error (unit : LSB)

The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value

• Total error (unit : LSB)

The difference between theoretical and actual conversion values

Theoretical I/O characteristics

Total error

VFST

3FF

3FE

3FD

3FF

3FE

3FD

Actual conversion

value

1.5 LSB

{1 LSB × N + 0.5 LSB}

004

003

002

001

004

003

002

001

VOT

VNT

Actual conversion

value

1 LSB

Theoretical value

0.5 LSB

AVSS

VCC

AVSS

VCC

Analog input

V^FST− VOT

V^NT− {1 LSB × N + 0.5 LSB}

(V)

1 LSB =

Total error of digital output N =

1022

1 LSB

31

MB89930A Series

Zero transition error

Full-scale transition error

004

Theoretical value

Actual conversion value

3FF

3FE

3FD

3FC

Actual conversion value

003

002

VFST

(Measured

value)

Theoretical

conversion

value

Actual conversion

value

001

Actual conversion

value

VOT

(Measured value)

AVSS

VCC

Analog input

Linearity error

Differential linearity error

Theoretical conversion value

Actual conversion value

3FF

3FE

3FD

N + 1

N

{1 LSB × N + VOT}

Actual conversion value

V (N + 1) T

VFST

(Measured

value)

VNT

Actual conversion

value

004

003

002

001

VNT

N − 1

N − 2

Theoretical conversion

value

Actual conversion

value

VOT (Measured value)

AVSS

VCC

AVSS

VCC

Analog input

V^NT− {1 LSB × N + VOT}

Linearity error of digital output N =

1 LSB

V ^{(N + 1) T}− VNT

−1

Differential linearity of error digital output N =

1 LSB

32

MB89930A Series

(3) Notes on Using A/D Converter

• Input impedance of the analog input pins

The A/D converter used for the MB89930A series contains a sample hold circuit as illustrated below to fetch

analog input voltage into the sample hold capacitor for 16 instruction cycles after activating A/D conversion.

For this reason, if the output impedance of the external circuit for the analog input is high, analog input voltage

might not stabilize within the analog input sampling period. Therefore, it is recommended to keep the output

impedance of the external circuit low (below 4 kΩ) .

Note that if the impedance cannot be kept low, it is recommended to connect an external capacitor of about

0.1 µF for the analog input pin.

• Analog Input Equivalent Circuit

Sample hold circuit

Analog input pin

Comparator

R

C

If the analog input

Close for 16 instruction cycles after

activating A/D conversion

impedance is higher than

4 kΩ, it is recommended to

connect an external

Analog channel selector

capacitor of approx. 0.1 µF.

• Error

The smaller the | V^CC− AVSS |, the greater the error would become relatively.

33

MB89930A Series

■ EXAMPLE CHARACTERISTICS

• Power supply current (MB89935A/MB89935B/MB89P935A : 8 MHz ( when FAR resonator [NM8000] is used)

MB89935B

MB89P935A

MB89935A/MB89935B/

MB89P935A/

MB89935A

Normal operation mode

(ICC1 − VCC, ICC2 − VCC)

Normal operation mode Normal operation mode

(I^CC1 − VCC, ICC2 − VCC)

(ICC1 − VCC, ICC2 − VCC)

FAR : [NM8000]

ICC (mA)

(FCH = 8 MHz, Ta = +25 °C)

8

6

4

2

0

8

6

4

2

0

2

6

4

2

0

ICC1

(gear : 4 divide)

ICC1

(gear : 4 divide)

ICC1

(gear : 4 divide)

1

MB89935A

ICC2

(gear : 64 divide)

MB89P935A

ICC2

(gear : 64 divide)

ICC2 (gear : 64 divide)

MB89935B

0

3

4

5

6

3

4

5

6

3

4

5

6

3

4

5

6

VCC (V)

FAR : [NM8000]

External clock

MB89935A/MB89935B/

MB89P935A/

MB89935A

Sleep mode

MB89935B

Sleep mode

MB89P935A

Sleep mode

(I^CCs1 − VCC, ICCs2 − VCC) (I^CCs1 − VCC, ICCs2 − VCC) (I^CCs1 − VCC, ICCs2 − VCC)

FAR : [NM8000]

ICCs (mA)

(FCH = 8 MHz, Ta = +25 °C)

ICCs (mA)

(FCH = 8 MHz, Ta = +25 °C)

ICCs (mA)

(FCH = 8 MHz, Ta = +25 °C)

ICCs (mA)

(FCH = 8 MHz, Ta = +25 °C)

4

3

2

1

0

4

3

2

1

0

4

3

2

1

0

2

ICCs1

(gear : 4 divide)

ICCs1

(gear : 4 divide)

ICCs1

(gear : 4 divide)

1

MB89935A

MB89P935A

ICCs2

(gear : 64 divide)

ICCs2

(gear : 64 divide)

ICCs2

(gear : 64 divide)

MB89935B

0

3

4

5

6

3

4

5

6

3

4

5

6

3

4

5

6

VCC (V)

FAR : [NM8000]

External clock

34

MB89930A Series

• MB89935A/MB89935B/MB89P935A : 4 MHz (when FAR resonator [NM4000] used)

MB89935A

MB89935B

MB89P935A

MB89935A/MB89935B/

MB89P935A/

Normal operation mode Normal operation mode Normal operation mode

(ICC1 − VCC, ICC2 − VCC)

FAR : [NM4000]

ICC (mA)

(FCH = 4 MHz, Ta = +25 °C)

4

2

1

0

ICC1

(gear : 4 divide)

3

2

1

0

3

ICC1

(gear : 4 divide)

ICC1

(gear : 4 divide)

2

MB89935A

ICC2

(gear : 64 divide)

MB89P935A

1

ICC2

(gear : 64 divide)

ICC2

(gear : 64 divide)

MB89935B

0

3

4

5

6

3

4

5

6

3

4

5

6

3

4

5

6

VCC (V)

FAR : [NM4000]

External clock

MB89935A

Seep mode

MB89935B

Seep mode

MB89P935A

Seep mode

MB89935A/MB89935B/

MB89P935A/

(I^CCs1 − VCC, ICCs2 − VCC) (I^CCs1 − VCC, ICCs2 − VCC) (I^CCs1 − VCC, ICCs2 − VCC)

FAR : [NM4000]

ICCs (mA)

(FCH = 4 MHz, Ta = +25 °C)

ICCs (mA)

(FCH = 4 MHz, Ta = +25 °C)

ICCs (mA)

(FCH = 4 MHz, Ta = +25 °C)

ICC (mA)

(FCH = 4 MHz, Ta = +25 °C)

4

3

2

1

0

4

3

2

1

4

3

2

1

0

2

1

0

ICCs1

(gear : 4 divide)

ICCs1

(gear : 4 divide)

MB89935A

MB89P935A

ICCs1

(gear : 4 divide)

ICCs2

(gear : 64 divide)

ICCs2

(gear : 64 divide)

ICCs2

(gear : 64 divide)

MB89935B

0

3

4

5

6

3

4

5

6

3

4

5

6

3

4

5

6

VCC (V)

FAR : [NM4000]

External clock

35

MB89930A Series

• MB89935A/MB89935B : 10 MHz (when external clock is used)

MB89935A/B

Normal operation mode

(ICC1 − VCC, ICC2 − VCC)

MB89935A/B

Normal operation mode

(ICCs1 − VCC, ICCs2 − VCC)

MB89935A/B

Normal operation mode

(ICCh − VCC)

ICC (mA)

ICCs (mA)

(FCH = 10 MHz, Ta = +25 °C)

ICCh (µA)

(FCH = 10 MHz, Ta = +25 °C)

8

6

4

2

0

4

3

2

1

0

0.4

0.3

0.2

0.1

0

ICC1

(gear : 4 divide)

ICCs1

(gear : 4 divide)

ICC2

(gear : 64 divide)

ICCs2

(gear : 64 divide)

0

3

4

5

6

0

3

4

5

6

0

3

4

5

6

VCC (V)

MB89935A/MB89935B

Stop mode (I^CCh − VCC)

MB89P935A

Stop mode (ICCh − VCC)

ICCh (µA)

(FCH = 10 MHz, VCC = 5.5 V)

10

8

6

4

2

8

6

4

2

0

−50 −25

0

25

50

75

100 125 150

−50 −25

0

25

50

75

100 125 150

Temperature (°C)

36

MB89930A Series

(2) “L” level output voltage

VOL vs. IOL1

VOL vs. IOL2

VOL (V)

0.6

VOL (V)

0.6

VCC = 2.0 V

0.5

0.4

0.3

0.2

0.1

0.5

0.4

0.3

0.2

0.1

VCC = 2.5 V

VCC = 3.0 V

VCC = 3.5 V

VCC = 4.0 V

VCC = 4.5 V

VCC = 5.0 V

VCC = 5.5 V

VCC = 6.0 V

VCC = 3.5 V

VCC = 4.0 V

VCC = 4.5 V

VCC = 5.0 V

VCC = 5.5 V

VCC = 6.0 V

0.0

1

0.0

4

2

3

4

5

6

8

10

12

14

16

IOL1 (mA)

IOL2 (mA)

(3) “H” level output voltage

(VCC − VOH) vs. IOH

VCC − VOH (V)

0.8

VCC = 2.0 V

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

VCC = 2.5 V

VCC = 3.0 V

VCC = 3.5 V

VCC = 4.0 V

VCC = 4.5 V

VCC = 5.0 V

VCC = 5.5 V

VCC = 6.0 V

−1

−2

−3

−4

−5

−6

IOH (mA)

37

MB89930A Series

■ INSTRUCTIONS (136 INSTRUCTIONS)

Execution instructions can be divided into the following four groups:

• Transfer

• Arithmetic operation

• Branch

• Others

Table 1 lists symbols used for notation of instructions.

Table 1 Instruction Symbols

Symbol

dir

Meaning

Direct address (8 bits)

off

Offset (8 bits)

ext

#vct

#d8

#d16

dir: b

rel

Extended address (16 bits)

Vector table number (3 bits)

Immediate data (8 bits)

Immediate data (16 bits)

Bit direct address (8:3 bits)

Branch relative address (8 bits)

Register indirect (Example: @A, @IX, @EP)

@

A

AH

AL

Accumulator A (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of accumulator A (8 bits)

Lower 8 bits of accumulator A (8 bits)

T

TH

TL

Temporary accumulator T (Whether its length is 8 or 16 bits is determined by the instruction in use.)

Upper 8 bits of temporary accumulator T (8 bits)

Lower 8 bits of temporary accumulator T (8 bits)

Index register IX (16 bits)

IX

EP

PC

SP

PS

dr

CCR

RP

Ri

Extra pointer EP (16 bits)

Program counter PC (16 bits)

Stack pointer SP (16 bits)

Program status PS (16 bits)

Accumulator A or index register IX (16 bits)

Condition code register CCR (8 bits)

Register bank pointer RP (5 bits)

General-purpose register Ri (8 bits, i = 0 to 7)

Indicates that the very × is the immediate data.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

×

Indicates that the contents of × is the target of accessing.

( × )

(( × ))

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

The address indicated by the contents of × is the target of accessing.

(Whether its length is 8 or 16 bits is determined by the instruction in use.)

Columns indicate the following:

Mnemonic: Assembler notation of an instruction

~:

#:

The number of instructions

The number of bytes

Operation: Operation of an instruction

TL, TH, AH:

A content change when each of the TL, TH, and AH instructions is executed. Symbols in

the column indicate the following:

• “–” indicates no change.

• dH is the 8 upper bits of operation description data.

• AL and AH must become the contents of AL and AH prior to the instruction executed.

• 00 becomes 00.

N, Z, V, C:

OP code:

An instruction of which the corresponding flag will change. If + is written in this column,

the relevant instruction will change its corresponding flag.

Code of an instruction. If an instruction is more than one code, it is written according to

the following rule:

Example: 48 to 4F ← This indicates 48, 49, ... 4F.

38

MB89930A Series

Table 2 Transfer Instructions (48 instructions)

Mnemonic

MOV dir,A

MOV @IX +off,A

MOV ext,A

MOV @EP,A

MOV Ri,A

MOV A,#d8

MOV A,dir

MOV A,@IX +off

MOV A,ext

MOV A,@A

MOV A,@EP

MOV A,Ri

MOV dir,#d8

MOV @IX +off,#d8

MOV @EP,#d8

MOV Ri,#d8

MOVW dir,A

MOVW @IX +off,A

~

#

Operation

TL

TH AH NZVC OP code

3

4

3

2

3

4

3

4

5

4

5

2

3

1

2

3

1

3

2

(dir) ← (A)

–

AL

–

– – – –

+ + – –

– – – –

45

46

61

( (IX) +off ) ← (A)

(ext) ← (A)

( (EP) ) ← (A)

47

(Ri) ← (A)

(A) ← d8

(A) ← (dir)

48 to 4F

04

05

06

60

92

(A) ← ( (IX) +off)

(A) ← (ext)

(A) ← ( (A) )

(A) ← ( (EP) )

07

(A) ← (Ri)

(dir) ← d8

08 to 0F

85

86

87

88 to 8F

D5

( (IX) +off ) ← d8

( (EP) ) ← d8

–

(Ri) ← d8

(dir) ← (AH),(dir + 1) ← (AL)

( (IX) +off) ← (AH),

( (IX) +off + 1) ← (AL)

(ext) ← (AH), (ext + 1) ← (AL)

( (EP) ) ← (AH),( (EP) + 1) ← (AL)

(EP) ← (A)

–

D6

MOVW ext,A

MOVW @EP,A

MOVW EP,A

MOVW A,#d16

MOVW A,dir

MOVW A,@IX +off

5

4

2

3

4

5

3

1

3

2

–

AL

–

AH

–

dH

– – – –

+ + – –

D4

D7

E3

E4

C5

C6

(A) ← d16

(AH) ← (dir), (AL) ← (dir + 1)

(AH) ← ( (IX) +off),

(AL) ← ( (IX) +off + 1)

(AH) ← (ext), (AL) ← (ext + 1)

(AH) ← ( (A) ), (AL) ← ( (A) ) + 1)

(AH) ← ( (EP) ), (AL) ← ( (EP) + 1)

(A) ← (EP)

MOVW A,ext

MOVW A,@A

MOVW A,@EP

MOVW A,EP

MOVW EP,#d16

MOVW IX,A

MOVW A,IX

MOVW SP,A

MOVW A,SP

MOV @A,T

MOVW @A,T

MOVW IX,#d16

MOVW A,PS

MOVW PS,A

MOVW SP,#d16

SWAP

5

4

2

3

2

3

4

3

2

3

2

4

2

3

2

3

1

3

1

3

1

3

1

2

1

AL

–

AH

–

dH

–

dH

–

dH

–

dH

–

AL

–

dH

+ + – –

– – – –

+ + + +

– – – –

C4

93

C7

F3

E7

E2

F2

E1

F1

82

83

E6

70

71

E5

10

(EP) ← d16

(IX) ← (A)

(A) ← (IX)

(SP) ← (A)

(A) ← (SP)

( (A) ) ← (T)

( (A) ) ← (TH),( (A) + 1) ← (TL)

(IX) ← d16

(A) ← (PS)

(PS) ← (A)

(SP) ← d16

(AH) ↔ (AL)

(dir): b ← 1

(dir): b ← 0

(AL) ↔ (TL)

(A) ↔ (T)

(A) ↔ (EP)

(A) ↔ (IX)

(A) ↔ (SP)

(A) ← (PC)

SETB dir: b

CLRB dir: b

XCH A,T

A8 to AF

A0 to A7

42

AL

–

AH

–

XCHW A,T

43

F7

F6

F5

XCHW A,EP

XCHW A,IX

XCHW A,SP

MOVW A,PC

–

F0

Note During byte transfer to A, T ← A is restricted to low bytes.

Operands in more than one operand instruction must be stored in the order in which their mnemonics

are written. (Reverse arrangement of F²MC-8 family)

39

MB89930A Series

Table 3 Arithmetic Operation Instructions (62 instructions)

Mnemonic

ADDC A,Ri

ADDC A,#d8

ADDC A,dir

ADDC A,@IX +off

ADDC A,@EP

ADDCW A

ADDC A

SUBC A,Ri

SUBC A,#d8

SUBC A,dir

SUBC A,@IX +off

SUBC A,@EP

SUBCW A

SUBC A

INC Ri

INCW EP

INCW IX

INCW A

DEC Ri

DECW EP

DECW IX

DECW A

MULU A

DIVU A

~

#

Operation

(A) ← (A) + (Ri) + C

TL

TH AH NZVC OP code

3

2

3

4

3

2

3

2

3

4

3

2

4

3

4

3

19

21

3

2

3

2

1

2

1

2

1

–

dL

–

00

–

dH

–

dH

–

dH

–

+ + + +

+ + + –

– – – –

+ + – –

+ + + –

– – – –

+ + – –

– – – –

+ + R –

+ + + +

+ + – +

28 to 2F

24

(A) ← (A) + d8 + C

(A) ← (A) + (dir) + C

(A) ← (A) + ( (IX) +off) + C

(A) ← (A) + ( (EP) ) + C

(A) ← (A) + (T) + C

(AL) ← (AL) + (TL) + C

(A) ← (A) − (Ri) − C

(A) ← (A) − d8 − C

(A) ← (A) − (dir) − C

(A) ← (A) − ( (IX) +off) − C

(A) ← (A) − ( (EP) ) − C

(A) ← (T) − (A) − C

(AL) ← (TL) − (AL) − C

(Ri) ← (Ri) + 1

(EP) ← (EP) + 1

(IX) ← (IX) + 1

(A) ← (A) + 1

(Ri) ← (Ri) − 1

(EP) ← (EP) − 1

(IX) ← (IX) − 1

(A) ← (A) − 1

25

26

27

23

22

38 to 3F

34

35

36

37

33

32

C8 to CF

C3

C2

C0

D8 to DF

D3

–

D2

D0

01

11

63

73

53

12

dH

00

dH

–

(A) ← (AL) × (TL)

(A) ← (T) / (AL),MOD → (T)

(A) ← (A) (T)

ANDW A

ORW A

XORW A

CMP A

CMPW A

RORC A

(TL) − (AL)

(T) − (A)

–

13

03

→

C

A

←

C

ROLC A

2

1

–

+ + – +

02

(A) − d8

(A) − (dir)

(A) − ( (EP) )

(A) − ( (IX) +off)

CMP A,#d8

CMP A,dir

CMP A,@EP

CMP A,@IX +off

CMP A,Ri

DAA

2

3

4

3

2

3

4

3

2

3

2

1

2

1

2

1

2

1

2

–

+ + + +

+ + R –

14

15

17

16

(A) − (Ri)

18 to 1F

84

Decimal adjust for addition

Decimal adjust for subtraction

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

DAS

XOR A

94

52

54

55

57

56

XOR A,#d8

XOR A,dir

XOR A,@EP

XOR A,@IX +off

XOR A,Ri

AND A

58 to 5F

62

AND A,#d8

AND A,dir

64

65

(A) ← (AL) (dir)

(Continued)

40

MB89930A Series

(Continued)

Mnemonic

~

#

Operation

(A) ← (AL) ( (EP) )

TL

TH AH NZVC OP code

AND A,@EP

AND A,@IX +off

AND A,Ri

OR A

OR A,#d8

3

4

3

2

3

4

3

5

4

5

4

3

1

2

1

2

1

2

1

3

2

3

2

1

–

+ + R –

+ + + +

– – – –

67

66

68 to 6F

72

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(A) ← (AL) (TL)

(A) ← (AL) d8

(A) ← (AL) (dir)

(A) ← (AL) ( (EP) )

(A) ← (AL) ( (IX) +off)

(A) ← (AL) (Ri)

(dir) – d8

74

75

77

76

OR A,dir

OR A,@EP

OR A,@IX +off

OR A,Ri

CMP dir,#d8

CMP @EP,#d8

CMP @IX +off,#d8

CMP Ri,#d8

INCW SP

78 to 7F

95

97

96

98 to 9F

C1

( (EP) ) – d8

( (IX) + off) – d8

(Ri) – d8

(SP) ← (SP) + 1

(SP) ← (SP) – 1

DECW SP

D1

Table 4 Branch Instructions (17 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

BZ/BEQ rel

BNZ/BNE rel

BC/BLO rel

BNC/BHS rel

BN rel

BP rel

BLT rel

3

5

2

3

6

3

4

6

2

3

1

3

1

3

1

If Z = 1 then PC ← PC + rel

If Z = 0 then PC ← PC + rel

If C = 1 then PC ← PC + rel

If C = 0 then PC ← PC + rel

If N = 1 then PC ← PC + rel

If N = 0 then PC ← PC + rel

If V N = 1 then PC ← PC + rel

If V N = 0 then PC ← PC + reI

If (dir: b) = 0 then PC ← PC + rel

If (dir: b) = 1 then PC ← PC + rel

(PC) ← (A)

(PC) ← ext

Vector call

Subroutine call

(PC) ← (A),(A) ← (PC) + 1

Return from subrountine

Return form interrupt

–

dH

–

– – – –

– + – –

– – – –

Restore

FD

FC

F9

F8

FB

FA

FF

FE

BGE rel

BBC dir: b,rel

BBS dir: b,rel

JMP @A

JMP ext

CALLV #vct

CALL ext

XCHW A,PC

RET

B0 to B7

B8 to BF

E0

21

E8 to EF

31

F4

20

30

RETI

–

Table 5 Other Instructions (9 instructions)

Mnemonic

~

#

Operation

TL

TH AH NZVC OP code

PUSHW A

POPW A

PUSHW IX

POPW IX

NOP

CLRC

SETC

4

1

–

dH

–

– – – –

– – – R

– – – S

– – – –

40

50

41

51

00

81

91

80

90

CLRI

SETI

41

MB89930A Series

■ INSTRUCTION MAP

42

MB89930A Series

■ MASK OPTIONS

Part number

MB89935A/B

MB89P935A

MB89PV930A

No

Specify when order-

ing masking

Specifying procedure

Setting not possible

Selection of initial value of main

clock oscillation settling time*

(with F^CH= 10 MHz)

01 : 2¹⁴/FCH (Approx.1.63 ms)

10 : 2¹⁷/FCH (Approx.13.1 ms)

11 : 2¹⁸/FCH (Approx.26.2 ms)

Fixed to 2¹⁸/FCH

(Approx. 26.2 ms)

Fixed to 2¹⁸/FCH

(Approx. 26.2 ms)

1

Selectable

Power-on reset selection

With power-on reset

2

3

Selectable

Available

Without power-on reset

Reset pin output

With reset output

Without reset output

With reset output

FCH : Main clock oscillation frequency

* : Initial value to which the oscillation settling time bit (SYCC : WT1, WT0) in the system clock control register is set

■ ORDERING INFORMATION

Part number

MB89935APFV

MB89935BPFV

MB89P935APFV

Package

Remarks

30-pin Plastic SSOP

(FPT-30P-M02)

48-pin Ceramic MQFP

(MQP-48C-P01)

MB89PV930ACFV

43

MB89930A Series

■ PACKAGE DIMENSIONS

30-pin plastic LQFP

(FPT-30P-M02)

* : This dimension does not include resin protrusion.

1.25 –⁺0⁰.^.1²0⁰

*

9.70±0.10(.382±.004)

(Mounting height)

.049 ⁺^–.^.⁰⁰⁰⁰⁴⁸

0.10(.004)

5.60±0.10

(.220±.004) (.299±.008)

7.60±0.20

6.60(.260)

NOM

INDEX

"A"

0.65±0.12(.0256±.0047)

0.22 –⁺0⁰.^.0¹5⁰

.009 ⁺^–.^.⁰⁰⁰⁰²⁴

0.15 –⁺0⁰.^.0⁰2⁵

.006 ⁺^–.^.⁰⁰⁰⁰¹²

Details of "A" part

0.10±0.10(.004±.004)

(STAND OFF)

9.10(.358)REF

0

10°

0.50±0.20

(.020±.008)

C

1994 FUJITSU LIMITED F30003S-2C-3

Dimensions in mm (inches)

(Continued)

44

MB89930A Series

(Continued)

48-pin ceramic MQFP

(MQP-48C-P01)

17.20(.677)TYP

15.00±0.25

(.591±.010)

1.50(.059)TYP

1.00(.040)TYP

8.80(.346)REF

PIN No.1 INDEX

14.82±0.35

(.583±.014)

0.80±0.22

(.0315±.0087)

PIN No.1 INDEX

1.02±0.13

(.040±.005)

10.92 –⁺0⁰.^.0¹³

.430 –⁺0^.005

8.71(.343)

TYP

7.14(.281)

TYP

PAD No.1 INDEX

4.50(.177)TYP

1.10 ⁺^–0⁰^.^.²⁴⁵⁵

.043 ⁺^–.^.⁰⁰¹¹⁰⁸

0.40±0.08

(.016±.003)

0.60(.024)TYP

0.30(.012)TYP

8.50(.335)MAX

0.15±0.05

(.006±.002)

C

1994 FUJITSU LIMITED M48001SC-4-2

Dimensions in mm (inches)

45

MB89930A Series

FUJITSU LIMITED

For further information please contact:

Japan

FUJITSU LIMITED

Corporate Global Business Support Division

Electronic Devices

The contents of this document are subject to change without notice.

Customers are advised to consult with FUJITSU sales

representatives before ordering.

Shinjuku Dai-Ichi Seimei Bldg. 7-1,

Nishishinjuku 2-chome, Shinjuku-ku,

Tokyo 163-0721, Japan

Tel: +81-3-5322-3347

Fax: +81-3-5322-3386

The information and circuit diagrams in this document are

presented as examples of semiconductor device applications, and

are not intended to be incorporated in devices for actual use. Also,

FUJITSU is unable to assume responsibility for infringement of

any patent rights or other rights of third parties arising from the use

of this information or circuit diagrams.

http://edevice.fujitsu.com/

North and South America

FUJITSU MICROELECTRONICS, INC.

3545 North First Street,

San Jose, CA 95134-1804, U.S.A.

Tel: +1-408-922-9000

Fax: +1-408-922-9179

The contents of this document may not be reproduced or copied

without the permission of FUJITSU LIMITED.

Customer Response Center

Mon. - Fri.: 7 am - 5 pm (PST)

Tel: +1-800-866-8608

FUJITSU semiconductor devices are intended for use in standard

applications (computers, office automation and other office

equipments, industrial, communications, and measurement

equipments, personal or household devices, etc.).

Fax: +1-408-922-9179

http://www.fujitsumicro.com/

CAUTION:

Europe

Customers considering the use of our products in special

applications where failure or abnormal operation may directly

affect human lives or cause physical injury or property damage, or

where extremely high levels of reliability are demanded (such as

aerospace systems, atomic energy controls, sea floor repeaters,

vehicle operating controls, medical devices for life support, etc.)

are requested to consult with FUJITSU sales representatives before

such use. The company will not be responsible for damages arising

from such use without prior approval.

FUJITSU MICROELECTRONICS EUROPE GmbH

Am Siebenstein 6-10,

D-63303 Dreieich-Buchschlag,

Germany

Tel: +49-6103-690-0

Fax: +49-6103-690-122

http://www.fujitsu-fme.com/

Asia Pacific

FUJITSU MICROELECTRONICS ASIA PTE. LTD.

#05-08, 151 Lorong Chuan,

New Tech Park,

Any semiconductor devices have inherently a certain rate of failure.

You must protect against injury, damage or loss from such failures

by incorporating safety design measures into your facility and

equipment such as redundancy, fire protection, and prevention of

over-current levels and other abnormal operating conditions.

Singapore 556741

Tel: +65-281-0770

Fax: +65-281-0220

http://www.fmap.com.sg/

If any products described in this document represent goods or

technologies subject to certain restrictions on export under the

Foreign Exchange and Foreign Trade Control Law of Japan, the

prior authorization by Japanese government should be required for

export of those products from Japan.

Korea

FUJITSU MICROELECTRONICS KOREA LTD.

1702 KOSMO TOWER, 1002 Daechi-Dong,

Kangnam-Gu,Seoul 135-280

Korea

Tel: +82-2-3484-7100

Fax: +82-2-3484-7111

F0010

FUJITSU LIMITED Printed in Japan


型号：	MB89P935APFV
厂家：	FUJITSU
描述：	8-bit Proprietary Microcontroller 8位微控制器专有微控制器外围集成电路光电二极管可编程只读存储器时钟
文件：	总46页 (文件大小：588K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MB89P935APFV [FUJITSU]

相关型号：

MB89P935B

MB89P935BPFV

MB89P945

MB89P945PF

MB89P945PF

MB89P955

MB89P955PFM

MB89P965A

MB89P965APF

MB89P965APFM

MB89P965APFV1

MB89P965PFM