IC-MQTSSOP20 [ICHAUS]
PROGRAMMABLE 9-BIT Sin/Cos INTERPOLATION IC WITH RS422 DRIVER; 可编程的9位正弦/余弦插值用IC RS422驱动器
| 型号： | IC-MQTSSOP20 |
| 厂家： | 
IC-HAUS GMBH |
| 描述： | PROGRAMMABLE 9-BIT Sin/Cos INTERPOLATION IC WITH RS422 DRIVER |
| 文件： | 总39页 (文件大小：816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 1/39
FEATURES
APPLICATIONS
♦ Optical and magnetic position
sensors
♦ Angle encoders
♦ Linear scales
♦ Latency-free sine-to-digital conversion to 400 angle steps
♦ 500 kHz input frequency for interpolation factors of x1 and x2
(10 kHz for x100)
♦ Flexible pin assignment due to signal path multiplexers
♦ PGA inputs for differential and single-ended signals
♦ Variable input resistance for current/voltage conversion
♦ Signal conditioning for offset, amplitude and phase
♦ Controlled 50 mA current source for LED or MR sensor supply
♦ Fault-tolerant RS422 outputs with 50 mA sink/source drive
current
♦ Preselectable minimum phase distance for spike-proof counter
stimulus
PACKAGES
♦ Zero signal conditioning and electronic index pulse generation
♦ Signal and operation monitoring with configurable alarm
output, output shutdown and error storage
♦ I2C multimaster interface for in-circuit calibration and
parameters (EEPROM)
♦ Adjustable overtemperature alarm and shutdown
♦ Supply from 4.3 to 5.5 V, operation from -25(-40) to +100 °C
♦ Reverse polarity proof including the sub-system
TSSOP20
BLOCK DIAGRAM
VDDS
VDD
GND
REVERSE POLARITY
PROTECTION
iC-MQ
GNDS
SCL
MONITORING
ERR
C
SERIAL I2C
INTERFACE
CONFIGURATION
REGISTER
SINE-TO-DIGITAL
CONVERSION
Tw
LineCount
Monitor
Sin/Cos
Monitor
PWRon
Toff
SDA
PHI
PGA INPUT
I/V
SIGNAL PATH MUX
CALIBRATION
DIGITAL DRIVER
OUTPUT
X1
PZ
NZ
PB
NB
PA
NA
x
ZIN
CH0
-
-
-
X2
I/V
I/V
I/V
I/V
I/U
x
SIGNAL LEVEL
CONTROLLER
X3
x
CH1
x
x
+
X4
+
-
x
X5
x
ADJ
CH2
x
X6
x
ACO
Copyright © 2006, 2010 iC-Haus
http://www.ichaus.com
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 2/39
DESCRIPTION
Interpolator iC-MQ is a non-linear A/D converter A control signal is generated from the conditioned
which digitizes sine/cosine sensor signals using a signals which can track the transmitting LED of op-
count-safe tracking conversion principle with se- tical encoders via the integrated 50 mA driver stage
lectable resolution and hysteresis. The angle reso- (output ACO). If MR sensors are connected this
lution per sine period can be set using SELRES; up driver stage can also track the power supply of the
to 400 angle steps are possible (see page 26).
measuring bridges. By tracking the sensor energy
supply any temperature and aging effects are com-
The angle position is output incrementally by differ- pensated for, the input signals stabilized and the ex-
ential RS422 drivers as an encoder quadrature signal act calibration of the input signals is maintained. This
with a zero pulse or, if selected, as a counter signal enables a constant accuracy of the interpolation cir-
for devices compatible with 74HC191 or 74HC193.
cuit across the entire operating temperature range.
The zero pulse is generated electronically when an When control limits are reached, these can be indi-
enable has been set by the X1/X2 inputs. This pulse cated at the maskable error pin ERR. Faults such as
can be configured extensively: both in its relative po- overdrive, wire breakage, short circuiting, dirt or ag-
sition to the input signal with regard to the logic gating ing, for example, are logged.
with A and/or B and in its width from 90° to 360° (1/4
to 1 T).
iC-MQ includes extensive self-test and system diag-
nosis functions which check whether the sensor is
A preselectable minimum transition distance permits working properly or not. For all error events the user
glitch-free output signals and prevents counting er- can select whether the fault be displayed at error pin
rors which in turn boosts the noise immunity of the ERR or the outputs shutdown. At the same time er-
position encoder.
rors can be stored in the EEPROM to enable failures
to be diagnosed at a later stage. For encoder ap-
Programmable instrumentation amplifiers with se- plications the line count of the code disc, the sensor
lectable gain levels allow differential or single-ended, signal regarding signal level and frequency and the
referenced input signals; via input X2 the external ref- operating temperature can be monitored, for exam-
erence can be used as reference voltage for the off- ple, the latter using an adjustable on-chip sensor.
set correction.
Display error pin ERR is bidirectional; a system fault
The modes of operation differentiate between high recognized externally can be recorded and also reg-
impedance (V modes) and low impedance (I modes). istered in the error memory.
This adaptation of the iC to voltage or current signals
enables MR sensor bridges or photosensors to be di- iC-MQ is protected against reverse polarity and of-
rectly connected up to the device. The optical scan- fers its monitored supply voltage to the external cir-
ning of low resolution code discs is also supported by cuit, thus extending the protection to the system (for
the reference function of input X2; these discs do not load currents to 20 mA). Reverse polarity protection
evaluate tracks differentially but in comparison with a also covers the short-circuit-proof line drivers so that
reference photodiode.
an unintentional faulty wiring during initial operation
is tolerated.
The integrated signal conditioning unit allows signal
amplitudes and offset voltages to be calibrated accu- On being activated the device configuration is loaded
rately and also any phase error between the sine and via the serial configuration interface from an exter-
cosine signals to be corrected. The channel for the nal EEPROM and verified by a CRC. A microcon-
zero signal can be configured separately.
troller can also configure iC-MQ; the implemented in-
terface is multimaster-competent and enables direct
RAM access.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 3/39
CONTENTS
PACKAGES
4
5
1. Photodiode array connected to current
inputs, LED supply with constant
current source . . . . . . . . . . . . . . 23
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
2. Encoder supplying 100 mVpp to voltage
inputs . . . . . . . . . . . . . . . . . . . 23
5
SIGNAL CONDITIONING CH0
24
ELECTRICAL CHARACTERISTICS
PROGRAMMING
6
Gain Settings CH0 . . . . . . . . . . . . . . . 24
Offset Calibration CH0 . . . . . . . . . . . . . 24
11
12
14
SIGNAL LEVEL CONTROL and SIGNAL
REGISTER MAP
MONITORING
25
26
27
SERIAL CONFIGURATION INTERFACE
SINE-TO-DIGITAL CONVERSION
OUTPUT SETTINGS AND ZERO SIGNAL
Example of CRC Calculation Routine . . . . . 14
EEPROM Selection . . . . . . . . . . . . . . 14
I2C Slave Mode (ENSL = 1) . . . . . . . . . . 15
Zero Signal Generation . . . . . . . . . . . . 27
Description Of CFGABZ Setup . . . . . . . . 28
Setup Example 1 . . . . . . . . . . . . . . . . 28
Setup Example 2 . . . . . . . . . . . . . . . . 28
Output Driver Configuration . . . . . . . . . . 29
Minimum Phase Distance . . . . . . . . . . . 29
BIAS CURRENT SOURCE AND
TEMPERATURE SENSOR CALIBRATION
16
Bias Current . . . . . . . . . . . . . . . . . . 16
Temperature Sensor . . . . . . . . . . . . . . 16
OPERATING MODES
17
ERROR MONITORING AND ALARM OUTPUT
30
Mode ABZ . . . . . . . . . . . . . . . . . . . 17
Mode 191/193 . . . . . . . . . . . . . . . . . 17
Calibration 1, 2, 3 . . . . . . . . . . . . . . . 17
TEST 6 . . . . . . . . . . . . . . . . . . . . . 18
System Test . . . . . . . . . . . . . . . . . . 18
Error Protocol . . . . . . . . . . . . . . . . . . 31
Line Count Error . . . . . . . . . . . . . . . . 31
Temperature Monitoring . . . . . . . . . . . . 31
REVERSE POLARITY PROTECTION
32
33
TEST MODE
INPUT CONFIGURATION
19
Quick programming in the
Current Signals . . . . . . . . . . . . . . . . . 19
Voltage Signals . . . . . . . . . . . . . . . . . 19
single master system . . . . . . . . . . . 34
Quick programming in the
multimaster system . . . . . . . . . . . . 34
SIGNAL PATH MULTIPLEXING
20
21
EXAMPLE APPLICATIONS
APPLICATION HINTS
35
37
SIGNAL CONDITIONING CH1, CH2
Gain Settings . . . . . . . . . . . . . . . . . . 21
Offset Calibration CH1, CH2 . . . . . . . . . 22
Phase Correction CH1 vs. CH2 . . . . . . . . 22
Signal Conditioning Examples . . . . . . . . 23
In-circuit programming of the EEPROM . . . 37
Absolute angle accuracy and edge jitter . . . 37
Information on the demo board . . . . . . . . 37
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 4/39
PACKAGES
PIN CONFIGURATION TSSOP20
PIN FUNCTIONS
No. Name Function
1 X1
2 X2
3 X3
4 X4
Signal Input 1 (Index +)
Signal Input 2 (Index -)
Signal Input 3
Signal Input 4
5 VDDS Switched Supply Output
(reverse polarity proof, load to 20 mA
max.)
6 GNDS Switched Ground
(reverse polarity proof)
7 X5
8 X6
Signal Input 5
Signal Input 6
9 ACO Signal Level Controller,
high-side current source output
10 SDA Serial Configuration Interface,
data line
11 SCL
Serial Configuration Interface,
clock line
12 NB
13 PB
14 NA
15 PA
Incremental Output B-
Incremental Output B+
Incremental Output A-
Incremental Output A+
16 GND Ground
17 VDD +4.3...5.5 V Supply Voltage
18 NZ
19 PZ
Incremental Output Z-
Incremental Output Z+
20 ERR Error Signal (In/Out) / Test Mode Trigger
Input
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 5/39
ABSOLUTE MAXIMUM RATINGS
These ratings do not imply operating conditions; functional operation is not guaranteed. Beyond these ratings device damage may occur.
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Max.
G001 V()
Voltage at VDD, PA, NA, PB, NB, PZ,
NZ, SCL, SDA, ACO
-6
6
V
G002 V()
G003 V()
G004 V()
Voltage at ERR
-6
8
6
V
V
V
Pin-Pin Voltage
Voltage at X1...X6, SCL, SDA
-0.3
VDDS +
0.3
G005 I(VDD)
G006 I()
Current in VDD
-20
-50
400
50
mA
mA
mA
mA
mA
kV
Current in VDDS, GNDS
Current in X1...X6, SCL, SDA, ERR
Current in PA, NA, PB, NB, PZ, NZ
Current in ACO
G007 I()
-20
20
G008 I()
-100
-100
100
20
G009 I(ACO)
G010 Vd()
G011 Ptot
G012 Tj
ESD Susceptibility at all pins
Permissible Power Dissipation
Junction Temperature
HBM 100 pF discharged through 1.5 kΩ
2
300
150
150
mW
°C
-40
-40
G013 Ts
Storage Temperature
°C
THERMAL DATA
Item Symbol
No.
Parameter
Conditions
Unit
°C
Min. Typ. Max.
-25 100
T01 Ta
Operating Ambient Temperature Range
(extended range to -40 °C on request)
T02 Rthja
Thermal Resistance Chip to Ambient
80
K/W
All voltages are referenced to pin GNDS unless otherwise stated.
All currents flowing into the device pins are positive; all currents flowing out of the device pins are negative.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 6/39
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 °C...125 °C, IBN calibrated to 200 µA, unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
Total Device
001
V(VDD)
Permissible Supply Voltage
Supply Current
Load current I(VDDS) to 10 mA
Load current I(VDDS) to 20 mA
4.3
4.5
5.5
5.5
V
V
002
I(VDD)
Tj = -40...125 °C, no load
Tj = 27 °C, no load
25
mA
mA
12
003 I(VDDS)
004 Vcz()hi
005 Vc()hi
Permissible Load Current VDDS
Clamp-Voltage hi at all pins
-20
0
mA
V
11
1.5
Clamp-Voltage hi at Inputs SCL, Vc()hi = V() - V(VDD), I() = 1 mA
SDA
0.4
0.3
V
006 Vc()hi
007 Vc()lo
Clamp-Voltage hi at Inputs
X1...X6
Vc()hi = V() - V(VDD), I() = 4 mA
1.2
V
V
Clamp-Voltage lo at all pins
I() = -4 mA
-1.2
-0.3
Signal Conditioning, Inputs X1...X6 (CH1, CH2: i = 12, CH0: I = 0)
101
Vin()sig
Permissible Input Voltage Range
RINi() = 0x01
0.75
0
VDDS
− 1.5
VDDS
V
V
RINi() = 0x09
102
Iin()sig
Permissible Input Current Range
RINi(0) = 0; BIASi = 0
RINi(0) = 0; BIASi = 1
-300
10
-10
300
µA
µA
103 Iin()
104
Input Current
RINi() = 0x01
-10
10
µA
Rin()
Input Resistance vs. VREFin
Tj = 27 °C;
RINi(3:0) = 0x09
RINi(3:0) = 0x00
RINi(3:0) = 0x02
RINi(3:0) = 0x04
RINi(3:0) = 0x06
16
1.1
1.6
2.2
3.2
20
1.6
2.3
3.2
4.6
24
2.1
3.0
4.2
6.0
kΩ
kΩ
kΩ
kΩ
kΩ
105 TC(Rin)
Temperature Coefficient of Rin
0.15
%/K
106
VREFin() Reference Voltages
RINi(0) = 0, BIASi = 1
RINi(0) = 0, BIASi = 0
1.35
2.25
1.5
2.5
1.65
2.75
V
V
VREFin0, VREFin12
107
G0, G12
Selectable Gain Factors
RINi(3) = 0, GRi and GFi = 0x0
RINi(3) = 0, GRi and GFi = max.
2
100
RINi(3) = 1, GRi and GFi = 0x0
RINi(3) = 1, GRi and GFi = max.
0.5
25
108
109
Gdiff
Relative Gain Ratio CH1 vs. CH2
GF2 = 0x10, GF1 = 0x0
GF2 = 0x10, GF1 = 0x7F
39
255
%
%
∆G
Step Width Of Fine Gain
Adjustment
for CH0
for CH1
for CH2
1.06
1.015
1.06
110 INL(Gi)
111
Integral Linearity Error of Gain
Adjustment
-1.06
1.06
Vin()diff
Recommended Differential Input
Voltage
Vin()diff = V(PCHx) - V(NCHx);
RINi(3) = 0
RINi(3) = 1
10
40
500
2000
mVpp
mVpp
112 Vin()os
113
Input Offset Voltage
referred to side of input
25
µV
VOScal
Offset Calibration Range
referenced to the selected source (VOS0 resp.
VOS12), mode Calibration 2;
ORi = 00
ORi = 01
ORi = 10
ORi = 11
±100
±200
±600
±1200
%V()
%V()
%V()
%V()
114 ∆OF0
115 ∆OF12
116 INL(OFi)
117 PHI12
CH0 Offset Calibration Step
Width
referenced to the selected source VOS0;
OR0 = 0x0
3.2
%
CH1/2 Offset Calibration Step
Width
referenced to the selected source VOS12;
OR12 = 0x0
0.79
%
Integral Linearity Error of Offset limited test coverage (guaranteed by design)
Calibration
-5
5
LSB
°
Phase Error Calibration Range
CH1 vs. CH2
±20.2
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 7/39
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 °C...125 °C, IBN calibrated to 200 µA, unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
0.8
118 ∆PHI12
Phase Error Calibration Step
Width
0.63
°
°
119 INL(PHI12) Integral Linearity Error of Phase limited test coverage (guaranteed by design)
Calibration
-0.8
120 fin()
Permissible Maximum Input Freq. analog signal path
Output Voltage at X2 BIASEX = 10, I(X2) = 0, referenced to VRE-
Fin12
200
95
kHz
%
121 Vout(X2)
100
105
122 Vin(X2)
123 Rin(X2)
Permissible Input Voltage Range BIASEX = 11
at X2
0.5
20
VDDS
− 2
30
V
Input Resistance at X2
BIASEX = 11, RIN0(3:0) = 0x01, RIN12(3:0) =
27
kΩ
0x01
Sine-To-Digital Conversion
201 AAabs Absolute Angle Accuracy
referenced to 360° input signal, ideal waveform,
quasi static signals, adjusted signal condition-
ing, SELHYS = 0
0.9
1.8
°
202
AArel
Relative Angle Accuracy
referenced to output period T (see Fig. 1), ideal
waveform, quasi static signals;
at 4 edges per period
10
10
10
10
%
%
%
%
at 100 edges per period
at 384 edges per period
at 400 edges per period
<0.5
<2
203 AAR
Repeatability
see 201; VDD = const., Tj = const.
0.1
°
Line Driver Outputs PA, NA, PB, NB, PZ, NZ
501
Vs()hi
Saturation Voltage hi
Vs() = VDD - V();
SIK(1:0) = 00, I() = -1.2 mA
SIK(1:0) = 01, I() = -4 mA
SIK(1:0) = 10, I() = -20 mA
SIK(1:0) = 11, I() = -50 mA
200
200
400
700
mV
mV
mV
mV
502
503
Vs()lo
Isc()hi
Saturation Voltage lo
SIK(1:0) = 00, I() = 1.2 mA
SIK(1:0) = 01, I() = 4 mA
SIK(1:0) = 10, I() = 20 mA
SIK(1:0) = 11, I() = 50 mA
200
200
400
700
mV
mV
mV
mV
Short-Circuit Current hi
V() = 0 V;
SIK(1:0) = 00
SIK(1:0) = 01
SIK(1:0) = 10
SIK(1:0) = 11
-4
-12
-60
-150
-1.2
-4
-20
-50
mA
mA
mA
mA
504
505
506
Isc()lo
tr()
Short-Circuit Current lo
Rise Time
V() = VDD;
SIK(1:0) = 00
SIK(1:0) = 01
SIK(1:0) = 10
SIK(1:0) = 11
1.2
4
20
50
4
12
60
150
mA
mA
mA
mA
RL = 100 Ω to GND;
SSR(1:0) = 00
SSR(1:0) = 01
SSR(1:0) = 10
SSR(1:0) = 11
5
5
20
50
20
40
140
350
ns
ns
ns
ns
tf()
Fall Time
RL = 100 Ω to VDD;
SSR(1:0) = 00
SSR(1:0) = 01
SSR(1:0) = 10
SSR(1:0) = 11
5
5
30
50
20
40
140
350
ns
ns
ns
ns
507 Ilk()tri
508 IIk()rev
509 Rin()cal
510 I()cal
Leakage Current
TRIHL(1:0) = 11 (tristate)
reversed supply voltage
20
100
2.5
100
µA
µA
kΩ
µA
Leakage Current
Test Signal Source Impedance
Permissible Test Signal Load
Op. modes Calibration 1, 2, 3
Op. modes Calibration 1, 2, 3
4
3
-3
511
tclk()lo
Clock Signal Low-Pulse Duration
for CP, CPD, CPU
Op. mode Mode 191/193;
MTD = 0x0
110
800
ns
ns
MTD = 0x7
512 tw()hi
Duty Cycle
referenced to output period T, see Fig. 1
50
%
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 8/39
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 °C...125 °C, IBN calibrated to 200 µA, unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
513 tAB
Phase Shift A vs. B
see Fig. 1
25
%
514
tMTD
Minimum Phase Distance
edge to edge, see Fig. 1;
MTD = 0x0, IBN calibrated to 200 µA
MTD = 0x0, IBN calibrated to 220 µA
220
200
ns
ns
515 ∆t()MTD Minimum Phase Distance Toler- nominal values in Table 52
-18
13.5
%
ance
516 ∆t()MTD Minimum Phase Distance Varia- variation versus VDD = 5 V, Tj = 27 °C due to
+/- 2
%
tion
VDD = 4.3...5.5 V or Tj = -40...125 °C
Signal Level Controller ACO
601
Vs()hi
Saturation Voltage hi
Vs() = VDD - V();
ADJ(8:0) = 0x11F, I(ACO) = -5 mA
ADJ(8:0) = 0x13F, I(ACO) = -10 mA
ADJ(8:0) = 0x15F, I(ACO) = -25 mA
ADJ(8:0) = 0x17F, I(ACO) = -50 mA
1
1
1
V
V
V
V
1.2
602
Isc()hi
Short-Circuit Current hi
V() = 0 ... VDD - 1 V;
ADJ(8:0) = 0x11F
ADJ(8:0) = 0x13F
ADJ(8:0) = 0x15F
V() = 0 ... VDD - 1.2 V;
ADJ(8:0) = 0x17F
-10
-20
-50
-5
-10
-25
mA
mA
mA
-100
-50
mA
603 It()min
604 It()max
605 Vt()min
606 Vt()max
Control Range Monitoring 1:
lower limit
referenced to range ADJ(6:5)
referenced to range ADJ(6:5)
referenced to Vscq()
3
%Isc
Control Range Monitoring 2:
upper limit
90
%Isc
%Vpp
%Vpp
Signal Level Monitoring 1:
lower limit
40
Signal Level Monitoring 2:
upper limit
referenced to Vscq()
130
Bias Current Source and Reference Voltages
801
IBN
Bias Current Source
Calibration 1, I(NB) vs. VDDS;
CFGIBN = 0x0
110
µA
µA
µA
CFGIBN = 0xF
IBN calibrated at T = 25 °C
370
220
180
1.2
45
200
1.25
50
802 VBG
Internal Bandgap Reference
Reference Voltage
1.3
55
V
803 VPAH
804 V05
%VDDS
mV
Reference Voltage V05
Reference Voltage V025
450
500
50
550
805 V025
%V05
Power-Down-Reset
901 VDDon
Turn-on Threshold VDD, Power- increasing voltage at VDD
Up-Enable
3.6
3.0
0.4
4.0
3.5
4.3
3.8
V
V
V
902 VDDoff
Turn-off Threshold VDD, Power- decreasing voltage at VDD
Down-Reset
903 VDDhys
Hysteresis
Error Signal Input/Output, Pin ERR
B01 Vs()lo
B02 Isc()lo
Saturation Voltage lo
versus GND, I() = 4 mA
0.4
8
V
Short-Circuit Current lo
versus GND, V(ERR) ≤ VDD
versus GND, V(ERR) > VTMon
L state
Z state
4
5
mA
B03
Isc()
Low-Side Current Source For
Data Output
2
0
mA
mA
B04 Vt()hi
B05 Vt()lo
B06 Vt()hys
B07 Ipu()
Input Threshold Voltage hi
Input Threshold Voltage lo
Input Hysteresis
versus GND
2
V
V
versus GND
0.8
300
-400
Vt()hys = Vt()hi − Vt()lo
V() = 0...VDD − 1 V, EPU = 1
Vpu() = VDD − V(), I() = -5 µA, EPU = 1
increasing voltage at ERR
500
mV
µA
V
Input-Pull-Up-Current
Pull-Up-Voltage
-300
-200
0.4
B08 Vpu()
B09 VTMon
Test Mode Turn-on Threshold
VDD +
2
V
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 9/39
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 4.3...5.5 V, Tj = -40 °C...125 °C, IBN calibrated to 200 µA, unless otherwise stated
Item Symbol
No.
Parameter
Conditions
Unit
Min.
Typ.
Max.
B10 VTMoff
Test Mode Turn-off Threshold
decreasing voltage at ERR
VDD +
0.5
V
B11 VTMhys
Test Mode Threshold Hysteresis VTMhys = VTMon − VTMoff
0.15
0.3
V
B12
fclk()
Data Output Signal Frequency
ENFAST = 0
ENFAST = 1
120
480
160
640
200
800
kHz
kHz
B13 tp(ERR)in Process Delay for System Error upon power up (VDD > VDDon)
Message at ERR
10
ms
Reverse Polarity Protection and Supply Switches VDDS, GNDS
C01
Vs()
Saturation Voltage vs. VDD
Vs(VDDS) = VDD − V(VDDS);
I(VDDS) = -10...0 mA
150
250
mV
mV
I(VDDS) = -20...-10 mA
C02
Vs()
Saturation Voltage vs. GND
Vs(GNDS) = V(GNDS) − GND;
I(GNDS) = 0...10 mA
150
200
mV
mV
I(GNDS) = 10...20 mA
C03 Irev(VDD) Reversed Polarity Current
V(VDD) = −5.5V...−4.3 V
-1
4
0
mA
Serial Configuration Interface SCL, SDA
D01 Vs()lo
D02 Isc()lo
D03 Vt()hi
D04 Vt()lo
D05 Vt()hys
D06 Ipu()
D07 Vpu()
Saturation Voltage lo
Short-Circuit Current lo
Input Threshold Voltage hi
Input Threshold Voltage lo
Input Hysteresis
I = 4 mA
400
75
2
mV
mA
V
0.8
300
-600
V
Vt()hys = Vt()hi − Vt()lo
V() = 0...VDDS − 1 V
500
mV
µA
V
Input Pull-Up Current
Pull-Up Voltage
-300
-60
0.4
Vpu() = VDDS − V(), I() = -5 µA
D08
fclk()
Clock Frequency at SCL
ENFAST = 0
ENFAST = 1
60
240
80
320
100
400
kHz
kHz
D09
tbusy()cfg Duration of Startup Configuration
IBN not calibated, EEPROM access without
read failure, time to outputs operational;
ENFAST = 0
36
24
48
34
ms
ms
ENFAST = 1
D10
D11
tbusy()err End Of I2C Communication;
IBN not calibrated;
Time Until I2C Slave Is Enabled V(SDA) = 0 V
4
indef.
45
12
ms
ms
ms
ms
V(SCL) = 0 V or arbitration lost
no EEPROM
CRC ERROR
135
285
95
tp()
Start Of Master Activity On I2C
Protocol Error
SCL without clock signal: V(SCL) = constant;
IBN not calibrated
IBN calibrated to 200 µA
25
64
80
80
240
120
µs
µs
Temperature Monitoring
E01
VTs
Temperature Sensor Voltage
VTs() = VDDS − V(PA),
Calibration 3, without Load;
Tj = -40 °C
740
620
460
770
650
520
790
670
540
mV
mV
mV
Tj = 27 °C
Tj = 100 °C
E02 TCs
E03
Temp. Co. Temperature Sensor
Voltage
-1.8
mV/K
VTth
Temperature Warning Activation
Threshold
VTth() = VDDS - V(NA), Tj = 27 °C,
Calibration 3, without Load;
CFGTA(3:0) = 0x0
260
470
310
550
360
630
mV
mV
CFGTA(3:0) = 0xF
E04 TCth
E05
Temp. Co. Temperature Warning
Activation Threshold
0.06
%/K
Tw
Warning Temperature
CFGTA(3:0) = 0x0
CFGTA(3:0) = 0xF
125
140
65
°C
°C
80
25
25
E06 Thys
Warning Temperature Hysteresis 80 °C < Tj < 125 °C
10
5
15
15
°C
°C
E07 ∆T
Relative Shutdown Temperature ∆T = Toff − Tw
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 10/39
t
t
MTD
AB
B
A
t
whi
AArel
AArel
T
Figure 1: Definition of relative angle error and minimum phase distance
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 11/39
PROGRAMMING
Register Map, Overview . . . . . . . . . . . . . . . . . . . Page 12 Signal Conditioning CH0 (X1, X2) . . . . . . . . . Page 24
GR0:
GF0:
VOS0:
OR0:
OF0:
Gain Range CH0 (coarse)
Gain Factor CH0 (fine)
Offset Reference Source CH0
Offset Range CH0 (coarse)
Offset Factor CH0 (fine)
Serial Configuration Interface . . . . . . . . . . . . . Page 14
ENFAST:
ENSL:
I2C Fast Mode Enable
I2C Slave Mode Enable
DEVID:
Device ID of EEPROM providing the
chip configuration data (e.g. 0x50)
CRC of chip configuration data
(address range 0x00 to 0x2F)
Chip Release
CHKSUM:
Signal Level Controller . . . . . . . . . . . . . . . . . . . . Page 25
ADJ: Setup of ACO Output Function
CHPREL:
END:
Sine-To-Digital Conversion . . . . . . . . . . . . . . . . Page 26
SELRES:
SELHYS:
Configuration Enable
Resolution
Hysteresis
Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Page 16
CFGIBN:
CFGTA:
Bias Current
Temperature Monitoring
Quadrature Output Logic . . . . . . . . . . . . . . . . . . Page 27
CFGABZ: Output Logic
CFGZPOS: Zero Signal Positioning
ENZFF: Zero Signal Synchronisation
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . Page 17
MODE: Operating Mode
Input Configuration
and Signal Path Multiplexer . . . . . . . . . . . . . . . Page 19
Quadrature Output Settings . . . . . . . . . . . . . . . Page 29
MTD:
SIK:
SSR:
TRIHL:
Minimum Phase Distance
Driver Short-Circuit Current
Driver Slew Rate
INMODE:
RIN12:
Diff./Single-Ended Input Mode
I/V Mode and Input Resistance CH1,
CH2
Driver Mode
BIAS12:
RIN0:
BIAS0:
BIASEX:
INVZ:
Reference Voltage CH1, CH2
I/V Mode and Input Resistance CH0
Reference Voltage CH0
Input Reference Selection
Index Signal Inversion
Error Monitoring and Alarm Output . . . . . . . Page 30
EMTD:
EPH:
EPU:
Minimal Alarm Indication Time
Alarm Input/Output Logic
Alarm Output Pull-Up Enable
Error Mask For Alarm Indication (pin
ERR)
EMASKA:
MUXIN:
Input-To-Channel Assignment:
X3...X6 to CH1, CH2
EMASKE:
EMASKO:
PDMODE:
LINECNT:
Error Mask For Protocol (EEPROM)
Error Mask For Driver Shutdown
Driver Activation After Cycling Power
Line Count (Pulses) Between 2 Zero
Pulses
Error Protocol: First Error
Error Protocol: Last Error
Error Protocol: History
Signal Conditioning CH1, CH2 (X3...X6) . . . Page 21
GR12:
GF1:
Gain Range CH1, CH2 (coarse)
Gain Factor CH1 (fine)
GF2:
Gain Factor CH2 (fine)
VOS12:
VDC1:
VDC2:
OR1:
Offset Reference Source CH1, CH2
Intermediate Voltage CH1
Intermediate Voltage CH2
Offset Range CH1 (coarse)
Offset Factor CH1 (fine)
ERR1:
ERR2:
ERR3:
Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Page 33
OF1:
OR2:
OF2:
PH12:
Offset Range CH2 (coarse)
Offset Factor CH2 (fine)
Phase Correction CH1 vs. CH2
EMODE:
EMODE2:
Test Mode
Register And Address Selection For
Test Mode
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 12/39
REGISTER MAP
Register Map
Adr
Serial Configuration Interface
0x00 ENFAST
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DEVID(6:0)
Calibration
0x01
CFGIBN(3:0)
CFGTA(3:0)
Operating Mode
0x02
Input Configuration
0x03
END
1
0
ENZFF
0
MODE(3:0)
0
0
0
INVZ
INMODE
MUXIN(1:0)
Signalkonditionierung CH1, CH2
0x04
GF2(4:0)
GF1(3:0)
GR12(2:0)
0
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0
0
0
0
VDC1(0)
0
0
0
0
0
0
GF1(6:4)
VDC1(5:1)
OR1(0)
VDC2(5:0)
0
OF1(3:0)
0
0
0
OR1(1)
0
0
OR2(1:0)
OF1(7:4)
OF2(6:0)
0
PH12(2:0)
0
0
1
0
0
OF2(7)
BIASEX(1:0)
0
1
PH12(5:3)
RIN12(3:0)
1
BIAS12
VOS12(1:0)
Signal Level Controller
0x0F
0x10
ADJ(0)
—
0
1
0
0
0
0
ADJ(8:1)
Signal Conditioning CH0
0x11
0x12
GF0(4:0)
GR0(2:0)
OF0(5:0)
VOS0(1:0)
OR0(1:0)
0x13
0
BIAS0
RIN0(3:0)
Error Monitoring and Alarm Output
0x14
EMASKA(7:0)
EMTD(2:0)
EMASKO(7:0)
0x15
0x16
0x17
0x18
EMODE(1:0)
EMASKE(3:0)
EPH
EPU
EMASKA(9:8)
EMASKO(9:8)
ENSL
EMODE2
PDMODE
EMASKE(9:4)
Zero Signal Output
0x19
0x1A
CFGABZ(7:0)
CFGZPOS(7:0)
Sine-To-Digital Conversion, Minimum Phase Distance
0x1B
SELRES(7:0)
0x1C
0x1D
—
SELRES(14:8)
MTD(3:0)
SELHYS(3:0)
Output Driver Settings
0x1E
—
—
SIK(1:0)
SSR(1:0)
TRIHL(1:0)
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 13/39
Register Map
Adr
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Line Counter
0x1F
LINECNT(7:0)
LINECNT(13:8)
0x20
0
0
0
0
Reserved
0x21
0
0
1
0
0
0
0x22
0x00 (recommended programming)
0x00 (recommended programming)
free for OEM data
0x23
0x24
0x25
free for OEM data
0x26
free for OEM data
0x27
free for OEM data
0x28
free for OEM data
0x29
free for OEM data
0x2A
0x2B
0x2C
0x2D
0x2E
free for OEM data
free for OEM data
free for OEM data
free for OEM data
free for OEM data
Check Sum
0x2F
CHKSUM(7:0) of EEPROM data
[CHPREL(7:0), refer to Table 7]
Error Register
0x30
0x31
0x32
ERR1(7:0)
ERR2(5:0)
ERR1(9:8)
ERR3(3:0)
ERR2(9:6)
0x33
—
—
ERR3(9:4)
Notes
The device RAM initially contains random data following power-on.
Table 4: Register layout (EEPROM)
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 14/39
SERIAL CONFIGURATION INTERFACE
ENSL
Code
0
Adr 0x17, bit 3
The serial configuration interface consists of the two
pins SCL and SDA and enables read and write ac-
cess to an EEPROM with an I2C interface. The readout
clock rate can be selected using ENFAST.
Function
Normal operation
I2C Slave Mode Enable (Device ID 0x55)
1
Table 6: Config. Interface Mode
ENFAST
Code
0
Adr 0x00, bit 7
Function
The device ID for the EEPROM can be entered in reg-
ister DEVID(6:0) (address 0x00), from which iC-MQ
will take its configuration after exiting test mode (see
page 33). The DEVID stored therein is then accepted.
Regular clock rate, f(SCL) approx. 80 kHz
High clock rate, f(SCL) approx. 320 kHz
1
Notes
For in-circuit programming bus lines SCL and SDA
require pull-up resistors.
For line capacitances to 170 pF, adequate values
are:
4.7 kΩ with clock frequency 80 kHz
2 kΩ with clock frequency 320 kHz
Example of CRC Calculation Routine
unsigned char ucDataStream
int iCRCPoly 0x11D ;
unsigned char ucCRC=0;
int 0;
= 0;
The pull-up resistors may not be less than 1.5 kΩ.
To separate the signals a ground line between SCL
and SDA is recommended.
iC-MQ requires a supply voltage during EEPROM
programming (5 V to VDD).
=
i
=
ucCRC = 1; / / s t a r t value ! ! !
for ( iReg
= 0; iReg <47; iReg ++)
{
Table 5: Clock Frequency Configuration Interface
ucDataStream
for ( i =0; i <=7; i ++)
i f ( (ucCRC & 0x80 ) != ( ucDataStream & 0x80 ) )
ucCRC = (ucCRC << 1) iCRCPoly ;
else
ucCRC = (ucCRC << 1 ) ;
ucDataStream ucDataStream << 1;
= ucGetValue ( iReg ) ;
{
^
Once the supply has been switched on the iC-MQ out-
puts are high impedance (tristate*) until a valid config-
uration is read out from the EEPROM using device ID
0x50.
=
}
}
EEPROM Selection
The following minimal requirements must be fulfilled:
Bit errors in the 0x00 to 0x2F memory section are
pinpointed by the CRC deposited in register CHK-
SUM(7:0) (address 0x2F in the EEPROM; the CRC
polynomial used is "’1 0001 1101"’ with a start value
of "1").
• Operation from 3.3 to 5 V, I2C interface
• At least 512 bits, 64x8
(address range used is 0x00 to 0x3F)
Should the read configuration data not be confirmed
by the CRC, the readin process is repeated. If no valid
configuration data is available after a fourth readin, iC-
MQ terminates EEPROM access and switches to I2C
slave mode. This switch takes place after 150 ms at
the latest (see Electrical Characteristics, D11), for ex-
ample when no EEPROM is connected.
• Support of Page Write with Pages of at least 4
bytes. Errors can otherwise not be saved to the
EEPROM (EMASKE = 0x0).
• Device ID 0x50 "1010 000", no occupation of
0x55 (A2...A0 = 0). iC-MQ can otherwise not be
accessed via 0x55 in I2C slave mode.
For devices loading a valid configuration from the EEP-
ROM register bit ENSL decides whether the I2C slave Recommended device:
Atmel AT24C01B, ST
function is enabled or not.
M24C01W
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 15/39
I2C Slave Mode (ENSL = 1)
Register
Read access via I2C slave mode (ENSL = 1)
In this mode iC-MQ behaves like an I2C slave with the
device ID 0x55 and the configuration interface permits
write and read accesses to iC-MQ’s internal registers.
RAM Addr Content
0x00-0x21 Configuration data
(see EEPROM addresses 0x00-0x21)
0x22-0x2A Not available
0x2B-0x2E Configuration data
For chip release verification purposes an identification
value is stored under ROM address 0x2F; a write ac-
cess to this address is not permitted.
(see EEPROM addresses 0x2B-0x2E)
Chip release CHPREL(7:0)
0x30-0x33 Configuration data
(see EEPROM addresses 0x30-0x33)
0x2F
CHPREL
Code
0x00
Adr 0x2F, bit 7:0 (ROM)
Chip Release
Not available
iC-MQ 3
0x34-0x3A Not available
0x3B-0x3E Configuration data
(see EEPROM addresses 0x2B-0x2E)
0x04
0x3F
Chip release CHPREL(7:0)
0x08
iC-MQ X
0x40-0x43 Current error memory (only active when enabled by
EMASKE; messages will be transferred to
0x09
iC-MQ X1
EEPROM Addresses 0x30-0x33)
0x44-0x7F Not available
Table 7: Chip Release
Table 9: RAM Read Access
END
Code
0
Adr 0x02, bit 7
Function
Register
RAM Addr Access and conditions
Write access via I2C slave mode (ENSL = 1)
Sin/D converter and line driver disabled
(RAM configuration data invalid)
0x00
0x01
Changes possible, no restrictions
1
Restart of Sin/D conversion, line driver active
(RAM configuration data valid)
Changes possible
(wrong entries for CFGIBN can limit functions)
0x02
Changes to bits 6:0 are permitted only when Sin/D
conversion is halted (END = 0, ie. bit 7);
Table 8: Configuration Enable
Restarting Sin/D conversion by changing END (bit
7) is permitted only with no changes of operating
mode (bits 6:0 remain as set)
0x03-0x16 Changes possible, no restrictions
0x17
Changes to bits 7:4 and 2:0 are permitted
(ENSL, bit 3 must be kept 1)
0x18
Changes possible, no restrictions
0x19-0x21 Changes possible when Sin/D conversion is halted
(END = 0)
0x2B-0x2E Changes possible, no restrictions
0x2F-0x3F No write access permitted
0x40-0x43 No write access permitted
0x44-0x7F Not available
Table 10: RAM Write Access
Notes: The converter function should be halted by
END = 0 for the deletion of errors saved in the EEP-
ROM (Dev-ID 0x50, Addresses 0x30-0x33). Other-
wise active errors could be transferred to the EEP-
ROM again (from addresses 0x40-0x43 if enabled by
EMASKE).
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 16/39
BIAS CURRENT SOURCE AND TEMPERATURE SENSOR CALIBRATION
Bias Current
Example: VTs(T1) is ca. 650 mV, measured from
The calibration of the bias current source in operation VDDS versus PA, with T1 = 25 °C;
mode Calibration 1 (see Table 13) is prerequisite for
adherence to the given electrical characteristics and
The necessary reference voltage VTth(T1) is then cal-
also instrumental in the determination of the chip tim-
ing (e.g. clock frequency at SCL). For setup purposes
the IBN bias current is measured using a 10 kΩ resis-
tor by pin VDDS connected to pin NC. The setpoint is
200 µA which is equivalent to a voltage drop of 2 V.
culated. The required warning temperature T2, tem-
perature coefficients TCs and TCth (see Electrical
Characteristics, Section E) and measurement value
VTs(T1) are entered into this calculation:
CFGIBN
Code k
0x0
Adr 0x01, bit 7:4
31
39−k
31
39−k
VTs(T1) + TCs · (T2 − T1)
VTth(T1) =
IBN ∼
79 %
81 %
84 %
86 %
88 %
91 %
94 %
97 %
Code k
0x8
IBN ∼
100 %
103 %
107 %
111 %
115 %
119 %
124 %
129 %
1 + TCth · (T2 − T1)
0x1
0x9
0x2
0xA
0xB
0xC
0xD
0xE
0xF
0x3
Example: For T2 = T1 + 100 K VTth(T1) must be pro-
grammed to 443 mV.
0x4
0x5
0x6
Reference voltage VTth(T1) is provided for a high
impedance measurement (10 MΩ) at output pin NA
(measurement versus VDDS) and must be set by pro-
gramming CFGTA(3:0) to the calculated value.
0x7
Table 11: Calibration of Bias Current
Temperature Sensor
The temperature monitoring is calibrated in operating
mode Calibration 3.
Example: Altering VTth(T1) from 310 mV (measured
with CFGTA(3:0)= 0x0) to 443 mV is equivalent to
143 %, the closest value for CFGTA is 0x9;
To set the required warning temperature T2 the tem-
perature sensor voltage VTs at which the warning
message is generated is first determined. To this
end a voltage ramp from VDDS towards GNDS is ap-
plied to pin PA until pin ERR displays the warning
message. The following settings are required here:
EMASKA = 0x20, EMTD = 0x00 and EPH = 0x00.
CFGTA
Code k
0x0
Adr 0x01, bit 3:0
65+3k
VTth ∼
65
65+3k
65
Code k
0x8
VTth ∼
140 %
145 %
150 %
155 %
160 %
165 %
170 %
175 %
100 %
105 %
110 %
115 %
120 %
125 %
130 %
135 %
0x1
0x9
0x2
0xA
0xB
0xC
0xD
0xE
0xF
0x3
0x4
0x5
The signal at ERR first switches from tristate to low
(on reaching the warning threshold VTs) and then from
low to tristate (on overshooting the internal hysteresis
which is not relevant to calibration). To avoid confusion
a clear change of state (from low to high) must be gen-
erated with the help of an external pull-up resistor at
pin ERR.
0x6
0x7
Notes
With CFGTA = 0xF Toff is 80 °C typ.,
with CFGTA = 0x0 Toff is 155 °C typ.
Table 12: Calibration of Temperature Monitoring
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 17/39
OPERATING MODES
iC-MQ has various modes of operation, for which the coder quadrature signal with a zero pulse. Only in
functions of outputs PA, NA, PB, NB, PZ, NZ and ERR these modes are the line drivers and the reverse po-
are altered.
larity protection feature active.
Two operating modes can be selected for the out- In order to condition the input signals and to cali-
put of the angle position in normal operation. Mode brate and test iC-MQ Calibration and Test modes are
191/193 provides control signals for devices compati- available. Digital and analog test signals are pro-
ble with 74HC191 or 74HC193, whereas in Mode ABZ vided; the latter must always be measured at high load
the angle position is output incrementally as an en- impedance.
MODE(3:0)
Code
0x00
0x0F
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Addr. 0x02; bit 3:0
Operating Mode
Mode ABZ
Mode 191/193
Calibration 1
Calibration 2
Test 3*
PA
NA
PB
NB
PZ
NZ
ERR
ERR
ERR
IERR
A
not(A)
CPU
B
not(B)
nU/D
IBN
Z
not(Z)
nPL
CPD
CP
MR
TANAZ(2)
PCH1
VPAH
PS_out
PSIN
PCH1I
VTs
VREFIZ
NCH1
VPD
VREFISC
PCH2
—
PCH0
VDC1
IPF
NCH0
VDC2
V05
NCH2
CGUCK
NC_out
NCOS
NCH2I
—
IERR
IERR
IERR
res.
Test 4*
NS_out
NSIN
NCH1I
VTth
PC_out
PCOS
PCH2I
—
PZO
PZO
VDC1
VTTFE
NZO
NZO
VDC2
VTTSE
Test 5*
Test 6*
Calibration 3
Lo-Signal
Hi-Signal
Test 10*
ERR
All outputs and SCL, SDA, ERR to low level
All outputs to high level
TP
A4
A
CLK6
A8
CLK1
B4
CLK3/8
B8
ZIn
ZIn
Z
CLK4
TP1
not(Z)
—
System Test*
Test 12*
ERR
ERR
—
not(A)
—
B
not(B)
—
—
—
—
—
IDDQ Test*
Hints
All PU/PD resistors, oscillator and analog supply voltage deactivated.
*) Test function for iC-Haus device test only.
Table 13: Operating Modes
Mode 191/193
Mode ABZ
Pin
PA
Signal
CPD
CPU
CP
Description
In Mode ABZ A/B signals are generated and output via
PA, NA, PB and NB. A freely configurable zero signal
is simultaneously provided at pins PZ and NZ. The dif-
ferential RS422 line drivers are active; an Nx pin con-
stantly supplies a complementary signal which is the
inversion of pin Px.
Clock Down Pulse
Clock Up Pulse
Clock Pulse
NA
PB
NB
PZ
nU/D
MR
Count Direction (0: up, 1: down)
Asynch. Master Reset (active high)
Signal is ’1’ if index position is reached,
otherwise ’0’.
NZ
nPL
Asynch. Parallel Load Input (active low) /
Reset (active low)
Signal is ’0’ if index position is reached,
otherwise ’1’.
Table 14: Operating mode for counter devices compat-
ible with 74HC191 or 74HC193.
Mode 191/193
In Mode 191/193 the output pins provide control sig-
nals for counter devices compatible with 74HC191 or
74HC193 according to the following table. The driving
capability (SIK) and the slew rate (SSR) of the output Calibration 1, 2, 3
drivers must be selected so that the clock pulses can These modes are used to condition the input signals
be output with a low pulse of typically 50 ns (see Elec- and calibrate iC-MQ. In mode Calibration 1 the user
trical Characteristics, 511).
can measure the IBN bias current and the zero chan-
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 18/39
nel analog signals are available following signal condi- this end at a resolution of 8 the interpolator generates
tioning (PCH0 and NCH0).
a switchpoint every 45 degrees. The objective of the
calibration procedure is a pulse duty cycle of exactly
In mode Calibration 2 the conditioned sine and cosine 50% respectively for A4, B4 und A8, B8. The following
signals are output (PCH1, NCH1, PCH2 and NCH2). settings are required for mode System Test:
In addition intermediate potential VDC1 is provided for
compensating circuit CH1, as is intermediate potential
VDC2 for CH2 (for a description of the calibration pro-
cess, see page 21).
• MODE = 0x0B
• SELRES = 0x1B0
• SELHYS = 0xF
In mode Calibration 3 the internal temperature moni-
toring signals are provided. Calibration of the bias cur-
rent source and temperature monitoring is described
on page 16 and calibration of the zero channel on page
24.
• CFGABZ(7:4) = ’0000’
System Test
TEST 6
Pin
PA
Signal
A4
Description
Offset CH1
The input voltages at pins X3 to X6 can be checked in
mode Test 6. The following settings are required here:
NA
A8
Phase deviation from 90° between
CH1 and CH2
PB
NB
B4
B8
Offset CH2
• GF1 = 0x0
Amplitude deviation between
CH1 and CH2
• GF2 = 0x0
PZ
NZ
ZIn
Digital zero signal, unmasked
• Byte 0x05, bit 3:0 = ’0000’
• Byte 0x0F, bit 3 = ’1’
• Byte 0x0F, bit 4 = ’0’
TP1
Verification of line count (pulses) between
two zero pulses
Low signal: verification running (state after
power on reset)
High signal: verification finished
An error messaging at ERR is valid after the
second zero signal (enable required).
System Test
This mode enables the signal conditioning to be ad-
justed using comparated sine and cosine signals. To
Table 15: Digital Calibration Signals
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 19/39
INPUT CONFIGURATION
All input stages are configured as instrumentation am-
plifiers and thus directly suitable for differential input
signals. Referenced input signals can be processed;
input X2 can be configured as a reference input. Both
current and voltage signals can be processed, se-
lected using RIN12 and RIN0.
INMODE
Adr 0x03, bit 2
Code
0
Function
Differential input signals
Single-ended input signals *
* Input X2 is reference for all inputs.
1
Note
Figure 2: Signal Conditioning
Table 16: Input Signal Mode
RIN12
RIN0
Code
–000
–010
–100
–110
1—1
0—1
Adr 0x0E, bit 3:0
Current Signals
Adr 0x13, bit 3:0
In I Mode an input resistor Rin() becomes active at
each input pin, converting the current signal into a
voltage signal. Input resistance Rin() consists of a
pad wiring resistor and resistor Rui() which is linked
to the adjustable bias voltage source VREFin(). BIA-
SEX must be set to ’00’. The table besides shows the
possible selections, with Rin() giving the typical result-
ing input resistance (see Electrical Characteristics for
tolerances). The input resistor should be set in such
a way that intermediate potentials VDC1 and VDC2 lie
between 125 mV and 250 mV (verifiable in mode Cali-
bration 2).
Nominal Rin() Internal Rui()
I/V Mode
1.7 kΩ
2.5 kΩ
3.5 kΩ
4.9 kΩ
20 kΩ
1.6 kΩ
2.3 kΩ
3.2 kΩ
4.6 kΩ
5 kΩ
current input
current input
current input
current input
voltage input
voltage input
high
impedance
1 MΩ
Table 17: I/V Mode and Input Resistance
BIAS12
BIAS0
Code
0
Adr 0x0E, bit 6
Adr 0x13, bit 6
VREFin()
2.5 V
Voltage Signals
Type of sensor
In V mode an optional voltage divider can be selected
which reduces unacceptably large input amplitudes to
ca. 25 %. The circuitry is equivalent to the resistor
chain in I mode; the pad wiring resistor is considerably
larger here, however. For sensors whose offset cali-
bration is to be proportional to an external DC voltage
source the reference source can be selected using BI-
ASEX; for all other sensors BIASEX should be set to
’00’.
Lowside sink current (I Mode)
Highside current source (I Mode)
1
1.5 V
Note
Not valid with BIASEX=11.
Table 18: Reference Voltage
BIASEX
Code
00*
Adr 0x0D, bit 7:6
VREFin()
Signal at X2
1.5 / 2.5 V
(internal)
Neg. Zero Signal (Index -), input
10
11
1.5 / 2.5 V
(internal)
Ref. Voltage VREFin12, output
Voltage at X2 supplies VREFin
external
Table 19: Input Reference Selection
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 20/39
SIGNAL PATH MULTIPLEXING
MUX_OUT
MUX_IN
Calibration
X1
X2
X3
X4
X5
X6
PCH0i
PCH0o
NCH0o
INVZ
PZO
NZO
+
+
0
1
ZIN
NCH0i
-
-
VREFin0
MUXIN(0)
PCH2i
PCH2o
NCH2o
0
1
PC_out
NC_out
+
NCH2i
MUXIN(1)
-
0
1
PCH1i
PCH1o
NCH1o
PS_out
NS_out
+
MUXIN(1)
NCH1i
-
0
1
VDC1
VDC2
VDC1
VDC2
INMODE
VREFin12
Figure 3: Principle Of Multiplexer Function
MUXIN
Code
00
Adr 0x03, bit 1:0
The signals for index channel CH0 are connected up to
pins X1 and X2. Pins X3 to X6 are allocated to internal
channels CH1 and CH2 via MUXIN. INMODE can be
activated for referenced input signals; this then selects
X2 as the reference signal input. For output purposes
INVZ allows the index signal phase to be inverted for
channel CH0.
PCH1i
NCH1i
PCH2i
X3
NCH2i
X4
X2
X2
01
not permitted
not permitted
X4
10
11
X2
X5
X2
Table 21: Input Multiplexer for INMODE = 1
MUXIN
Code
00
Adr 0x03, bit 1:0
PCH1i
NCH1i
PCH2i
X3
NCH2i
X5
X4
X6
INVZ
Code
0
Adr 0x03, bit 3
01
not permitted
PZO
NZO
10
X4
X4
X5
X3
X3
X5
X6
X6
PCH0o
NCH0o
NCH0o
PCH0o
11
1
Table 20: Input Multiplexer for INMODE = 0
Table 22: Index Signal Inversion
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 21/39
SIGNAL CONDITIONING CH1, CH2
GR12
Code
0x0
Adr 0x04, bit 2:0
The analog voltage signals necessary for the calibra-
tion of the sine signals can be measured in operation
mode Calibration 2. Alternatively, characteristic digital
test signals are also available for offset, amplitude and
phase errors in operating mode System Test.
Range RIN12=0x9
Range RIN12=0x9
0.5
1.0
1.3
1.7
2.2
2.6
3.3
4.0
2.0
0x1
4.1
0x2
5.3
0x3
6.7
0x4
8.7
Gain Settings
The gain is set in four steps:
0x5
10.5
13.2
16.0
0x6
0x7
1. The sensor supply controller is shut down and the
constant current source for the ACO output set to a
suitable output current (register ADJ; current value
close to the later operating point).
Table 23: Gain Range CH1, CH2
GF2
Code
0x00
0x01
...
Adr 0x04, bit 7:3
Factor
2. The coarse gain is selected so that differential signal
amplitudes of ca. 1 Vpp are produced internally (signal
Px versus Nx, see Figure).
1.00
1.06
6.25GF2
31
3. Using fine gain factor GF2 the CH2 signal amplitude
is then adjusted to 1 Vpp.
0x1F
6.25
Table 24: Fine Gain Factor CH2
4. The CH1 signal amplitude can then be adjusted to
the CH2 signal amplitude via fine gain factor GF1. This
results in a total gain of GR12 * GFi for differential input
signals.
GF1
Code
0x00
0x01
...
Adr 0x06, bit 2:0, Adr 0x05, bit 7:4
Factor
1.0
1.015
GF1
124
6.25
0x7F
6.53
Table 25: Fine Gain Factor CH1
Px
VPNx
R0
VPx
Nx
VNx
GND
Figure 4: Definition of 1 Vpp signal. Termination R0
must be high-ohmic during all Test and
Calibration modes.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 22/39
Offset Calibration CH1, CH2
The offset calibration range for CH1 and CH2 is de-
In order to calibrate the offset the reference source pendent on the selected VOS12 source and is set us-
must first be selected using VOS12. Two fixed voltages ing OR1 and OR2. Both sine and cosine signals are
and two dependent sources are available for this pur- then calibrated using factors OF1 and OF2. The cal-
pose. The fixed voltage sources should be selected for ibration target is reached when the DC fraction of the
external sensors which provide stable, self-regulating differential signals PCHi versus NCHi is zero.
signals.
OR1
OR2
Code
0x0
Adr 0x09, bit 0; Adr 0x08, bit 7
So that photosensors can be operated in optical en-
coders iC-MQ tracks changes in offset voltages via
the signal-dependent source VDC when used in con-
junction with the controlled sensor current source for
LED supply (pin ACO). The VDC potential automati-
cally tracks higher DC photocurrents. To this end inter-
mediate potentials VDC1 and VDC2 must be adjusted
to a minimal AC ripple using the selectable k factor
(this calibration must be repeated when the gain set-
ting is altered). The ideal DC voltage level of 0.125 V
to 0.25 V is selected via input resistor Rui().
Adr 0x0A, bit 5:4
Range
x1
0x1
x2
0x2
x6
0x3
x12
Table 28: Offset Range CH1, CH2
OF1
OF2
Code
0x00
0x01
...
Adr 0xA, bit 3:0; Adr 0x9, bit 7:4
Adr 0xC, bit 0; Adr 0xB, bit 7:1
Factor
Code
0x80
0x81
...
Factor
The feedback of pin voltage V(ACO) fulfills the same
task as source VDC when MR bridge sensors are sup-
plied by the controlled sensor current source. In this
instance the VDC sources do not need adjusting.
0
0
0.0079
−0.0079
−0.0079 · OFi
−1
0.0079 · OFi
1
0x7F
0xFF
VOS12
Code
0x0
Adr 0x0E, bit 5:4
Table 29: Offset Factors CH1, CH2
Source
0.05 · V(ACO)
0.5 V
0x1
Phase Correction CH1 vs. CH2
0x2
0.25 V
The phase shift between CH1 and CH2 can be ad-
justed using parameter PH12. Following phase cal-
ibration other calibration parameters may have to be
adjusted again (those as amplitude compensation, in-
termediate potentials and offset voltages).
0x3
VDC (VDC1 for CH1, VDC2 for CH2)
Table 26: Offset Reference Source CH1, CH2
VDC1
Adr 0x07, bit 4:0; Adr 0x06, bit 7
Adr 0x08, bit 6:1
VDC2
Code
0x00
0x01
...
PH12
Code
0x00
0x01
...
Adr 0xD, bit 2:0; Adr 0xC, bit 7:5
VDC = k · VPi + (1 − k) · VNi
k = 0.33
Correction angle
+0
Code
0x20
0x21
...
Correction angle
−0
k = 0.335
+0.65
−0.65
k = 0.33 + VDCi · 0.0052
k = 0.66
+0.65 · PH12
+20.2
−0.65 · PH12
−20.2
0x3F
0x1F
0x3F
Table 27: Intermediate Voltages CH1, CH2
Table 30: Phase Correction CH1 vs. CH2
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 23/39
Signal Conditioning Examples
1. Photodiode array connected to current inputs, LED supply with constant current source
Step
1.
Operating Mode
Calibration and Signal
Presets
VOS12= 0x3, GF1= 0x40, VDC1= 0x20, OF1= 0x0, GF2= 0x10, VDC2= 0x20, OF2= 0x0
Example: LED current approx. 6.25 mA
ADJ(8)= 1 (constant current source), ADJ(6:5)= 11 (range 50 mA), ADJ(4:0)= 0x04 (value 12.5)
2.
Calibration 2
Calibration of Channel 1:
Parameter GR12: Adjust diff. signal at PA vs. NA to approx. 1 Vpp amplitude
Parameter GF1: Adjust diff. signal at PA vs. NA to exactly 1 Vpp amplitude
Parameter VDC1: Minimization of VDC1 AC fraction at output PZ (ripple < 10 mVpeak)
Parameter OR1, OF1: Calibration of DC fraction to zero for diff. signal PA vs. NA (< 5 mVdc)
3.
4.
Calibration 2
System Test
Calibration of Channel 2:
Parameter GF2: Adjust diff. signal at PB vs. NB to exactly 1 Vpp amplitude
Parameter VDC2: Minimization of VDC2 AC fraction at ouput NZ (ripple < 10 mVpeak)
Parameter OR2, OF2: Calibration of DC fraction to zero for diff. signal PB vs. NB (< 5 mVdc)
1. Iteration, Calibration of Channel 1 vs. Channel 2:
Parameter OF1: Adjust duty ratio of A4 at PA to 50 %
Parameter OF2: Adjust duty ratio of B4 at PB to 50 %
Parameter PH12: Adjust duty ratio of A8 at NA to 50 %
Parameter GF1: Adjust duty ratio of B8 at NB to 50 %
5.
6.
Calibration 2
System Test
Repeated Adjustment of Intermediate Voltages, VDC1 and VDC2:
Parameter VDC1: Minimization of VDC1 AC fraction at ouput PZ
Parameter VDC2: Minimization of VDC2 AC fraction at ouput NZ
2. Iteration, Calibration of Channel 1 vs. Channel 2:
Parameter OF1: Adjust duty ratio of A4 at PA to 50 %
Parameter OF2: Adjust duty ratio of B4 at PB to 50 %
Parameter PH12: Adjust duty ratio of A8 at NA to 50 %
Parameter GF1: Adjust duty ratio of B8 at NB to 50 %
Table 31: Conditioning example 1
2. Encoder supplying 100 mVpp to voltage inputs
Step
1.
Operating Mode
Calibration and Signal
Presets
VOS12= 0x1, GF1= 0x40, OF1= 0x0, GF2= 0x10, OF2= 0x0
2.
Calibration 2
Calibration of Channel 1:
Parameter GR12: Adjust diff. signal at PA vs. NA to approx. 1 Vpp amplitude
Parameter GF1: Adjust diff. signal at PA vs. NA to exactly 1 Vpp amplitude
Parameter OR1, OF1: Calibration of DC fraction to zero for diff. signal PA vs. NA (< 5 mVdc)
3.
4.
Calibration 2
System Test
Calibration of Channel 2:
Parameter GF2: Adjust diff. signal at PB vs. NB to exactly 1 Vpp amplitude
Parameter OR2, OF2: Calibration of DC fraction to zero for diff. signal PB vs. NB (< 5 mVdc)
Calibration of Channel 1 vs. Channel 2:
Parameter OF1: Adjust duty ratio of A4 at PA to 50 %
Parameter OF2: Adjust duty ratio of B4 at PB to 50 %
Parameter PH12: Adjust duty ratio of A8 at NA to 50 %
Parameter GF1: Adjust duty ratio of B8 at NB to 50 %
Table 32: Conditioning example 2
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 24/39
SIGNAL CONDITIONING CH0
The voltage signals needed to calibrate the zero chan- Offset Calibration CH0
nel are available in mode Calibration 1. The relative To calibrate the offset the reference source must first
phase position of the ungated zero signal Zin com- be selected using VOS0 (see Offset Calibration CH1
pared to A and B can be determined in mode System and CH2 for further information). For the CH0 path the
Test.
dependent source VDC is identical to source VDC1.
Gain Settings CH0
VOS0
Code
0x0
Adr 0x13, bit 5:4
Source
Parallel to the conditioning process for the CH1 and
CH2 signals the CH0 gain is also set in the following
steps:
0.05 · V(ACO)
0.5 V
0x1
0x2
0.25 V
1. The sensor supply controller is shut down and the
constant current source for the ACO output set to the
same output current as in the calibration of CH1 and
CH2 (register ADJ; current value close to the later op-
erating point).
0x3
VDC (i.e. VDC1)
Table 35: Offset Reference Source CH0
OR0
Code
0x0
Adr 0x12, bit 1:0
Range
x1
2. The coarse gain is selected so that a differential sig-
nal amplitude of ca. 1 Vpp is produced internally (sig-
nal PCHi versus NCHi).
0x1
x2
0x2
x6
0x3
x12
3. GF0 then permits fine gain adjustment to 1 Vpp. The
total gain is accrued from GR0 x GF0.
Table 36: Offset Range CH0
GR0
Code
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
Adr 0x11, bit 2:0
OF0
Code
0x00
0x01
...
Adr 0x12, bit 7:2
Range RIN0 = 0x9
Range RIN0 = 0x9
Factor
Code
0x20
0x21
...
Factor
0.5
1.0
1.3
1.7
2.2
2.6
3.3
4.0
2.0
0
0
4.1
0.0322
-0.0322
-0.0322 · OF0
-1
5.3
0.0322 · OF0
1
6.7
0x1F
0x3F
8.7
10.5
13.2
16.0
Table 37: Offset Factor CH0
Table 33: Gain Range CH0
GF0
Code
0x00
0x01
...
Adr 0x11, bit 7:3
Factor
1.00
1.06
6.25GF0
31
0x1F
6.25
Table 34: Fine Gain Factor CH0
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 25/39
SIGNAL LEVEL CONTROL and SIGNAL MONITORING
ADJ (4:0)
Code
Adr 0x10, bit 3:0; Adr 0x0F, bit 7
Square control ADJ(8:7) = 00
Via the controlled sensor current source (pin ACO) iC-
MQ can keep the input signals for the internal sine-
to-digital converter constant regardless of temperature
and aging effects by tracking the sensor supply.
0x00
Vpp() ca. 300 mV (60 %)
Vpp() ca. 305 mV (61 %)
0x01
77
...
Vpp() ≈ 300 mV 77−(1.25∗Code)
Both the controller operating range and input signal
amplitude for the controller are monitored and can
be enabled for error messaging. A constant current
source can be selected for the ACO output when set-
ting the signal conditioning; the current range for the
highside current source is adjusted using ADJ(6:5).
0x19
...
Vpp() ca. 500 mV (98 %)
...
0x1F
Vpp() ca. 600 mV (120 %)
Table 40: Internal Sin/Cos Signal Amplitude For
Square Control
In operation with the active square control mode
ADJ(4:0) sets the internal signal amplitudes according
to the relation (PCH1-NCH1)² + (PCH2-NCH2)²; these
should be set to 0.25 Vpk.
ADJ (4:0)
Code
Adr 0x10, bit 3:0; Adr 0x0F, bit 7
Sum control ADJ(8:7) = 01
VDC1 + VDC2 ca. 245 mV
VDC1 + VDC2 ca. 249 mV
0x00
0x01
77
...
VDC1 + VDC2 ≈ 245mV 77−(1.25∗Code)
Figure 5: Internal signal level monitoring and test
signals in Calibration 2 mode (example
for ADJ(8:0) = 0x19; see Elec. Char.
Nos. 605 and 606 regarding Vt()min and
Vt()max).
0x1F
VDC1 + VDC2 ca. 490 mV
Table 41: DC Setpoint For Sum Control
ADJ (4:0)
Adr 0x10, bit 3:0; Adr 0x0F, bit 7
Constant current source ADJ(8:7) = 10
I(ACO) ca. 3.125% Isc(ACO)
Code
0x00
0x01
ADJ (8:7)
Code
00
Adr 0x10, bit 7:6
Function
I(ACO) ca. 6.25% Isc(ACO)
Sine/cosine square control
Sum control
01
...
I(ACO) ≈ 3.125% ∗ (Code + 1) ∗ Isc(ACO)
10
Constant current source
Not permitted (device test only)
11
0x1F
I(ACO) ca. 100% Isc(ACO)
Notes
See Elec. Char. No. 602 for Isc(ACO)
Table 38: Controller Operating Modes
Table 42: I(ACO) With Constant Current Source
ADJ (6:5)
Adr 0x10, bit 5:4
Function
Code
00
5 mA - Range
10 mA - Range
25 mA - Range
50 mA - Range
01
10
11
Table 39: ACO Output Current Range (applies for con-
trol modes and constant current source)
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 26/39
SINE-TO-DIGITAL CONVERSION
SELRES
Adr 0x1C, bit 6:0; Adr 0x1B, bit 7:0
iC-MQ’s converter resolution can be set using SEL-
RES. For a resolution of 4, four angle steps per in-
put signal period are generated so that the switching
frequency at the A and B output matches the sine fre-
quency at the input.
Value
STEP
IPF
fin()max
Angle Steps
Per Period
Interpolation
Factor
Permissible Input
Frequency
(MTD=0x8)
0x00E0
0x01B0
0x02A0
0x0398
0x0414
0x0590
0x078C
0x090A
0x0B88
0x0F86
0x1305
0x1784
0x1804
0x1F83
0x2F82
0x3102
0x5F81
0x6301
4
1
500 kHz
500 kHz
200 kHz
200 kHz
200 kHz
166 kHz
125 kHz
100 kHz
83 kHz
62.5 kHz
50 kHz
40 kHz
40 kHz
30 kHz
20 kHz
20 kHz
10 kHz
10 kHz
8
2
The programmable converter hysteresis is determined
by SELHYS. It is set in multiples of the increment size
and may have a maximum of 45° of the input signal
period.
12
3
16
4
20
5
24
6
32
8
SELHYS
Code
0x0
Adr 0x1D, bit 3:0
40
10
12
16
20
24
25
32
48
50
96
100
Function
48
Nearly no hysteresis
64
0x1
1 increment (≈ 0.9°)
80
0x2
2 increments (≈ 1.8°)
96
0x3-0xD
0xE
3-13 increments (≈ 2.7°-11.7°)
SELRES(6:1) increments (0.5 LSB)
SELRES(6:0) increments
*) Not permissible with SELRES = 0x00E0
100
128
192
200
384
400
0xF*
Notes
Table 44: Converter Hysteresis
Table 43: Converter Resolution
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 27/39
OUTPUT SETTINGS AND ZERO SIGNAL
The set interpolation factor IPF determines the num- Zero Signal Generation
ber of A/B signal cycles generated internally which are The generation of the zero signal is dependant on the
counted via register POS to enable the positioning of internal enable signal ZIn which is produced by com-
the zero pulse. At a sine/cosine phase angle of zero paring the processed X1 and X2 input signals. The
degree the A/B cycle count starts at POS = 0, and the offset calibration of CH0 influences the width of the en-
highest cycle count is reached when POSmax = IPF-1. able signal so that the correct position of ZIn should be
The internal A/B signal cycle adheres to the following checked before the zero signal logic is configured. In
pattern:
Mode ABZ this is possible at the error signal output
(pin ERR; required settings are EMASKA = 0x010 and
EMTD = 0x0).
A 1 1 0 0
B 1 0 0 1
Table 45: Internal A/B Signal Cycle
Inversions and reversals can be selected for the output
of the A/B/Z signals and any logic combination for the
output of the zero signal. The output logic pairs param-
eters CFGABZ in accordance with the table below:
CFGABZ
Adr 0x19, bit 7:0
Figure 7: Signal path from ZIn to PZ/NZ
Bit
7
Function and Description
Output inversion for channel A: PA<>NA
PA = P1i xor CFGABZ(7)
The positioning of the zero signal by CFGZPOS is rel-
ative to the internal A/B cycle count POS. A cycle must
be selected across which enable signal ZIn is centered
as far as is possible. For cycle counts which cannot be
achieved due to a smaller interpolation factor no zero
signal is generated.
6
5
4
Output inversion for channel B: PB<>NB
PB = P2i xor CFGABZ(6)
Output inversion for index channel: PZ<>NZ
PZ = P0i xor CFGABZ(5)
Exchange of A/B signal assignation
0: P1i = A, P2i = B
1: P1i = B, P2i = A
CFGZPOS Adr 0x1A, bit 7:0
Zero Signal Logic CFGABZ(3:0)
Enable for A = 1, B = 1
Enable for A = 1, B = 0
Enable for A = 0, B = 0
Enable for A = 0, B = 1
Bit
7
Description
3
2
1
0
Mask Enable
(zero signal position determined by POS)
(6:0)
POS = A/B cycle count nl (releases zero signal
output)
Table 46: Output Logic
Table 47: Zero Signal Positioning
ENZFF
Adr 0x02, bit 4
Bit
0
Description
Zero signal output with state change of P0i
Zero signal output synchronized with A/B signal
1
Table 48: Zero Signal Synchronization
Figure 6: Signal Path from A and B to PA/NA and
PB/NB
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 28/39
Description Of CFGABZ Setup
Figure 9: Function of CFGABZ(4)
Figure 10: Function of CFGABZ(7)
Figure 8: Function of zero signal logic CF-
GABZ(3:0) (Example for CFGZPOS(7)=1,
CFGZPOS(6:0)=0x6)
Setup Example 1
Incremental ABZ output with a zero signal of 180° syn-
chronous with the A signal at PA:
CFGABZ = "0000 1100"
Setup Example 2
Incremental ABZ output with a zero signal of 270°
which can be synchronized externally with a 90° zero
pulse for PA = 1 und PB = 1:
CFGABZ = "1100 0111"
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 29/39
SIK
Code
00
Adr 0x1E, bit 5:4
Function
Output Driver Configuration
The output drivers can be used as push-pull, lowside
or highside drivers; the mode of operation is deter-
mined by TRIHL(1:0).
typ. 2 mA, linking logic or driver ICs
typ. 8 mA
01
10
typ. 40 mA
11
typ. 100 mA, recommended for RS422
See Elec. Char. Nos. 503/504
In order to avoid steep edges when transmitting via
short wires the slew rate can be set using SSR to suit
the length of the cable. This can result in a limiting
of the maximum permissible output frequency if at the
same time the RS422 specification is to be adhered
to (for example, to 300 kHz at a slew rate of 300 ns;
the tolerances in Electrical Characteristics, numbers
506/507, must be observed).
Note
Table 51: Output Short-Circuit Current
Minimum Phase Distance
The minimum phase distance for A/B/Z and
CPD/CPU/CP output signals can be preselected using
MTD(3:0). This setting limits the maximum possible
output frequency for safe transmission to counters
which cannot debounce spikes or only permit a low
input frequency.
The driver output short-circuit current can be set by
SIK and can be minimized when connecting to logic or
to an external 24 V line driver. If the outputs are used
as RS422-compatible 5 V drivers, it is recommended
that SIK = 11 to keep the power dissipation of iC-MQ
low.
When preselecting the minimum edge distance the
configuration of the RS422 output drivers (with regard
to the driver current and slew rate) and the length of
cable used must be taken into account.
TRIHL
Code
00
Adr 0x1E, bit 1:0
Function
Push-pull operation
MTD
Code
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
Note
Adr 0x1D, bit 7:4
Mode ABZ: tMTD
220 ns
01
Highside driver mode (P channel open drain)
Lowside driver mode (N channel open drain)
Not permitted
Mode 191/193: tclk()lo
110 ns
205 ns
300 ns
400 ns
500 ns
600 ns
700 ns
800 ns
50 ns
10
11
410 ns
600 ns
Table 49: Output Drive Mode
800 ns
1.0 µs
SSR
Code
00
Adr 0x1E, bit 3:2
1.2 µs
Function
1.4 µs
Nominal value 12 ns
Nominal value 25 ns
Nominal value 80 ns
Nominal value 220 ns
See Elec. Char. Nos. 506/507
1.6 µs
01
220 ns
10
410 ns
50 ns
11
600 ns
50 ns
Note
800 ns
50 ns
1.0 µs
50 ns
Table 50: Output Slew Rate
1.2 µs
50 ns
1.4 µs
50 ns
1.6 µs
50 ns
All timing specifications are nominal values, see
Elec. Char. No. 515 for tolerances.
Table 52: Minimum Phase Distance
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 30/39
ERROR MONITORING AND ALARM OUTPUT
EMASKA
Adr 0x15, bit 1:0; Adr 0x14, bit 7:0
Error event
iC-MQ monitors the input signals, the internal interpo-
lator and the sensor supply controller via which the in-
put signal levels are stabilized. If the sensor supply
tracking unit reaches its control limits this can be inter-
preted as an end-of-life message, for example.
Bit
9
Line count error (wrong count of sine periods
between two zero pulses)
8
Temporal tracking error (out-of-sync: position output
differs from actual angle, e.g. after cycling power)
7
6
Loss of tracking (excessive input frequency)
Three separate error masks stipulate whether error
events are signaled as an alarm via the current-limited
open drain I/O pin ERR (mask EMASKA), whether they
cause the RS422 line drivers to shutdown or not (mask
EMASKO) or whether they are stored in the EEPROM
(mask EMASKE).
Configuration error*
(SDA or SCL pin error, no acknowledge signal from
EEPROM or invalid check sum)
5
4
Excessive temperature warning
Ungated index enable signal ZIn
(comparated X1/X2 inputs for CFGABZ and
CFGZPOS adjustment)
3
2
1
0
Control error 2: range at max. limit
The display logic (via EPH) and the minimum alarm in-
dication time (via EMTD) can be set for I/O pin ERR; an
internal pull-up current source can be switched in via
EPU. ERR pin also has an input function for switching
iC-MQ to test mode (see page 33) and for the accep-
tance of a system error message in normal operation
(only for EPH = 0).
Control error 1: range at min. limit
Signal error 2: clipping due to excessive input level
Signal error 1: loss of signal (poor input level or s/c
phase out of range)
Code
1
Function
Enable: event will be displayed
Disable: event will not be displayed
0
Notes
*) The line drivers remain high impedance (tristate)
when cycling power.
EPH
Code
0
Adr 0x15, bit 2
Pin Logic
Low on error (otherwise Z)
Z on error (otherwise low)
Table 57: Error Event Mask for Alarm Output
1
EMASKO
Adr 0x17, bit 1:0; Adr 0x16, bit 7:0
Error event
Table 53: Alarm Input/Output Logic
Bit
9
Line count error (wrong count of sine periods
between two zero pulses)
EMTD
Code
0x0
Adr 0x15, bit 5:3
Indication Time
0 ms
Code
0x4
0x5
0x6
0x7
Indication Time
50 ms
8
Temporal tracking error (out-of-sync: position output
differs from actual angle, e.g. after cycling power)
7
6
Loss of tracking (excessive input frequency)
0x1
12.5 ms
25 ms
62.5 ms
75 ms
Configuration error* (ROM bit with fixed value = 1)
SDA or SCL pin error, no acknowledge signal from
EEPROM or invalid check sum
0x2
0x3
37.5 ms
87.5 ms
5
4
Excessive temperature warning
Table 54: Minimum Alarm Indication Time
System error: I/O pin ERR pulled to low by an
external error signal (only permitted with EPH = 0)
EPU
Code
0
Adr 0x17, bit 2
3
2
1
0
Control error 2: range at max. limit
Function
Control error 1: range at min. limit
No internal pull-up active
Internal 300 µA pull-up current source active
Signal error 2: clipping due to excessive input level
1
Signal error 1: loss of signal (poor input level or s/c
phase out of range)
Code
1
Function
Table 55: Pull-Up Enable for Alarm Output ERR
Enable: event triggers tri-state
Disable: event does not cause tri-state
0
PDMODE
Adr 0x18, bit 6
Notes
*) The line drivers remain high impedance (tristate)
when cycling power.
Code
Function
0
1
Line driver active when no error persists
Line driver active only after cycling power
Table 58: Error Event Mask for Driver Shutdown
Table 56: Driver Activation
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 31/39
Error Protocol
Line Count Error
Out of the errors enabled by EMASKE both the first The line count error feature is particularly interest-
(under ERR1) and last error (under ERR2) which oc- ing for encoder systems. The disc is checked anew
cur after the iC-MQ is turned on are stored in the EEP- with each zero pulse, with the number of sine cycles
ROM.
counted until the next zero pulse occurs. If the direc-
tion of rotation is changed, the check is aborted.
The EEPROM also has a memory area in which all oc-
curring errors can be stored (ERR3). Only the fact that The line count is then stored under LINECNT minus 1,
an error has occurred can be recorded, with no infor- i.e. for a code disc with 256 lines LINECNT records
mation as to the time and count of appearance of that a value of 255. If the counted line number does not
error given. Error recording can be used to statistically match the number already stored in LINECNT, a line
evaluate the causes of system failure, for example.
count error is set. In mode System Test signal TP1
indicates when the line count check is first ended.
EMASKE
Adr 0x18, bit 5:0; Adr 0x17, bit 7:4
Error event
Bit
9
Temperature Monitoring
If the temperature warning threshold is exceeded an
excessive temperature message is generated which is
processed in the temperature monitor block (Tw corre-
sponds to T2).
Line count error (wrong count of sine periods
between two zero pulses)
8
7
6
5
4
—
Loss of tracking (excessive input frequency)
—
Excessive temperature warning
Exceeding the temperature warning threshold can be
signaled at pin ERR or used to shut down the line
drivers (via mask EMASKO). The temperature warn-
ing is deleted when the temperature drops below Tw
System error: I/O pin ERR reads low by an external
error signal (only permitted with EPH = 0)
3
2
1
0
Control error 2: range at max. limit
Control error 1: range at min. limit
-Thys
.
Signal error 2: clipping due to excessive input level
Signal error 1: loss of signal (poor input level or s/c
phase out of range)
If the temperature shutdown threshold Toff = Tw + ∆ T
is exceeded the line drivers are shut down independent
of EMASKO.
Code
Function
1
0
Enable: event will be latched
Disable: event will not be latched
Table 59: Error Event Mask for EEPROM Savings
ERR1
Adr 0x31, bit 1:0; Adr 0x30, bit 7:0
Adr 0x32, bit 3:0; Adr 0x31, bit 7:2
Adr 0x33, bit 5:0; Adr 0x32, bit 7:4
Error Event
ERR2
ERR3
Bit
6:0
Assignation according to EMASKE
Code
Function
0
1
No event
Registered error event
Table 60: Error Protocol
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 32/39
REVERSE POLARITY PROTECTION
iC-MQ is protected against a reversal of the supply The following pins are also reverse polarity protected:
voltage and has short-circuit-proof, error-tolerant line PA, NA, PB, NB, PZ, NZ, ERR, VDD, GND and ACO.
drivers. A defective device cable or one wrongly con-
nected is tolerated by iC-MQ. All circuitry components Conditions: This is based on the condition that GNDS
which draw the monitored supply voltage from VDDS only receives load currents from VDDS. The maxi-
and GNDS are also protected.
mum voltage difference between GNDS and another
pin should not exceed 6 V, the exception here being
pin ERR (see Test Mode page 33).
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 33/39
TEST MODE
EMODE
Adr 0x15, bit 7:6
iC-MQ switches to test mode when a voltage greater
than VTMon is applied to pin ERR (precondition:
EMODE(0) = 1). In response iC-MQ transmits its setup
settings as current-modulated data using error sig-
nal I/O pin ERR either directly from the RAM (for
EMODE2 = 1) or after re-reading the EEPROM (for
EMODE2 = 0). Should the voltage at the ERR pin fall
below VTMoff test mode is terminated and data trans-
mission aborted.
Code
Function during test
mode
Function following test
mode
00
01
Normal operation
Normal operation
Transmission of error
and OEM data*
Repeated read out of
EEPROM
10
11
Normal operation
Repeated read out of
EEPROM
Transmission of
EEPROM contents
(0x0-0x7F)
Repeated read out of
EEPROM
Notes
*) Selectable address ranges:
EMODE2 = 0: EEPROM addresses 0x24 to 0x7F
EMODE2 = 1: RAM addresses 0x3B to 0x43
The clock rate for the data output is determined by
ENFAST. Two clock rates can be selected: 780 ns for
ENFAST = 1 or 3.125 µs for ENFAST = 0 (see Electri-
cal Characteristics, B12, for clock frequency and toler-
ances).
Table 61: Test Mode
EMODE2
Adr 0x18, bit 7
Data is output in Manchester code via two clock pulses
per bit. To this end the lowside current source switches
between a Z state (OFF = 0 mA) and an L state (ON =
2 mA).
Code
Register selection
Address range for
EMODE = 01
0
1
Reading/sending
external configuration
data (DEVID is device
address)
EEPROM address
range 0x24-0x7F
The bit information lies in the direction of the current
source switch:
Sending internal
configuration data
(ENSL = 1)
RAM address range
0x3B-0x43
Zero bit: change of state Z → L (OFF to ON)
One bit: Change of state L → Z (ON to OFF)
Table 62: Register And Address Selection For Test
Mode
Transmission consists of a start bit (a one bit), 8 data
bits and a pause interval in Z state (the timing is iden-
tical with an EEPROM access via the I2C interface).
VP
U23-B
VP LM393
VP
7
8
6
5
VP
VP
C21
100nF
C22
100nF
-
U22-S
AD8029
VN
U23-S
LM393
GND
7
+
4
4
Example: byte value = 1000 1010
Transmission including the start bit: 1 1000 1010
In Manchester code: LZ LZZL ZLZL LZZL LZZL
JP4
R24
470
ERR
max. 5V
VDD
M22
IRLML6401
C24
VP
R26
100pF
100k
R23
2K
C26
100nF
R28
51k
U22-A
U23-A
LM393
R25
2k
2
D21
LL4148
Decoding of the data stream:
-
M21
2N7002
6
2
3
DATA_ON
AD8029
-
3
1
NDIS
DATA_OUT
+
8
+
R21
475k
8
4
R27
U21
LM285
VP
100k
5
ZZZZZZ LZ LZ ZL ZL ZL LZ ZL LZ ZL ZZZZZZ
Pause 1 1 0 0 0 1 0 1 0 Pause
C25
100nF
R22
365k
VDD
C23
100nF
dra_mq1d_error_schem
Figure 11: Example circuit for the decoding and
conversion of the current-modulated sig-
nals to logic levels.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 34/39
Quick programming in the
single master system
Quick programming in the
multimaster system
For the purpose of signal conditioning it is possible Fast programming of iC-MQ, byte for byte, is possible
to reprogram iC-MQ quickly. If test mode is quit and with a multimaster-competent programming device. To
EMODE = 00, iC-MQ reads the configuration data in this end the integrated I2C slave mode must be en-
again. In place of the standard EEPROM (DEVID abled by ENSL; iC-MQ then reacts to the device ID
0x50) an EEPROM with a different device address can 0x55.
be read in which can be stored under DEVID (address
0x00, bit 6:0).
If no EEPROM is connected, iC-MQ automatically
In operating modes Mode ABZ, System Test and Mode sets the I2C slave mode enable (after a maximum of
191/193 the content of the EEPROM is read in its en- 150 ms, see Electrical Characteristics, D11) and deac-
tirety. For other modes the address area is limited to tivates the digital section (ENSL = 1 and END = 0 are
0x0-0x31 so that the configuration time for either cali- set). Any number of bytes can be written at any one
bration or IC testing is shortened.
time; the received data is accepted directly into the
RAM register. The conditions given in the following
If the setup is switched to test mode during the readin table must be taken into consideration here. After pro-
procedure, readin is aborted and only repeated once gramming END = 1 must be set to restart sine-to-digital
test mode has been terminated.
conversion in the selected mode of operation.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 35/39
EXAMPLE APPLICATIONS
Figure 12 is a circuit diagram of an optical encoder with tive the magnetic encoder in Figure 13 uses magneto-
an incremental output of quadrature signals as RS422- resistive sensor bridges. An external overvoltage pro-
compatible differential signals which can be terminated tection circuit may be realized employing TVS diodes
by 100 Ω at the controller end. By way of an alterna- plus a PolyFuse in the VDD line, for instance.
iC-MQ
Disc
iC-LSHB
Figure 12: Example application with an optical encoder
iC-MQ
Figure 13: Example application with a magnetic encoder
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 36/39
When iC-MQ is used in 24 V systems, with supply volt- mask is set for output shutdown (EMASKO). In the
ages of 5 V to 30 V for example, it can be combined event of error the pull-down current sources ensure
with iC-DL which acts as a line driver with an integrated that a low signal is produced at the iC-DL inputs on
line adaptation feature (Figure 14).
all lines which the controller recognizes as an error. If
there is an overload at the outputs, via its temperature
A reduced driving capability of iC-MQ is sufficient protection unit iC-DL itself makes sure that the driver
(SIK = 00) to operate iC-DL so that the current required outputs are shutdown (tristate) - which the controller
is reduced at the 5 V end. If an LDO voltage regulator also classes as an error. In addition iC-MQ can trans-
is selected, the circuit is suitable for a supply range of mit the overload to the error memory as a system error
4.5 V to 30 V without any changes having to be made.
when information is returned to the bidirectional I/O pin
ERR (as shown).
The wiring of the iC-DL error message output (pin
NER) to the PLC is not necessary if the iC-MQ error
iC-MQ
iC-DL
Figure 14: Example application with a 24 V line driver
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 37/39
APPLICATION HINTS
In-circuit programming of the EEPROM
A phase error between the sine and cosine signals
Access to the EEPROM is unhindered when the iC- (a deviation in phase shift from the ideal 90°) has the
MQ supply voltage is kept below power down reset most marked influence on the absolute angle error at
threshold VDDoff. In this case an EEPROM which op- 0°, 90°, 180° and 270°. The greatest effect on the tran-
erates at a supply voltage of 2.5 V and above is re- sition distance is noted at 45°, 135°, 225° and 315°.
quired. If 3.3 V are necessary to power the EEPROM, iC-MQ’s phase correction feature permits a step size of
iC-MQ’s supply voltage can be raised at a maximum 0.64° so that incorrect compensation by 1 LSB would
to power on threshold VDDon; this must occur without increase the absolute angle error by ca. 0.64°. The
overshooting.
transition distance would then vary by +/- 1.1 %.
The supply voltage provided by pins VDDS and GNDS In a perfect signal conditioning procedure it can be as-
can be used to power the EEPROM; shutdown only sumed that the residual error constitutes half a com-
occurs with reverse polarity. Here, the load-dependent pensation step respectively. With this, in theory iC-
voltage drop at both switches must be taken into ac- MQ would achieve an absolute angle accuracy of ca.
count; see Vs(VDDS) and Vs(GNDS) in the Electrical 0.5°, with the transition distance varying by ca. +/-
Characteristics, C01 and C02.
1.5 %. The linearity error of the interpolator must also
be taken into consideration; this increases the absolute
angle error by ca. 0.12° and the variation in transition
Absolute angle accuracy and edge jitter
The precise setting of the signal conditioning unit for distance by 0.4 %. With ideal, almost static input sig-
correction of the analog input signals is crucial to the nals iC-MQ then obtains an absolute angle accuracy
result of interpolation; the absolute angle error ob- of 0.62° and a variation in transition distance of under
tained determines the minimum signal jitter. Here, the 2 %.
effect on the transition distance of the A/B output sig-
nals is not always the same but instead dependent on Information on the demo board
the absolute phase angle of the input signals. The fol- The default delivery status of demo board EVAL MQ1D
lowing gives an example for an interpolation factor of is such that it expects differential sine/cosine signals at
100, i.e. 400 edges per sine period.
inputs X3 to X6 with an amplitude of 125 mV, i.e.
The offset error in the cosine signal has the strongest
effect on the absolute angle error at 90° and 270°; at 0°
and 180° its influence on the transition distance is the
most marked. With a range setting of OR1 = OR2 = 00
and VOSSC = 01 the offset error can be compensated
for by an increment of 3.9 mV. If the offset has been
compensated for incorrectly by one step (1 LSB), the
absolute angle error would increase by ca. 0.45° and
V(X4) = 2.5 V + 0.125 Vsin(ϕt)
V(X3) = 2.5 V − 0.125 Vsin(ϕt)
V(X5) = 2.5 V + 0.125 Vsin(90 + ϕt)
V(X6) = 2.5 V − 0.125 Vsin(90 + ϕt)
the transition distance vary by approximately +/- 0.8 %. Outputs PA, NA, PB and NB generate a differential
Similar conditions apply to the sine signal, with the sole A/B signal with an angle resolution of 4 (an interpo-
difference that the maxima would be shifted by 90°.
lation factor of 1). When high sine input frequencies
are applied or the resolution is increased, the mini-
An error in amplitude has the strongest effect on the mum phase distance (MTD), short-circuit current limit
absolute angle error at 45°, 135°, 225° and 315°; the (SIK) and driver slew rate (SSR) must be adjusted to
biggest change in the transition distance can be ob- meet requirements. For example, a minimum phase
served at 0°, 90°, 180° and 270°. iC-MQ can compen- distance of MTD = 8 should be selected with a resolu-
sate for the amplitude ratio in steps of 1.5 % so that tion of 200 (an interpolation factor of 50) when input
incorrect compensation by 1 LSB would increase the frequencies of up to 20 kHz are to be applied.
absolute angle error by ca. 0.42°. The transition dis-
tance would then vary by +/- 1.5 %.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 38/39
iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the
relevant current specifications on our internet website www.ichaus.de/infoletter; this letter is generated automatically and shall be sent to registered users by
email.
Copying – even as an excerpt – is only permitted with iC-Haus’ approval in writing and precise reference to source.
iC-Haus does not warrant the accuracy, completeness or timeliness of the specification and does not assume liability for any errors or omissions in these
materials.
The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness
for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no
guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of
the product.
iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade
mark rights of a third party resulting from processing or handling of the product and/or any other use of the product.
As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical
applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of
use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued
annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in
Hanover (Hannover-Messe).
We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations
of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can
be put to.
iC-MQ PROGRAMMABLE 9-BIT
Sin/Cos INTERPOLATION IC WITH RS422 DRIVER
Rev D4, Page 39/39
ORDERING INFORMATION
Type
Package
Order Designation
iC-MQ
TSSOP20
iC-MQ TSSOP20
Evaluation Board iC-MQ
iC-MQ EVAL MQ1D
For technical support, information about prices and terms of delivery please contact:
iC-Haus GmbH
Tel.: +49 (61 35) 92 92-0
Am Kuemmerling 18
D-55294 Bodenheim
GERMANY
Fax: +49 (61 35) 92 92-192
Web: http://www.ichaus.com
E-Mail: sales@ichaus.com
Appointed local distributors: http://www.ichaus.com/sales_partners
相关型号：
©2020 ICPDF网 联系我们和版权申明