ICS84021 [ICSI]
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER; 为260MHz ，水晶- TO- LVCMOS / LVTTL频率合成器
| 型号： | ICS84021 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 260MHZ, CRYSTAL-TO-LVCMOS / LVTTL FREQUENCY SYNTHESIZER |
| 文件： | 总14页 (文件大小：253K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
• 2 LVCMOS/LVTTL outputs
The ICS84021 is a general purpose, Crystal-to-
ICS
LVCMOS/LVTTL High Frequency Synthesizer
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.The
ICS84021 has a selectable TEST_CLK or crys-
• Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
HiPerClockS™
• Output frequency range: 103.3MHz to 260MHz
• Crystal input frequency range: 14MHz to 40MHz
• VCO range: 620MHz to 780MHz
tal input.The VCO operates at a frequency range of 620MHz
to 780MHz. The VCO frequency is programmed in steps
equal to the value of the input reference or crystal frequency.
The VCO and output frequency can be programmed using
the serial or parallel interface to the configuration logic. The
low phase noise characteristics of the ICS84021 make it an
ideal clock source for Gigabit Ethernet, SONET, Fibre Chan-
nel 1 and 2, and Infiniband applications.
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 4.3ps (typical) (N ÷ 4, VDDO = 3.3V ꢀ5)
• RMS phase jitter at 1ꢀꢀ.ꢀ2MHz, using a 38.88MHz crystal
(12KHz to 20MHz): 2.88ps (typical)
Phase noise: 1ꢀꢀ.ꢀ2MHz
Offset
Noise Power
100Hz ................. -93.7 dBc/Hz
1KHz ............... -111.3 dBc/Hz
10KHz ............... -120.4 dBc/Hz
100KHz ............... -12ꢀ.1 dBc/Hz
• Full 3.3V or mixed 3.3V core/2.ꢀV or 1.8V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
OE0
OE1
VCO_SEL
XTAL_SEL
32 31 30 29 28 27 26 2ꢀ
Mꢀ
M6
M7
M8
N0
N1
nc
1
2
3
4
ꢀ
6
7
8
24
23
22
21
20
19
18
17
XTAL2
TEST_CLK
0
TEST_CLK
XTAL_SEL
VDDA
XTAL1
1
OSC
ICS84021
XTAL2
S_LOAD
S_DATA
S_CLOCK
MR
PLL
GND
PHASE DETECTOR
9
10 11 12 13 14 1ꢀ 16
÷3
÷4
÷ꢀ
÷6
0
1
MR
VCO
Q0
Q1
÷ M
32-Lead LQFP
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
7mm x 7mm x 1.4mm package body
CONFIGURATION
INTERFACE
LOGIC
TEST
Y Package
Top View
M0:M8
N0:N1
84021AY
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REV. A NOVEMBER 7, 2003
1
ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op- M divider and N output divider to a specific default state that will
eration using a 2ꢀMHz crystal. Valid PLL loop divider values automatically occur during power-up.The TEST output is LOW
for different crystal or input frequencies are defined in the when operating in the parallel input mode.The relationship be-
Input Frequency Characteristics, Table ꢀ, NOTE 1.
tween the VCO frequency, the crystal frequency and the M di-
vider is defined as follows: fVCO = fxtal x M
The ICS84021 features a fully integrated PLL and therefore
requires no external components for setting the loop band- The M value and the required values of M0 through M8 are
width. A fundamental crystal is used as the input to the on- shown in Table 3B, Programmable VCO Frequency Function
chip oscillator.The output of the oscillator is fed into the phase Table.Valid M values for which the PLL will achieve lock for a
detector. A 2ꢀMHz crystal provides a 2ꢀMHz phase detector 2ꢀMHz reference are defined as 2ꢀ ≤ M ≤ 31.The frequency
reference frequency. The VCO of the PLL operates over a out is defined as follows: FOUT = fVCO = fxtal x M
N
N
range of 620MHz to 780MHz. The output of the M divider is
also applied to the phase detector.
Serial operation occurs when nP_LOAD is HIGH and
S_LOAD is LOW. The shift register is loaded by sampling
The phase detector and the M divider force the VCO output the S_DATA bits with the rising edge of S_CLOCK. The con-
frequency to be M times the reference frequency by adjusting tents of the shift register are loaded into the M divider and N
the VCO control voltage. Note that for some values of M (either output divider when S_LOAD transitions from LOW-to-HIGH.
too high or too low), the PLL will not achieve lock.The output of The M divide and N output divide values are latched on the
the VCO is scaled by a divider prior to being sent to each of HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH,
the LVCMOS output buffers. The divider provides a ꢀ05 out- data at the S_DATA input is passed directly to the M divider
put duty cycle.
and N output divider on each rising edge of S_CLOCK. The
serial mode can be used to program the M and N bits and
The programmable features of the ICS84021 support two input test bits T1 and T0. The internal registers T0 and T1 deter-
modes to program the M divider and N output divider. The two mine the state of the TEST output as follows:
input operational modes are parallel and serial. Figure 1 shows
T1 T0
TEST Output
LOW
the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW.The data on inputs M0 through
M8 and N0 and N1 is passed directly to the M divider and
N output divider.On the LOW-to-HIGH transition of the nP_LOAD
input, the data is latched and the M divider remains loaded until
the next LOW transition on nP_LOAD or until a serial event oc-
curs. As a result, the M and N bits can be hardwired to set the
0
0
1
1
0
1
0
1
S_DATA, Shift Register Input
Output of M divider
CMOS Fout
SERIAL
L
OADING
S_CLOCK
T1
T0
*NULL
N1
N0
M8
M7
M6
Mꢀ
M4
M3
M2
M1
M0
S_DATA
S_LOAD
nP_LOAD
t
t
H
S
t
S
PARALLEL LOADING
M, N
M0:M8, N0:N1
nP_LOAD
t
t
H
Time
S
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
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REV. A NOVEMBER 7, 2003
2
ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
Mꢀ
Input
Input
M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines output divider value as defined in Table 3C,
Function Table. LVCMOS / LVTTL interface levels.
ꢀ, 6
N0, N1
Input
7
nc
Unused
Power
No connect.
8, 16
GND
Power supply ground.
Test output which is ACTIVE in the serial mode of operation. Output
driven LOW in parallel mode. LVCMOS / LVTTL interface levels.
9
TEST
VDD
Output
Power
10
Core supply pin.
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are in Tri-State. See Table 3E,
OE Function Table. LVCMOS / LVTTL interface levels.
11, 12
OE1, OE0
Input
Pullup
13
VDDO
Power
Output
Output supply pin.
14, 1ꢀ
Q0, Q1
Clock outputs. LVCMOS / LVTTL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the outputs to go low. When logic LOW, the
17
MR
Input
Pulldown internal dividers and the outputs are enabled. Assertion of MR
does not effect loaded M, N, and T values.
LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
S_CLOCK. LVCMOS / LVTTL interface levels.
18
19
S_CLOCK
S_DATA
Input
Input
Pulldown
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VDDA
Input
Pulldown
Power
Analog supply pin.
Selects between crystal or test inputs as the PLL reference source.
22
XTAL_SEL
Input
Pullup
Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW.
LVCMOS / LVTTL interface levels
23
TEST_CLK
Input
Input
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
24, 2ꢀ
XTAL2, XTAL1
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
26
nP_LOAD
Input
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
84021AY
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REV. A NOVEMBER 7, 2003
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ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
pF
KΩ
KΩ
VDD, VDDA, VDDO = 3.46ꢀV
VDD, VDDA = 3.46ꢀV, VDDO = 2.62ꢀV
VDD, VDDA = 3.46ꢀV, VDDO = 1.89V
1ꢀ
1ꢀ
20
ꢀ1
ꢀ1
Power Dissipation Capacitance
(per output)
CPD
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
1
8
M3
1
4
M2
0
2
M1
0
1
M0
1
VCO Frequency
(MHz)
M Divide
62ꢀ
•
2ꢀ
•
•
•
•
•
•
•
•
•
•
700
•
28
•
0
0
0
0
1
1
1
0
0
•
•
•
•
•
•
•
•
•
77ꢀ
31
0
0
0
0
1
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency
of 2ꢀMHz.
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REV. A NOVEMBER 7, 2003
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ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (PLL ENABLED)
Inputs
Output Frequency (MHz)
N Divider Value
N1
N0
0
Minimum
206.7
1ꢀꢀ
Maximum
260
0
0
1
1
3
4
ꢀ
6
1
19ꢀ
0
124
1ꢀ6
1
103.3
130
TABLE 3D. COMMONLY USED CONFIGURATION FUNCTION TABLE
Input
Output Frequency (MHz)
Crystal (MHz) M Divider Value N Divider Value
19.44
19.ꢀ312ꢀ
2ꢀ
32
32
2ꢀ
2ꢀ
2ꢀ
2ꢀ
2ꢀ
16
4
4
4
ꢀ
3
4
6
4
1ꢀꢀ.ꢀ2
1ꢀ6.2ꢀ
1ꢀ6.2ꢀ
12ꢀ
2ꢀ
2ꢀ.ꢀ0
2ꢀ.ꢀ0
2ꢀ.ꢀ0
38.88
212.ꢀ0
1ꢀ9.37ꢀ
106.2ꢀ
1ꢀꢀ.ꢀ2
TABLE 3E. OUTPUT ENABLE & CLOCK ENABLE FUNCTION TABLE
Control Inputs
Output
OE0
OE1
Q0
Q1
0
0
1
1
0
1
0
1
Hi-Z
Hi-Z
Hi-Z
Enabled
Hi-Z
Enabled
Enabled
Enabled
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REV. A NOVEMBER 7, 2003
ꢀ
ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
Inputs, VI
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied.Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
-0.ꢀV to VDD + 0.ꢀ V
-0.ꢀV to VDDO + 0.ꢀV
Outputs, VO
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, TSTG -6ꢀ°C to 1ꢀ0°C
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD=VDDA=3.3V ꢀ5, VDDO=3.3V ꢀ5, 2.ꢀV ꢀ5 OR 1.8V ꢀ5, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.13ꢀ
3.13ꢀ
3.13ꢀ
2.37ꢀ
1.71
Typical
3.3
Maximum Units
VDD
Core Supply Voltage
3.46ꢀ
3.46ꢀ
3.46ꢀ
2.62ꢀ
1.89
140
V
V
VDDA
Analog Supply Voltage
Output Supply Voltage
3.3
3.3
V
VDDO
2.ꢀ
V
1.8
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
IDDO
2ꢀ
ꢀ
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REV. A NOVEMBER 7, 2003
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ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD=VDDA=3.3V ꢀ5,
DDO=3.3V ꢀ5, 2.ꢀV ꢀ5 OR 1.8V ꢀ5, TA=0°C TO 70°C
V
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, OE0, OE1,
N0:N1, M0:M8
2
V
DD + 0.3
V
V
V
Input
VIH
High Voltage
TEST_CLK
2
VDD + 0.3
0.8
VCO_SEL, XTAL_SEL, MR,
S_LOAD, nP_LOAD, S_DATA,
S_CLOCK, OE0, OE1,
N0:N1, M0:M8
-0.3
-0.3
Input
VIL
Low Voltage
TEST_CLK
1.3
V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
Mꢀ, OE0, OE1,
VDD = VIN = 3.46ꢀV
VDD = VIN = 3.46ꢀV
1ꢀ0
µA
Input
IIH
High Current
ꢀ
µA
µA
XTAL_SEL, VCO_SEL
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
VDD = 3.46ꢀV,
VIN = 0V
-ꢀ
Input
IIL
Low Current
VDD = 3.46ꢀV,
VIN = 0V
Mꢀ, OE0, OE1,
XTAL_SEL, VCO_SEL
-1ꢀ0
µA
V
DDO = 3.3V ꢀ5
2.6
1.8
V
V
V
V
V
V
VOH
Output High Voltage; NOTE 1
VDDO = 2.ꢀV ꢀ5
VDDO = 1.8V ꢀ5
VDDO - 0.3
VDDO = 3.3V ꢀ5
0.ꢀ
0.ꢀ
0.4
VOL
Output Low Voltage; NOTE 1
VDDO = 2.ꢀV ꢀ5
VDDO = 1.8V ꢀ5
NOTE 1: Outputs terminated with ꢀ0Ω to VDDO/2. See Parameter Measurement Section, “Load Test Circuit Diagrams”.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V ꢀ5, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
14
14
40
40
ꢀ0
MHz
MHz
MHz
fIN
Input Frequency XTAL1, XTAL2; NOTE 1
S_CLOCK
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within
the 620MHz to 780MHz range. Using the minimum input frequency of 14MHz, valid values of M are 4ꢀ ≤ M ≤ ꢀꢀ.
Using the maximum frequency of 40MHz, valid values of M are 16 ≤ M ≤ 19.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
14
40
ꢀ0
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance (CO)
pF
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REV. A NOVEMBER 7, 2003
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ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 7A. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V ꢀ5, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
103.3
260
10
7
MHz
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
5
N ÷ 3
N ÷ 4
N ÷ ꢀ
N ÷ 6
7.ꢀ
4.3
tjit(per)
Period Jitter, RMS; NOTE 1
4.1
6
12.9
16
100
800
tsk(o)
tR / tF
Output Skew; NOTE 2, 3
Output Rise/Fall Time
205 to 805
300
ꢀ
M, N to nP_LOAD
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
ꢀ
ꢀ
M, N to nP_LOAD
ꢀ
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
ꢀ
ꢀ
odc
Output Duty Cycle
PLL Lock Time
4ꢀ
ꢀꢀ
1
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 6ꢀ.
TABLE 7B. AC CHARACTERISTICS, VDD = VDDA = 3.3V ꢀ5, VDDO = 2.ꢀV ꢀ5, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
103.3
260
8
MHz
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
5
N ÷ 3
N ÷ 4
N ÷ ꢀ
N ÷ 6
6.4
4.3
4.2
9
8
tjit(per)
Period Jitter, RMS; NOTE 1
7
12
90
800
tsk(o)
tR / tF
Output Skew; NOTE 2, 3
Output Rise/Fall Time
205 to 805
300
ꢀ
M, N to nP_LOAD
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
ꢀ
ꢀ
M, N to nP_LOAD
ꢀ
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
ꢀ
ꢀ
odc
Output Duty Cycle
PLL Lock Time
4ꢀ
ꢀꢀ
1
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 6ꢀ.
84021AY
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REV. A NOVEMBER 7, 2003
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ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 7C. AC CHARACTERISTICS, VDD = VDDA = 3.3V ꢀ5, VDDO = 1.8V ꢀ5, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
103.3
260
8
MHz
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
5
N ÷ 3
N ÷ 4
N ÷ ꢀ
N ÷ 6
6.8
4.ꢀ
4.2
8.ꢀ
8
tjit(per)
Period Jitter, RMS; NOTE 1
6
10
120
800
tsk(o)
tR / tF
Output Skew; NOTE 2, 3
Output Rise/Fall Time
205 to 805
300
ꢀ
M, N to nP_LOAD
tS
Setup Time S_DATA to S_CLOCK
S_CLOCK to S_LOAD
ꢀ
ꢀ
M, N to nP_LOAD
ꢀ
tH
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
ꢀ
ꢀ
odc
Output Duty Cycle
PLL Lock Time
42
ꢀ8
1
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 6ꢀ.
84021AY
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REV. A NOVEMBER 7, 2003
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ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
VDD, VDDA, VDDO = 1.6ꢀV ꢀ5
1.2ꢀV ꢀ5
2.0ꢀV ꢀ5
SCOPE
SCOPE
,
VDD
VDDA
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND= -1.6ꢀV ꢀ5
GND= -1.2ꢀV ꢀ5
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
0.9V ꢀ5
2.4V ꢀ5
VOH
VREF
SCOPE
,
VDD
VDDA
VOL
VDDO
1σ contains 68.265 of all measurements
2σ contains 9ꢀ.45 of all measurements
3σ contains 99.735 of all measurements
4σ contains 99.993665 of all measurements
6σ contains (100-1.973x10-7)5 of all measurements
Qx
LVCMOS
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
GND= -0.9V ꢀ5
PERIOD JITTER
3.3V/1.8V OUTPUT LOAD AC TEST CIRCUIT
VDDO
805
805
tR
Qx
Qy
2
205
205
Clock
Outputs
VDDO
2
tF
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
VDDO
2
Q0, Q1
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
84021AY
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REV. A NOVEMBER 7, 2003
10
ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84021 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 24Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01µF
.01µF
24Ω
VDDA
10µF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS84021 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 3 below were determined using a 2ꢀMHz, 18pF
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
XTAL2
XTAL1
C1
22p
X1
18pF Parallel Crystal
C2
22p
Figure 3. CRYSTAL INPUt INTERFACE
84021AY
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REV. A NOVEMBER 7, 2003
11
ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
0
200
ꢀꢀ.9°C/W
42.1°C/W
500
ꢀ0.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84021 is: 432ꢀ
84021AY
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REV. A NOVEMBER 7, 2003
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ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.1ꢀ
1.4ꢀ
0.4ꢀ
0.20
A1
A2
b
0.0ꢀ
1.3ꢀ
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
ꢀ.60 Ref.
9.00 BASIC
7.00 BASIC
ꢀ.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.4ꢀ
0.7ꢀ
θ
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 9ꢀ, MS-026
84021AY
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REV. A NOVEMBER 7, 2003
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ICS84021
260MHZ, CRYSTAL-TO-LVCMOS / LVTTL
FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
32 Lead LQFP
Count
2ꢀ0 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS84021AY
ICS84021AY
ICS84021AY
ICS84021AYT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use
in life support devices or critical medical instruments.
84021AY
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REV. A NOVEMBER 7, 2003
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