ICS9179-12 [ICSI]
3 DIMM Buffer; 3缓冲DIMM
| 型号： | ICS9179-12 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 3 DIMM Buffer |
| 文件： | 总9页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9179-12
3 DIMM Buffer
General Description
Features
Thirteen high speed, low noise buffers, supports up to
three SDRAM DIMMs.
The ICS9179-12 is a buffer intended for reduced pin count
2 - chip Intel BX chipset designs
Buffer outputs skew matched to within 250ps.
I2C Serial Configuration interface to allow individual
OUTPUTs to be stopped low.
An I2C interface is included, enabling individual outputs to be
turned on or off. With 13 outputs, up to 3 DIMMs are supported.
Multiple VDD, VSS pins for noise reduction
3.3V±5% supply voltage
28-pin SOIC and SSOP package
Propagation delay between 1 to 5.5ns
Operationto133MHzat3.3V±5%
Block Diagram
Pin Configuration
28-Pin SOIC and SSOP
* Internal pull-up resistor of 100K
Ohms to 3.3V on indicated inputs
Power Groups
VDD(0:4), GND(0:4) =PowersupplyforOUTPUTbuffer
VDDI, GNDI = Power supply for I2C circuitry
PentiumPro is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
9179-12 Rev C 7/16/99
ICS9179-12
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE DESCRIPTION
2, 3, 6, 7, 10, 11,
12, 18, 19, 22, 23,
26, 27
OUTPUT (0:12)
OUT Clock outputs1
9
14
15
BUF_IN
SDATA
SCLK
IN
I/O
I/O
Input for buffers
Data pin for I2C circuitry3
Clock pin for I2C circuitry3
1, 5, 20, 24, 28
4, 8, 17, 21, 25
VDD (0:4)
GND (0:4)
PWR 3.3V Power supply for OUTPUT buffers
PWR Ground for OUTPUT buffers
13
16
VDDI
GNDI
PWR 3.3V Power supply for I2C circuitry and internal logic
PWR Ground for I2C circuitry and internal logic
Notes:
1.
2.
3.
At power up all thirteen OUTPUTs are enabled and active.
OE has a 100K Ohm internal pull-up resistor to keep all outputs active.
TheSDATAandSCLKinputsbothhaveinternalpull-upresistorswithvaluesabove100KOhms.
2
ICS9179-12
Technical Pin Function Descriptions
VDD
This is the power supply to the internal core logic of the
device as well as the clock output buffers for OUTPUT (0:12).
This pin operates at 3.3V volts. Clocks from the listed
buffers that it supplies will have a voltage swing from Ground
to this level. For the actual guaranteed high and low voltage
levels for the Clocks, please consult the DC parameter table
in this data sheet.
GND
This is the power supply ground (common or negative) return
pin for the internal core logic and all the output buffers.
OUTPUT(0:12)
These Output Clocks are use to drive Dynamic RAMs and
are low skew copies of the CPU Clocks. The voltage swing
of the OUTPUTs output is controlled by the supply voltage
that is applied to VDD of the device, operates at 3.3 volts.
I2C
The SDATA and SCLOCK Inputs are used to program the
device. The clock generator is a slave-receiver device in the
I2C protocol. It will allow read-back of the registers. See
configuration map for register functions. The I2C
specification in Philips I2C Peripherals Data Handbook
(1996) should be followed.
BUF_IN
Input for Fanout buffers (OUTPUT 0:12).
VDDI
This is the power supply to I2C circuitry.
3
ICS9179-12
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2(H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification.
Read-BackwillsupportIntelPIIX4"Block-Read"protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
4
ICS9179-12
Serial Configuration Command Bitmaps
Byte0:OUTPUTClockRegister(Default=0)
Byte 1: OUTPUT Clock Register
BIT
Bit7
Bit6
Bit5
Bit4
PIN#
PWD
DESCRIPTION
OUTPUT5
BIT PIN# PWD
DESCRIPTION
OUTPUT11 (Act/Inact)
OUTPUT10 (Act/Inact)
OUTPUT9 (Act/Inact)
OUTPUT8 (Act/Inact)
Reserved
11
10
-
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
27
26
23
22
-
1
1
1
1
1
1
1
1
OUTPUT4
Reserved
-
Reserved
7
Bit3
Bit2
OUTPUT3
OUTPUT2
OUTPUT1
OUTPUT0
6
-
Reserved
Bit1
Bit0
3
2
1
1
19
18
OUTPUT7 (Act/Inact)
OUTPUT6 (Act/Inact)
Byte 2: OUTPUT Clock Register
BIT PIN# PWD DESCRIPTION
Functionality
OE#
OUTPUT (0:13)
Hi-Z
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
12
-
1
1
1
1
1
1
1
1
Reserved
OUTPUT12 (Act/Inact)
Reserved
0
1
1 X BUF_IN
-
Reserved
-
Reserved
-
Reserved
-
Reserved
-
Reserved
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
ICS9279-12 Power Consumption
The values below are estimates of target specifications.
Max 3.3V supply consumption
Max discrete cap loads
VDD = 3.465V
Condition
All static inputs = VDD or GND
No Clock Mode
(BUF_IN - VDD1 or GND)
I2C Circuitry Active
3mA
Active 66MHz
(BUF_IN = 66.66MHz)
230mA
360mA
500mA
Active 100MHz
(BUF_IN = 100.00MHz)
Active 133MHz
(BUF_IN = 133.33MHz)
5
ICS9179-12
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
IIH
VIN = VDD
VIN = 0 V; Inputs with no pull-up resistors
uA
uA
uA
mA
mA
mA
mA
mA
mA
MHz
pF
IIL
-5
IIL
VIN = 0 V; Inputs with 100K pull-up resistors -60
CL = 0 pF; FIN @ 66MHz
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
Fi1
80
120
180
250
230
360
500
133
5
Operating
CL = 0 pF; FIN @ 100MHz
120
160
180
240
300
CL = 0 pF; FIN @ 133MHz
Supply Current
C = 30 pF; RS=33 ; F @ 66MHz
Ω
L IN
C = 30 pF; RS=33 ; F @ 100MHz
Ω
L
IN
C = 30 pF; RS=33 ; F @ 133MHz
Ω
L
IN
Input frequency
VDD = 3.3 V; All Outputs Loaded
10
1
CIN
Input Capacitance
Logic Inputs
1Guarenteed by design, not 100% tested in production.
6
ICS9179-12
Electrical Characteristics - Outputs
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
RDSP
RDSN
VOH
VOL
CONDITIONS
MIN
10
TYP MAX UNITS
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -30 mA
IOL = 23 mA
VOH = 2.0 V
24
24
Ω
Ω
10
2.6
V
0.4
-54
V
IOH
mA
mA
ns
ns
%
IOL
VOL = 0.8 V
40
45
Tr
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.33
1.33
55
250
5.5
5
Fall Time1
Duty Cycle1
Tf
Dt
Skew1
Tsk
VT = 1.5 V
ps
ns
ns
ns
ns
TPROP1
TPROP2
VT = 1.5 V
1
1
1
1
VT = 50% BIN to 10% OUT
Propagation1
TPROPEN VT = 1.5 V
TPROPDIS VT = 1.5 V
8
8
1Guarenteed by design, not 100% tested in production.
7
ICS9179-12
COMMON
DIMENSIONS
D
VARIATIONS
SYMBOL
MIN.
NOM.
MAX.
N
MIN.
NOM.
MAX.
A
A1
A2
b
c
D
0.068
0.002
0.066
0.010
0.004
0.073
0.005
0.068
0.012
0.006
0.078
0.008
0.070
0.015
0.008
14
16
20
24
28
30
0.239
0.239
0.278
0.318
0.397
0.397
0.244
0.244
0.284
0.323
0.402
0.402
0.249
0.249
0.289
0.328
0.407
0.407
See Variations
0.209
E
0.205
0.212
0.0256
BSC
e
H
L
N
0.301
0.025
0.307
0.030
See Variations
4°
0.311
0.037
28 Pin SSOP Package
0°
8°
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
8
ICS9179-12
LEAD COUNT
DIMENSIONL
28L
0.704
SOIC Package
Ordering Information
ICS9179M-12
Example:
ICS XXXX M - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC F=SSOP
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
9
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