ICS9248-146 [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩
| 型号： | ICS9248-146 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 文件： | 总16页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-146
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
Single chip clock solution for SIS630S chipsets.
Pin Configuration
VDDA
(AGPSEL)REF0
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL
1
*
CPUCLK0
CPUCLK1
CPUCLK2
GND
Output Features:
1
*(FS3)REF1
3
4
5
GND
X1
X2
•
•
•
•
•
•
3- CPUs @ 2.5V
13 - SDRAM @ 3.3V
6- PCI @3.3V,
6
VDDSDR
VDDPCI
7
SDRAM0
*(FS1)PCICLK_F
*(FS2)PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
GND
8
SDRAM1
9
SDRAM2
2 - AGP @ 3.3V
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
SDRAM3
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
SDRAM8/PD#
SDRAM9/SDRAM_STOP#
GND
SDRAM10/PCI_STOP#
SDRAM11/CPU_STOP#
SDRAM12
VDDSDR
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz)
VDDAGP
AGPCLK0
AGPCLK1
GND
•
2- REF @3.3V, 14.318MHz.
Features:
GND
*(FS0)48MHz
*(MODE)24_48MHz
VDD48
•
•
•
Up to 166MHz frequency support
Support FS0-FS3 trapping status bit for I2C read back.
SDATA
SCLK
Support power management: CPU, PCI, SDRAM stops
and Power down Mode form I2C programming.
48-Pin 300mil SSOP
•
•
Spread spectrum for EMI control (0 to -0.5%, 0.25%).
Uses external 14.318MHz crystal
*1These inputs have a 120K pull down to GND.
These are double strength.
Skew Specifications:
•
•
•
•
CPU - CPU: < 175ps
SDRAM - SDRAM < 250ps (except SDRAM12)
PCI - PCI: < 500ps
CPU (early) - PCI: 1-4ns (typ. 2ns)
Functionality
Block Diagram
AGP SEL AGP SEL
FS3 FS2 FS1 FS0 CPU SDRAM PCICLK
PLL2
48MHz
= 0
= 1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
66.67
100.00 100.00
166.67 166.67
133.33 133.33
66.67 100.00
100.00 66.67
100.00 133.33
133.33 100.00
112.00 112.00
124.00 124.00
66.67
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.60
31.00
66.67
66.67
66.66
66.67
66.67
66.67
66.67
66.67
67.20
62.00
50.00
50.00
55.56
50.00
50.00
50.00
50.00
50.00
56.00
46.50
24_48MHz
/ 2
X1
X2
XTAL
OSC
REF(1:0)
2
3
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
CPUCLK (2:0)
SDRAM (12:0)
SDRAM
DIVDER
Stop
Stop
13
5
SDATA
SCLK
Control
Logic
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
AGP (1:0)
1
1
0
0
1
1
0
1
138.00 138.00
150.00 150.00
34.50
30.00
69.00
60.00
51.75
50.00
FS(3:0)
PD#
AGP
DIVDER
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
MODE
2
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
66.67 133.33
100.00 150.00
150.00 100.00
160.00 120.00
33.33
30.00
30.00
30.00
66.67
60.00
60.00
60.00
50.00
50.00
50.00
48.00
Config.
Reg.
AGP_SEL
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-146 RevA- 4/23/01
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9248-146
Power Groups
Analog
General Description
The ICS9248-146 is the single chip clock solution for
Desktop/Notebook designs using the SIS 630S style chipset.
It provides all necessary clock signals for such a system.
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI=PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-146
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
MODE Pin Power Management Control Input
MODE
Pin 21
Pin 27
Pin 28
Pin 30
Pin 31
SDRAM8
PD#
0
SDRAM11
SDRAM10
SDRAM9
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
1
CPU_STOP# PCI_STOP# SDRAM_STOP#
Pin Configuration
PIN NUMBER
1, 7, 15, 22, 25,
35, 43
PIN NAME
TYPE
DESCRIPTION
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGP frequency select pin.
VDD
PWR
AGPSEL
REF0
FS3
IN
2
3
OUT
IN
14.318 MHz reference clock.
Frequency select pin.
REF1
OUT
14.318 MHz reference clock.
4, 14, 18, 19, 29,
GND
PWR
Ground pin for 3V outputs.
32, 39, 44
5
6
X1
X2
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
OUT
IN
FS1
8
9
PCICLK_F
FS2
OUT
IN
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCICLK0
PCICLK (4:1)
AGP (1:0)
FS0
OUT
OUT
OUT
IN
PCI clock output.
13, 12, 11, 10
17, 16,
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
20
48MHz
OUT
48MHz output clock
Pin 27, 28, 30, & 31 function select pins
0=Desktop 1=Mobile mode
MODE
IN
21
24_48MHz
SDATA
SCLK
OUT
I/O
Clock output for super I/O/USB default is 24MHz
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
23
24
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input
is low and MODE pin is in Mobile mode
SDRAM clock output
CPU_STOP#
SDRAM11
PCI_STOP#
IN
OUT
IN
27
28
30
Stops all CPUCLKs clocks at logic 0 level, when input is low and MODE pin
is in Mobile mode
SDRAM clock output
SDRAM10
SDRAM9
OUT
OUT
SDRAM clock output
Stops all SDRAM clocks at logic 0 level, when input is low and MODE pin
is in Mobile mode
SDRAM_STOP#
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
PD#
IN
31
SDRAM8
OUT
OUT
SDRAM clock output
26 33, 34, 36, 37,
38, 40, 41, 42
45, 46, 47
SDRAM (12, 7:0)
SDRAM clock outputs
CPUCLK (2:0)
VDDL
OUT
PWR
CPU clock outputs.
48
Power pin for the CPUCLKs. 2.5V
Third party brands and names are the property of their respective owners.
2
ICS9248-146
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
Bit 7 Bit 6 Bit 5 Bit 4
FS3 FS2 FS1 FS0
Bit 2
AGP
AGP
CPU
SDRAM
PCI
Spread Precentage
SEL = 0 SEL = 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.67
100.00
166.67
133.33
66.67
100.00
100.00
133.33
112.00
124.00
138.00
150.00
66.67
100.00
150.00
160.00
103.00
100.30
200.00
133.73
103.00
137.33
66.87
133.73
110.00
115.00
140.00
101.50
100.30
105.00
105.00
135.33
66.67
100.00
166.67
133.33
100.00
66.67
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.60
31.00
34.50
30.00
33.33
30.00
30.00
30.00
34.33
33.43
33.33
33.43
34.33
34.33
33.43
33.43
33.00
34.50
35.00
33.83
33.43
35.00
31.50
33.83
66.67
66.67
66.66
66.67
66.67
66.67
66.67
66.67
67.20
62.00
69.00
60.00
66.67
60.00
60.00
60.00
68.67
66.87
66.67
66.87
68.67
68.67
66.87
66.87
66.00
69.00
70.00
67.67
66.87
70.00
63.00
67.67
50.00
50.00
55.56
50.00
50.00
50.00
50.00
50.00
56.00
46.50
51.75
50.00
50.00
50.00
50.00
48.00
50.00
50.00
50.00
50.15
51.50
51.50
50.15
50.15
55.00
57.50
52.50
50.00
50.15
52.50
52.50
50.75
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 to -0.5% Down Spread
+/- 0.25% Center Spread 00000
133.33
100.00
112.00
124.00
138.00
150.00
133.33
150.00
100.00
120.00
103.00
100.30
200.00
133.73
137.33
103.00
100.30
100.30
110.00
115.00
140.00
101.50
133.73
140.00
157.50
101.50
Bit 2
Bit 7:4
Note1
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit , 2 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Bit 3
Bit 1
Bit 0
0
1
0
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
3
ICS9248-146
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
PIN# PWD
DESCRIPTION
Sel24_48
(1:24MHz, 0:48MHz)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Reserved
Reserved
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
Bit 7
-
1
-
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
Reserved
13
12
11
10
9
Reserved
-
Reserved
47
46
45
-
CPUCLK0
CPUCLK1
CPUCLK2
Reserved
8
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Reserved
24_48MHz
48MHz
33
34
36
37
38
40
41
42
1
1
1
1
1
1
1
1
21
20
26
27
28
30
31
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Byte 5: AGP, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
X
X
X
1
FS3 (Readback)
FS2 (Readback)
FS1 (Readback)
FS0 (Readback)
REF1
-
-
2
3
1
REF0
17
16
1
AGPCLK1
AGPCLK0
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
4
ICS9248-146
Byte 6: Control , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
REF strength 0=1X, 1=2X
Bit7
2,3
0
CPUCLK2 - Stop - Control
0=CPU_STOP# will control CPUCLK2,
1=CPUCLK2 is free running even if CPU_STOP# is low
Bit6
45
0
Bit5
Bit4
Bit3
Bit2
Bit1
-
-
-
-
-
X
X
X
X
X
AGPSEL (Readback)
MODE (Readback)
CPU_STOP# (Readback)
PCI_STOP# (Readback)
SDRAM_STOP# (Readback)
AGP Speed Toggle
0=AGPSEL (pin2) will be determined by latch input setting,
1=AGPSEL will be opposite of latch input setting
Bit0
-
0
Byte 7: Vendor ID Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
1
0
1
0
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Third party brands and names are the property of their respective owners.
5
ICS9248-146
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Volt age VDD = 3.3 V +/-5%VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Supply Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
400
600
16
5
IDD
CL=30 pF, CPU @ 66, 100 MHz
390
300
mA
Power Down
PD
µ
A
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
Logic Inputs
12
27
14.318
MHz
pF
CIN
CINX
Ttrans
TS
X1 & X2 pins
45
3
pF
Transition Time
Settling Time
Clk Stabilization1
Skew
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
TSTAB
TCPU-PCI
TCPU-SDRAM
From VDD= 3.3 V to 1% target Freq.
CPUVT= 1.5 V PCI VT=1.25V
CPUVT= 1.5 V SDRAM VT=1.25
3
4
0
ms
ns
ps
1
1.9
Skew
-500
-300
1 Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-146
Electrical Characteristics - CPU
TA = 0 - 70C; VDDL = 2.5 V +/-5%; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
RDSP2B
RDSN2B
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
10
TYP
MAX UNITS
Output Impedance1
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -12.0 mA
IOL = 12 mA
20
20
Ω
Ω
10
2
V
0.4
-19
V
VOH = 1.7 V
mA
mA
ns
IOL2B
VOL = 0.7 V
19
0.4
0.4
45
Rise Time1
Fall Time1
Duty Cycle1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.2
1.1
1.6
1.6
55
tf2B
dt2B
ns
%
ps
ps
ps
46.9
43
Skew window0:1
Skew window0:2
Jitter, Cycle-to-cycle1
tsk2B
VT = 1.25 V
175
375
250
tsk2B
VT = 1.25 V
142
177
tjcyc-cyc
VT = 1.25 V, CPU=66 MHz
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24-48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
CONDITIONS
MIN
20
TYP
MAX UNITS
1
RDSP5B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -14 mA
IOL = 6.0 mA
VOH = 2.0 V
60
60
Ω
Ω
1
RDSN5B
20
VOH15
VOL5
IOH5
2.4
V
0.4
-20
V
mA
mA
IOL5
VOL = 0.8 V
10
0.4
0.4
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.45
1.5
4
4
ns
ns
Fall Time1
Duty Cycle1
tf5
dt5
52.5
210
55
%
ps
tcycle to cycle VT = 1.5 V
500
Jitter
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-146
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
CONDITIONS
MIN
12
TYP
MAX UNITS
1
RDSP1B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1B
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-29
V
VOH @ MIN = 1.0 V
VOL @ MIN = 1.95 V
mA
mA
29
0.5
0.5
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2.3
2.3
2.5
2.5
55
ns
ns
%
ps
ps
Fall Time1
tf1
Duty Cycle1
dt1
51.2
108
353
Skew window1
tsk1
VT = 1.5 V
500
500
Jitter, Cycle-to-cycle1
tjcyc-cyc1
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20-30 pF (unless otherwise specified)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
CONDITIONS
MIN
10
TYP
MAX UNITS
1
Ω
Ω
RDSP3B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
24
24
1
RDSN3B
10
VOH3
VOL3
IOH3
IOL3
2.4
V
0.4
-46
V
mA
mA
VOL = 0.8V
Rise Time1
Fall Time1
Duty Cycle1
tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.8
0.8
1.6
1.6
55
ns
ns
%
ps
ps
ps
tf3
dt3
45
48.5
192
290
173
Skew window1(0:11)
Skew window1( 0:12)
Jitter, Cycle-to-cycle1
tsk3
tsk3
VT = 1.5 V
250
500
250
VT = 1.5 V
tjcyc-cyc3
VT = 1.5 V, CPU=66,100,133 MHz
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-146
Electrical Characteristics - AGP
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
MAX UNITS
1
Output Impedance
RDSP4B
VO=VDD*(0.5)
55
55
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN4B
VO=VDD*(0.5)
IOH = -18 mA
IOL = 18 mA
VOH = 2.0 V
VOL = 0.8 V
12
2
Ω
V
VOH4B
VOL4B
IOH4B
IOL4B
0.4
-19
V
mA
mA
19
0.5
0.5
45
tr4B
VOL = 0.4 V, VOH = 2.4 V
1.5
1.6
2
ns
ns
%
ps
ps
Fall Time1
tf4B
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
2
Duty Cycle1
Skew window1
Jitter Cyc-Cyc
dt4B
tsk1
tjcyc-cyc1
52.3
55.5
239
55
VT = 1.5 V
175
500
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%;VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
VOL5
IOH5
IOL5
CONDITIONS
IOH = -12 mA
MIN
TYP
MAX UNITS
2.4
V
IOL = 9 mA
0.4
-22
V
mA
mA
ns
VOH = 2.0 V
VOL = 0.8 V
16
45
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
1.8
1.9
4
4
Fall Time1
tf5
ns
Duty Cycle1
dt5
54.5
55
%
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-146
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock sends first byte (Byte 0) through byte 7
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Read:
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Start Bit
Address
Address
D3(H)
D2(H)
ACK
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
Dummy Byte Count
Byte 0
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
Stop Bit
Byte 7
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
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10
ICS9248-146
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) on the ICS9248-
146 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
11
ICS9248-146
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-146. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-146.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
Third party brands and names are the property of their respective owners.
12
ICS9248-146
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-146. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-146 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-146 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248-146.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
13
ICS9248-146
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an asychronous input to the clock synthesizer. It is used to stop SDRAM clocks for low power operation.
SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-146. All other clocks will continue to run while
the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that
guarantees the high pulse width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to
the SDRAM clocks inside the ICS9248-146.
3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
14
ICS9248-146
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-146 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
15
ICS9248-146
c
N
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
L
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
1
2
10.03
7.40
10.68
7.60
.395
.291
.420
.299
a
hh xx 4455°°
D
0.635 BASIC
0.025 BASIC
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
α
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
A1
- CC --
VARIATIONS
D mm.
D (inch)
e
SEATING
PLANE
N
b
MIN
15.75
MAX
16.00
MIN
.620
MAX
.10 (.004)
C
48
.630
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS9248yF-146-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
16
information being relied upon by the customer is current and accurate.
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