ICS9248-150 [ICSI]
Frequency Generator for Multi - Processor Servers; 频率发生器 - 多处理器服务器
| 型号： | ICS9248-150 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator for Multi - Processor Servers |
| 文件： | 总10页 (文件大小：155K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-150
FrequencyGeneratorforMulti-ProcessorServers
Recommended Application:
ServerWorks Grand Champion Systems.
Pin Configuration
Output Features:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
PCICLK
VDD48
FS0/48MHz
FS1/48MHz#
GND48
SEL100/133
GNDPCI
VDDA
GNDA
PD#
•
•
•
8 - Differential CPU Clock Pairs @ 3.3V
1 - 3V 33MHz PCI clocks
1 - 48MHz clock
VDDCPU
CPUCLKT0
CPUCLKC0
GNDCPU
CPUCLKT1
CPUCLKC1
VDDCPU
CPUCLKT2
CPUCLKC2
GNDCPU
CPUCLKT3
CPUCLKC3
VDDCPU
REF
VDDCPU
CPUCLKT4
CPUCLKC4
GNDCPU
CPUCLKT5
CPUCLKC5
VDDCPU
CPUCLKT6
CPUCLKC6
GNDCPU
CPUCLKT7
CPUCLKC7
VDDCPU
MULTSEL0
MULTSEL1
GND
•
•
1 - Inverted 48MHz clock
1 - 14.318 reference output
Features:
•
•
•
Up to 200MHz frequency support
Support power management: Power Down Mode
Supports Spread Spectrum modulation: 0 to -0.5% down
spread.
•
•
Uses external 14.318MHz crystal
Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum.
SPREAD#
GNDREF
X1
X2
VDDREF
•
•
External resistor for current reference
FS pins for frequency select
GNDI REF
I REF
VDDI REF
Key Specifications:
•
•
•
•
PCI Output jitter <500ps
CPU Output jitter <200ps
48MHz Output jitter <350ps
REF Output jitter < 1000ps
48-Pin SSOP and TSSOP
Functionality
Block Diagram
SEL133/
100
FS0 FS1
Function
PLL2
48MHz
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Active 100MHz
100MHz Test Mode
100MHz Test Mode
Tristate all outputs
Active 133MHz
133MHz Test Mode
Active 200MHz
Reserved
48MHz#
0
X1
X2
XTAL
OSC
0
REF
0
1
PLL1
Spread
Spectrum
CPUCLKT (7:0)
CPUCLKC (7:0)
CPU
DIVDER
8
1
8
1
PCI
DIVDER
PCICLK
1
PD#
SPREAD#
Control
Logic
MULTSEL(1:0)
SEL100/133
FS(1:0)
Analog Power Groups
VDD48, GND48=48MHz, PLL2
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
Config.
Reg.
I REF
Digital Power Group
VDDREF, GNDREF=REF, Xtal
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
9248-150 Rev B 06/12/01
Third party brands and names are the property of their respective owners.
ICS9248-150
General Description
The ICS9248-150 is a main clock for ServerWorks Grand Champion Systems.
Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-150 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
PCICLK
OUT
PCI clock output
2, 6, 12, 18, 24, 31,
37, 43,
VDD
PWR
3.3V power supply
FS0
48MHz
FS1
IN
OUT
IN
Frequency select pin
48MHz clock output
Frequency select pin
3
4
48MHz#
OUT
Inverted 48MHz clock output
5, 9, 15, 21, 28, 34,
40, 47
GND
PWR
OUT
Ground pins for 3.3V supply
"True" clocks of differential pair CPU outputs. These are current
outputs and external resistors are required for voltage bias.
33, 36, 39, 42, 16,
13, 10, 7
CPUCLKT (7:0)
32, 35, 38, 41, 17,
14, 11, 8
"Complementory" clocks of differential pair CPU outputs. These are
current outputs and external resistors are required for voltage bias.
CPUCLKC (7:0)
REF
OUT
OUT
19
Reference output 14.318MHz
Invokes Spread Spectrum functionality on the Differential host
clocks, Active Low
20
SPREAD#
IN
22
23
X1
X2
X2 Crystal Input
14.318MHz Crystal input
X1 Crystal Output 14.318MHz Crystal output
VDDI REF
VDDA,
25, 46
PWR
Analog power supply 3.3V
This pin establishes the reference current for the CPUCLK pairs.
This pin takes a fixed precision resistor tied to ground in order to
establish the required current.
26
I REF
OUT
29, 30
44
MULTSEL(1:0)
PD#
IN
IN
CPU swing select inputs
Invokes power-down mode. Active Low.
GNDI REF
GNDA
27, 45
48
PWR
IN
Analog Ground pins for 3.3V supply
SEL100/133
CPU Frequency Select. Low=100MHz, High=133MHz
Third party brands and names are the property of their respective owners.
2
ICS9248-150
Truth Table
SEL
FS0
CPUCLK
MHz
PCICLK
MHZ
48
MHz
FS1
133/100
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100
100
33
33
48
Disable
Disable
Tristate
48
100
Disable
Tristate
33
Tristate
133
133
33
Disable
48
200
33
TCLK/2
TCLK/8
TCLK/2
CPUCLK Buffer Configuration
Conditions
Configuration
Load
Min
Max
All combinations of M0,
M1 and Rr shown in
table below
Nominal test load for
given configuration
Vdd = nominal (3.30V)
-7% I nominal +7% I nominal
-12% I nominal +12% I nominal
Iout
Iout
All combinations of M0,
M1 and Rr shown in
table below
Nominal test load for
given configuration
Vdd = 3.30 ± 5%
Third party brands and names are the property of their respective owners.
3
ICS9248-150
CPUCLK Swing Select Functions
Reference R,
Iref=
Vdd/(3*Rr)
Board Target
Trace/Term Z
Output
Current
Voh @ Z,
Iref=2.32mA
MULTSEL0
MULTSEL1
Rr = 475 1%
Iref = 2.32mA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.71V @ 60
0.59V @ 50
0.85V /2 60
0.71V @ 50
0.56V @ 60
0.47V @ 50
0.99V @ 60
0.82V @ 50
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 221 1%
Iref = 5mA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.75V @ 30
0.62V @ 20
0.90V @ 30
0.75V @ 20
0.60 @ 20
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
0.5V @ 20
1.05V @ 30
0.84V @ 20
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Third party brands and names are the property of their respective owners.
4
ICS9248-150
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
V
VIL
VSS-0.3
-5
A
µ
IIH
VIN = VDD
5
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
Input Low Current
IIL2
-200
Operating Supply
Current
Powerdown Current
IDD3.3OP
mA
mA
CL = 0 pF; Select @ 100 MHz
181
52
250
60
CL = 0 pF; Input address to VDD or GND
IDD3.3PD
Fi
Input Frequency
Pin Inductance
VDD = 3.3 V
14.318
MHz
nH
pF
Lpin
7
5
CIN
Logic Inputs
Input Capacitance1
COUT
CINX
Ttrans
Ts
Output pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition time1
Settling time1
Clk Stabilization1
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
ms
ms
3
TSTAB
From VDD = 3.3 V to 1% target frequency
3
ms
ns
ns
tPZH,tPZL Output enable delay (all outputs)
PHZ,tPLZ
1
1
10
10
Delay1
t
Output disable delay (all outputs)
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
ICS9248-150
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP
714
714
MAX UNITS
1
Output Impedance
RDSP 2B
VO = VDD*(0.5)
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
RDSN2B
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
Ω
VOH2B
V
VOL2B
0.4
-27
30
V
2
mA
mA
V OH@ MIN = 1.0 V, V OH@ MAX = 2.375 V
VOL @ MIN = 1.2 V, VOL @ MAX = 0.3 V
VOL = 20%, VOH = 80%
-27
27
IOH2B
2
Output Low Current
Rise Time
IOL2B
1
tr2B
175
324
700
ps
1
Fall Time
Diff. Crossover Voltag
Duty Cycle
tf2 B
VOH = 80%, VOL = 20%
VDD = 3.3V
175
45
501
50
700
55
ps
%
%
Vx
1
VT = 50%
VT = 50%
VT = 50%
VT = 50%
45
51.2
83.8
78.5
86
55
dt2B
1
Skew CPUT0:7
Skew CPU C0:7
Jitter
tsk2B
100
100
150
ps
ps
ps
1
tsk2B
1
tjcyc-cyc
1Guaranteed by design, not 100% tested in production.
2
IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
FO1
CONDITIONS
MIN
TYP
48
MAX UNITS
MHz
Output Frequency
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
60
Ω
V
1
VOH
2.4
1
VOL
0.4
-23
27
V
1
mA
mA
IOH
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
1
1
IOL
1
Rise Time
Fall Time
Duty Cycle
tr1
1.6
2.4
4
ns
ns
%
1
tf1
1
4
1
dt1
45
53.5
55
1
Skew
Jitter
tsk1
VT = 1.5 V
N/A
1000
ps
ps
1
tjcyc-cyc
VT = 1.5 V
305
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-150
Electrical Characteristics - PCI
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
FO1
CONDITIONS
MIN
TYP
33
MAX UNITS
MHz
Output Frequency
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
55
Ω
V
1
VOH
2.4
1
VOL
0.55
-33
38
V
1
mA
mA
IOH
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
1
IOL
1
Rise Time
Fall Time
Duty Cycle
tr1
0.5
0.5
45
1.2
1.2
2
ns
ns
%
1
tf1
2
1
dt1
49.9
55
1
Skew
Jitter
tsk1
VT = 1.5 V
500
500
ps
ps
1
tjcyc-cyc
VT = 1.5 V
139.7
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
FO1
CONDITIONS
MIN
TYP
48
MAX UNITS
MHz
Output Frequency
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
60
Ω
V
1
VOH
2.4
1
VOL
0.4
-23
27
V
1
mA
mA
IOH
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
1
1
IOL
1
Rise Time
Fall Time
Duty Cycle
tr1
1.3
1.6
4
ns
ns
%
1
tf1
1
4
1
dt1
45
52.5
55
1
Skew
Jitter
tsk1
VT = 1.5 V
N/A
350
ps
ps
1
tjcyc-cyc
VT = 1.5 V
175
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-150
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below.
PD#
CPUCLKT
CPUCLKC
VCO
Crystal
Notes:
1. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock.
Third party brands and names are the property of their respective owners.
8
ICS9248-150
c
In Millimeters
In Inches
N
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
2.41
0.20
0.20
0.13
MAX
2.80
0.40
0.34
0.25
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
L
A
A1
b
E1
E
INDEX
AREA
c
D
E
E1
e
SEE VARIATIONS
SEE VARIATIONS
10.03
7.40
10.68
7.60
.395
.291
.420
.299
1
2
a
hh xx 4455°°
0.635 BASIC
0.025 BASIC
D
h
L
0.38
0.50
0.64
1.02
.015
.020
.025
.040
N
SEE VARIATIONS
SEE VARIATIONS
A
0°
8°
0°
8°
α
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
e
SEATING
PLANE
MIN
15.75
MAX
16.00
MIN
.620
MAX
b
48
.630
.10 (.004)
C
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS9248yF-150-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
Third party brands and names are the property of their respective owners.
9
ICS9248-150
c
N
In Millimeters
In Inches
SYMBOL
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
--
0.05
0.80
0.17
0.09
MAX
1.20
0.15
1.05
0.27
0.20
MIN
--
.002
.032
.007
.0035
MAX
.047
.006
.041
.011
.008
L
A
A1
A2
b
E1
E
INDEX
AREA
c
D
E
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319 BASIC
1
22
E1
e
6.00
6.20
.236
.244
a
D
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
aaa
0°
--
8°
0.10
0°
--
8°
.004
A
A2
A1
VARIATIONS
- CC --
D mm.
D (inch)
N
MIN
12.40
MAX
12.60
MIN
.488
MAX
.496
e
SEATING
PLANE
b
48
Reference Doc.: JEDEC Publication 95, MO-153
aaa
C
10-0039
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
(240 mil)
Ordering Information
ICS9248yG-150-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
Third party brands and names are the property of their respective owners.
10
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