ICS9248-163 [ICSI]
AMD - K7 System Clock Chip; AMD - K7系统时钟芯片
| 型号： | ICS9248-163 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | AMD - K7 System Clock Chip |
| 文件： | 总14页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-163
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
AMD - K7 System Clock Chip
Recommended Application:
VIA KX133 style chipset
Output Features:
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDREF
REF0/CPU_STOP*
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF1/FS2*
GND
CPUCLK
GND
CPUCLKC0
CPUCLKT0
VDDA
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
VDD48
•
•
•
•
•
•
•
1 - Differential pair open drain CPU clocks
1 - CPU clock @ 3.3V
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V fixed.
1 - 24/48MHz @ 3.3V
X1
X2
VDD
*MODE/PCICLK_F
*FS3/PCICLK0
GND
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
2 - REF @3.3V, 14.318MHz.
Features:
•
•
Up to 166MHz frequency support
BUFFER IN
GND
Support power management: CPU stop and Power down
Mode from I2C programming.
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GND
•
•
Spread spectrum for EMI control
(
ꢀ.2ꢁ5 center spreadꢂ.
Uses external 14.318MHz crystal
SDATA
SCLK
48MHz/FS0*
24/48MHz/FS1*
48-Pin 300mil SSOP
*
Internal Pull-up Resistor of 120K to VDD
Functionality
Block Diagram
CPU
(MHz)
90.00
PCICLK
(MHz)
30.00
31.67
33.67
34.00
33.57
34.33
35.00
33.33
35.67
36.33
36.67
37.00
37.67
38.33
39.00
33.33
PLL2
48MHz
FS3
FS2
FS1
FS0
24_48MHz
/ 2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
REF (1:0)
CPUCLK
95.00
X1
X2
XTAL
OSC
101.00
102.00
100.90
103.00
105.00
100.00
107.00
109.00
110.00
111.00
113.00
115.00
117.00
133.30
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
CPUCLKC0
CPUCLKT0
SEL24_48#
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
Control
Logic
SDATA
SCLK
FS (3:0)
Config.
Reg.
SDRAM
DRIVER
SDRAM (11:0)
SDRAM_OUT
PD#
CPU_STOP#
BUFFER IN
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
9248-163 Rev A 9/22/00
Third party brands and names are the property of their respective owners.
ICS9248-163
Preliminary Product Preview
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDDREF
PWR REF, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
REF0
OUT
2
This asynchronous input halts CPUCLKT, CPUCLKC & SDRAM
(11:0) at logic "0" level when driven low.
CPU_STOP#1, 2
GND
IN
3,9,16,22,
33,39,45, 47
PWR Ground
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
4
X1
IN
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
PWR Supply for internal digital logic
5
6
X2
OUT
VDD
Free running PCI clock not affected by PCI_STOP# for power
management.
PCICLK_F
OUT
7
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
Frequency select pin. Latched Input. Internal Pull-up to VDD
MODE1, 2
IN
FS31, 2
IN
8
PCICLK0
SEL24_48#1, 2
PCICLK1
PCICLK (4:2)
VDDPCI
OUT PCI clock output
IN
Logic input to select 24 or 48MHz for pin 25 output
10
OUT PCI clock output.
13, 12, 11
OUT PCI clock outputs.
14
15
PWR Supply for PCICLK_F and PCICLK, nominal 3.3V
BUFFER IN
IN
Input to Fanout Buffers for SDRAM outputs.
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
SDRAM (11:0)
OUT
19,30,36
23
VDDSDR
SDATA
SCLK
PWR Supply for SDRAM 9nominal 3.3V.
I/O
IN
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
24
24_48MHz
FS11, 2
OUT 24MHz/48MHz clock output
IN Frequency select pin. Latched Input.
OUT 48MHz output clock
25
26
48MHz
FS01, 2
IN
Frequency select pin. Latched Input
27
40
41
42
VDD48
SDRAM_OUT
PD#
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
OUT Reference clock for SDRAM buffer
IN
Powers down chip, active low
VDDA
PWR Supply for core, & CPU 3.3V
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
"Complementory" clock of differential pair CPU output. This open
drain outputs needs an external 1.5V pull-up.
43
CPUCLKT0
CPUCLKC0
OUT
44
46
OUT
CPUCLK
REF1
FS21, 2
OUT 3.3V CPU clock output powered by VDDA
OUT 14.318 MHz reference clock.
48
IN
Frequency select pin. Latched Input
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-163
Preliminary Product Preview
General Description
The ICS9248-163 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks
required for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-163
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
MODE, Pin 7
Pin 2
(Latched Input)
CPU_STOP#
0
(Input)
REF0
(Output)
1
Power Groups
VDD48 = 48MHz, PLL2
VDDA = VDD for Core PLL, CPU
VDDREF = REF, Xtal
Third party brands and names are the property of their respective owners.
3
ICS9248-163
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
CPUCLK
PWD
Bit Bit Bit Bit Bit
PCICLK
(MHz)
30.00
31.67
33.67
34.00
33.57
34.33
35.00
33.33
35.67
36.33
36.67
37.00
37.67
38.33
39.00
33.33
40.00
31.25
32.50
33.43
33.75
34.25
34.75
33.33
35.00
35.75
36.25
37.00
37.50
38.75
41.67
33.33
Spread
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(MHz)
90.00
95.00
Precentage
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
101.00
102.00
100.90
103.00
105.00
100.00
107.00
109.00
110.00
111.00
113.00
115.00
117.00
133.30
120.00
125.00
130.00
133.73
135.00
137.00
139.00
100.00
140.00
143.00
145.00
148.00
150.00
155.00
166.66
133.33
Bit 2,
Bit 7:4
Reserved
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 3
Bit 1
Bit 0
0
1
0
0 - Normal
1 - Spread Spectrum Enabled 0.25% Center Spread
0 - Running
1- Tristate all outputs
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Third party brands and names are the property of their respective owners.
4
ICS9248-163
Preliminary Product Preview
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
-
-
X
1
FS2#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
X
1
1
1
1
1
1
1
FS0#
(Reserved)
(Reserved)
FS3#
7
PCICLK_F
(Reserved)
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
-
1
-
-
40
-
X
1
13
12
11
10
8
SDRAM_OUT
(SEL24_48#)#
X
CPUCLK0 enable (both
differential pair. "True" and
Complimentary")
Bit 1
Bit 0
43,44
46
1
1
CPUCLKT enable
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
28
29
31
32
34
35
37
38
1
1
1
1
1
1
1
1
SDRAM 7
SDRAM 6
SDRAM 5
SDRAM 4
SDRAM 3
SDRAM 2
SDRAM 1
SDRAM 0
-
1
1
1
1
1
1
1
1
-
(Reserved)
48MHz
26
25
17
18
20
21
24_48MHz
SDRAM 11
SDRAM 10
SDRAM 9
SDRAM 8
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
(Reserved)
(Reserved)
MODE#
FS1#
-
1
-
X
X
1
-
-
(Reserved)
REF1
48
2
1
1
REF0
Note: Dont write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
5
ICS9248-163
Preliminary Product Preview
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
µA
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
IDD3.3OP133 CL = 0 pF; Select @ 133MHz
PD
180
mA
Supply Current
600
16
5
Power Down
µA
MHz
pF
Input frequency
Fi
CIN
VDD = 3.3 V;
12
27
14.318
Logic Inputs
Input Capacitance1
Clk Stabilization1
CINX
X1 & X2 pins
45
3
pF
TSTAB
From VDD = 3.3 V to 1% target Freq.
ms
tCPU-SDRAM
tCPU-PCI
tCPU-AGP
-125
-100
-500
125
100
500
Skew1
VT = 50%
ps
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-163
Preliminary Product Preview
Electrical Characteristics - USB, REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
4
4
ns
ns
%
dt5
55
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
ZO
CONDITIONS
VO = VX
MIN
TYP
MAX
UNITS
Output Impedance
Ω
Termination to
Vpull-up(external)
Termination to
Vpull-up(external)
VOL = 0.3 V
Output High Voltage
Output Low Voltage
VOH2B
VOL2B
1
1.2
0.4
V
V
Output Low Current
Rise Time1
Fall Time1
IOL2B
tr2B
18
mA
ns
VOL = 0.3 V, VOH = 1.2 V
VOH = 1.2 V, VOL = 0.3 V
0.9
0.9
tf2B
ns
V
Vpullup(external)
+ 0.6
Differential voltage-AC1
Differential voltage-DC1
VDIF
Note 2
Note 2
Note 3
0.4
0.2
Vpullup(external)
+ 0.6
VDIF
VX
V
Differential Crossover
Voltage1
Duty Cycle1
Skew1
Jitter, Cycle-to-cycle1
Jitter, Absolute1
Notes:
550
45
1100
mV
dt2B
tsk2B
tjcyc-cyc2B
tjabs2B
VT = 50%
VT = 50%
VT = VX
55
200
250
+250
%
ps
ps
ps
VT = 50%
-250
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
Third party brands and names are the property of their respective owners.
7
ICS9248-163
Preliminary Product Preview
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
55
%
1
Skew
tsk2B
VT = 1.25 V
175
250
150
+250
ps
1
Jitter, Cycle-to-cycle tjcyc-cyc2B VT = 1.25 V
ps
1
Jitter, One Sigma
tj1s2B
VT = 1.25 V
VT = 1.25 V
ps
1
tjabs2B
Jitter, Absolute
-250
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.6
TYP MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-16
V
IOH1
mA
mA
IOL1
19
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
2
2
ns
ns
%
ps
dt1
55
500
Skew1(window)
1
Tsk
VT = 1.5V
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-163
Preliminary Product Preview
Electrical Characteristics - PCICLK_F
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.6
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-12
V
IOH1
mA
mA
IOL1
12
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
2
2
ns
ns
%
ps
dt1
55
200
Skew1(window)
1
Tsk
VT = 1.5V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
4
4
ns
ns
%
ns
ns
dt5
45
-1
55
0.5
1
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
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9
ICS9248-163
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
ICS (Slave/Receiver)
Address
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
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10
ICS9248-163
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248-
163 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
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11
ICS9248-163
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. CPU_STOP# is considered
to be a don't care during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state
as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may
require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-163 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
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12
ICS9248-163
Preliminary Product Preview
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-163. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-163.
3. All other clocks continue to run undisturbed.
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13
ICS9248-163
Preliminary Product Preview
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEEVARIATIONS
SEEVARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEEVARIATIONS
SEEVARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
9.652
28
34
48
56
64
9.398
11.303
15.748
18.288
20.828
.370
.445
.620
.720
.820
.380
.455
.630
.730
.830
11.557
16.002
18.542
21.082
Ordering Information
ICS9248yF-163-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
Third party brands and names are the property of their respective owners.
14
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