ICS9248-157 [ICSI]
Frequency Timing Generator for Pentium II Systems; 频率时序发生器奔腾II系统
| 型号： | ICS9248-157 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for Pentium II Systems |
| 文件： | 总11页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-157
Frequency Timing Generator for Pentium II Systems
Recommended Application:
ALI1621/1632M style chipsets
Output Features:
•
•
•
•
2 - CPUs @2.5V, up to 140MHz.
7 - PCI @3.3V, (including one free running)
1 - 48MHz, @3.3V fixed.
Pin Configuration
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
*FS1/REF0
X1
VDDR
2 - REF @3.3V, 14.318MHz.
REF1/FS0*
SPREAD#
VDDL
CPUCLK1
CPUCLK0/F
GNDL
GND
PCI_STOP#
VDDA
3
X2
Features:
•
•
4
**FS2/PCICLK_F
*SEL_CPUF#/PCICLK0
PCICLK1
5
Up to 140 MHz frequency support
Support power management: CPU, PCI stop and
Power down.
Spread spectrum for EMI control (0.5% down spread).
Uses external 14.318MHz crystal
FS pins for frequency select
6
7
GND
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK_E
VDD48
8
•
•
•
9
10
11
12
13
14
CPU_STOP#
PD#
DIV/4#
Key Specifications:
GND
*FS3/48MHz
•
•
•
•
CPU – CPU: <175ps
PCI – PCI: <250ps
CPU(early)-PCI: 1.5ns - 4ns
PCI_E (early) - PCI: 2.1ns
28 Pin 209mil SSOP
*These inputs have a 120K pull up to VDD
**These inputs have a 120K pull down to GND
Block Diagram
Functionality
FS3
0
FS2
0
FS1 FS0
CPU
33.33
63.33
69.99
66.66
97.00
96.22
91.50
83.33
50.00
95.25
105.00
100.00
66.66
126.35
139.65
133.33
PCI
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
16.66
31.66
35.00
33.33
32.33
32.07
30.50
27.77
16.66
31.75
35.00
33.33
16.66
31.66
35.00
33.33
0
0
X1
REF (1:0)
OSC
2
X2
0
0
0
0
CPU_STOP#
0
1
PLL
Spread
Spectrum
CPU
STOP
0
1
CPUCLK 1
FS (3:0)
2
/ 4
0
1
CPU
STOP
CPUCLK0/F
0
1
Glitch
Free
Control
Logic
PD#
Div4#
1
0
/ 2
/ 3
BUS
STOP
SPREAD#
PCICLK (4:0),
PCICLK_E
5
1
0
SEL_CPUF#
PCI_STOP#
1
0
PCICLK_F
48MHz
1
0
1
1
PLL2
1
1
1
1
1
1
ICS reserves the right to make changes in the device data
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
9248-157 Rev A - 1/16/01
Third party brands and names are the property of their respective owners.
ICS9248-157
Advance Information
General Description
The ICS9248-157 is the Main clock solution for Notebook designs using the Intel ALI1621/1632M style chipset. Along with
an SDRAM buffer such as the ICS9179-03, it provides all necessary clock signals for such a system.
Spread spectrum may be enabled by driving pin 26, SPREAD# active (Low) at power-on. Spread spectrum typically reduces
system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding.
The ICS9248-157 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process
and temperature variations.
Pin Descriptions
Pin number
Pin name
FS1
Type
Input
Description
Frequency select pin
1
REF0
Output 3.3V, 14.318 MHz reference clock output.
Input 14.318 MHz crystal input
Output 14.318 MHz crystal output
Input Frequency select pin
2
3
X1
X2
FS2
4
PCICLK_F
Output 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
Active low input to select CPUCLK0/F (pin 23) either normal CPUCLK or Free
running (not stoppable through CPU_STOP#) clock.
SEL_CPUF#
Input
5
PCICLK0
PCICLK (4:1)
GND
Output 3.3V PCI clock output
Output 3.3 V PCI clock outputs, generating timing requirements
Power Ground for clock outputs
11, 10, 9, 6
7, 15, 21
8
12
13
VDDPCI
PCICLK_E
VDD48
Power 3.3 V power for the PCI clock outputs
Output Early PCICLK output, offset from other PCICLKs, stopped by PCI-STOP#
Power 3.3 V power for 48 MHz clocks
FS3
48MHz
Input
Frequency select pin
14
16
Output Fixed 48MHz clock.
Active low input, enables the CPUCLK and the PCICLK to run at 1/4 of the regular
frequecies
DIV4#
PD#
Input
Input
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
17
18
CPU_STOP#
Input
19
20
22
23
VDDA
PCI-STOP#
GNDL
Power 3.3 V power for the core
Synchronous active low input used to stop the PCICLK in active low state. It will not
effect PCICLK_F or any other outputs.
Input
Power Ground for the CPU and Host clock outputs
2.5V CPU clock output; can be selected to be free running by driving
SEL_CPUF# low
CPUCLK0/F
Output
24
25
CPUCLK1
VDDL
0utput 2.5 V CPU and Host clock outputs
Power 2.5 V power for the CPU and Host clock outputs
power-on spread spectrum enable option. Active low = spread spectrum clocking
enable. Active high = spread spectrum clocking disable.
26
SPREAD#
Input
FS0
REF1
VDDR
Input
Frequency select pin
27
28
Output 3.3V, 14.318 MHz reference clock output.
Power 3.3 V power for the REFCLK and crystal clock outputs
Third party brands and names are the property of their respective owners.
2
ICS9248-157
Power Management
ClockEnableConfiguration
CPU_STOP# PCI_STOP# PWR_DWN#
CPUCLK
Low
PCICLK PCICLK_F
REF
Crystal
Off
VCOs
Off
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Low
Low
Low
Stopped
Low
Running
Running
Running
Running
Running Running Running
Running Running Running
Running Running Running
Running Running Running
Low
Running
Low
Running
Running
Running
Full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. During power up
and power down operations using the PD# pin will not cause clocks of a short or longer pulse than that of the running clock.
The first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry.
Board routing and signal loading may have a large impact on the initial clock distortion also.
PowerManagementRequirements
Latency
SIGNAL
SIGNAL STATE
No. of rising edges of free running
PCICLK
CPU_ STOP#
0 (Disabled)2
1 (Enabled)1
0 (Disabled)2
1
1
1
PCI_STOP#
PD#
1 (Enabled)1
1 (Normal Operation)3
0 (Power Down)4
1
3ms
2max
Notes.
1. Clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device.
2. Clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device.
3. Power up latency is when PD# goes inactive (high) to when the first valid clocks are output by the device.
4. Power down has controlled clock counts applicable to CPUCLK, PCICLK only.
The REF will be stopped independant of these.
PowerGroups:
VDDA = PLL Core
VDD48 = 48MHz Core
VDDPCI=PCICLK
VDDL=CPUCLK
VDDR = Xtal & REF
Third party brands and names are the property of their respective owners.
3
ICS9248-157
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
IIH
VIN = VDD
0.1
2.0
-100
60
µ
A
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
µ
A
IIL2
-200
µ
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
180
180
600
mA
Supply Current
Power Down
66
mA
A
µ
IDD3.3PD
CL = 0 pF; With input address to Vdd or GND
70
Supply Current
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
11
27
14.318
36
16
5
MHz
pF
CIN
Logic Inputs
CINX
Ttrans
TSTAB
X1 & X2 pins
45
3
pF
Transition Time1
Clk Stabilization1
Skew1
To 1st crossing of target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ns
3
TCPU-PCI1 VT = 1.5 V;
1.5
2.3
4
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
IDD2.5OP66
IDD2.5OP100
tCPU-PCI2
CONDITIONS
CL = 0 pF; Select @ 66.8 MHz
CL = 0 pF; Select @ 100 MHz
VT = 1.5 V; VTL = 1.25 V
MIN
TYP
16
MAX UNITS
72
mA
mA
Supply Current
Skew1
23
100
1.5
3
4
ns
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
4
ICS9248-157
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
2.3
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.2
0.4
-19
V
mA
mA
ns
-41
37
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.99
1.05
50.3
34
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
55
%
1
Skew
tsk2B
VT = 1.25 V
175
250
150
+250
ps
1
Jitter, Cycle-to-cycle
Jitter, One Sigma
Jitter, Absolute
tjcyc-cyc2B
VT = 1.25 V
203
ps
1
tj1s2B
VT = 1.25 V
VT = 1.25 V
ps
1
tjabs2B
-250
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V +/-5% VDDL = 2.5 V +/-5%; CL = 30 pF
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.1
0.1
-62
57
MAX UNITS
V
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-22
V
IOH1
mA
mA
IOL1
16
45
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.1
50
2
2
ns
ns
%
Fall Time1
Duty Cycle1
dt1
55
Skew1
tsk1
VT = 1.5 V
290
500
ps
Jitter, Cycle-to-cycle
tjcyc-cyc1
VT = 1.25 V
200
500
ps
Jitter, One Sigma1
Jitter, Absolute1
tj1s1
VT = 1.5 V
VT = 1.5 V
150
250
ps
ps
tjabs1
-250
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
ICS9248-157
Advance Information
Electrical Characteristics - REF/48MHz
TA = 0 - 70C; VDDL= 2.5V+/-5%; VDD = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.6
TYP
3.1
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.17
-44
42
0.4
-22
V
IOH5
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.03
0.9
4
4
ns
ns
%
%
%
dt5
52.9
55
3
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
5
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-157
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) on the ICS9248-
157 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
7
ICS9248-157
Advance Information
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-157. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a low
state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4 CPUCLKs
and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs
inside the ICS9248-157.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
Third party brands and names are the property of their respective owners.
8
ICS9248-157
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-157. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-157 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
Third party brands and names are the property of their respective owners.
9
ICS9248-157
Advance Information
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal is synchronized internally by the ICS9248-157 prior to its control action of
powering down the clock synthesizer. Internal clocks will not be running after the device is put in power down state. When PD#
is active (low) all clocks are driven to a low state and held prior to turning off the VCOs and the crystal oscillator. The power on
latency is guaranteed to be less than 3ms. The power down latency is less than three CPUCLK cycles. PCI_STOP# and
CPU_STOP# are don’t care signals during the power down operations.
CPUCLK
(Internal)
PCICLK
(Internal)
PD#
CPUCLK
PCICLK_E, PCICLK_F,
PCICLK
REF
INTERNAL
VCOs
INTERNAL
CRYSTAL OSC.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside the ICS9248.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock is being generated.
Third party brands and names are the property of their respective owners.
10
ICS9248-157
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
-
MAX
2.00
-
MIN
-
MAX
.079
-
A
A1
A2
b
0.05
1.65
0.22
0.09
.002
.065
.009
.0035
1.85
0.38
0.25
.073
.015
.010
c
SEE VARIATIONS
SEE VARIATIONS
D
E
7.40
5.00
8.20
5.60
.291
.197
.323
.220
E1
e
0.65 BASIC
0.0256 BASIC
L
0.55
0.95
.022
.037
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
MAX
10.50
28
9.90
.390
M O-150 JE DE C
.413
6/ 1/ 00 Rev B
Doc.# 10-0033
Ordering Information
ICS9248yF-157-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data
Third party brands and names are the property of their respective owners.
identified in this publication without further notice. ICS advises
its customers to obtain the latest version of all device data to
verify that any information being relied upon by the customer is
11
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