ICS9248-189 [ICSI]
AMD - K7⑩ Clock Generator for Mobile System; AMD - K7 ™时钟发生器为移动系统
| 型号： | ICS9248-189 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | AMD - K7⑩ Clock Generator for Mobile System |
| 文件： | 总15页 (文件大小：237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-189
Integrated
Circuit
Systems, Inc.
Advance Information
AMD - K7™ Clock Generator for Mobile System
RecommendedApplication:
VIA K7/KN/KX-133 style chipset
Pin Configuration
Output Features:
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF01
REF
REF2/FS3*
GND
GND
VDD
1
•
•
•
•
•
•
•
1 - Differential pair open drain CPU clocks
1 - CPU clock @ 3.3V
7 - SDRAM @ 3.3V
8 - PCI @ 3.3V,
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz @ 3.3V
X2
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
CPUCLK_CS
CPUCLKT02
CPUCLKC02
CPU_STOP#*
CLK_STOP#*/PD#
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
3 - REF @ 3.3V, 14.318MHz.
Features:
•
•
Up to 166MHz frequency support
PCICLK6
Support power management via hardware select CPU
stop, CLOCK stop, PCI stop, and SDRAM stop
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
•
•
Support power management via I2C programing
Spread spectrum for EMI control
GND
GND
(
ꢀ.2ꢁ5 to ꢀ.ꢀ65 center, or ꢀ to -ꢀ.ꢁ5 or -1.ꢀ5 down
spread)
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
•
Uses external 14.318MHz crystal
SDATA
Key Specifications:
•
•
•
•
CPU - CPU Skew: <17ꢁps
CPU - SDRAM Skew: 12ꢁps
CPU - PCI Skew: 1ꢀꢀps
PCI - PCI Skew: <ꢁꢀꢀps
48-Pin 300mil SSOP & 240milTSSOP
*
Internal Pull-up Resistor of 120K to VDD
These outputs have double strength to drive 2 loads.
These outputs can be set to 1X or 1.5X strength
through I2C
1
2
Functionality
Block Diagram
FS2
0
FS1
0
FS0
0
CPU
PCI
33.33
33.33
Spread Percentage
+/- 0.35% Center Spread
+/- 0.35% Center Spread
PLL2
48MHz
100.00
133.33
100.00
133.33
100.00
133.33
100.00
133.33
24_48MHz
0
0
1
/ 2
0
1
0
33.33 0 to - 0.5% Down Spread
33.33 0 to - 0.5% Down Spread
REF (2:0)
X1
X2
XTAL
OSC
3
0
1
1
1
0
0
33.33
33.33
33.33
33.33
+/- 0.6% Center Spread
+/- 0.6% Center Spread
No Spread
PLL1
Spread
Spectrum
CPU
DIVDER
1
0
1
Stop
CPUCLK_CS
1
1
0
CPUCLKT0
CPUCLKC0
1
1
1
No Spread
Note: For a complete functionality table please see table in
page 3.
SEL24_48#
SDATA
PCI
DIVDER
Stop
Stop
PCICLK (6:0)
PCICLK_F
Control
Logic
7
6
SCLK
FS (3:0)
Power Groups
PD#
SDRAM
DIVIDER
SDRAM (5:0)
SDRAM_F
CPU_STOP#
CLK_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
Config.
Reg.
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
9248-189 Rev - 08/10/01
Third party brands and names are the property of their respective owners.
ICS9248-189
Advance Information
General Description
The ICS9248-189 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides
all clocks required for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-189 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Descriptions
PIN NUMBER
1, 6, 14, 24,
30, 35, 43
PIN NAME
TYPE
DESCRIPTION
VDD
PWR Power supply, nominal 3.3V
Crystal input, has internal load cap (36pF) and feedback
resistor from X2.
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF).
Frequency select pin, latched input
Free running PCI clock not affected by PCI_STOP# for power
management.
Frequency select pin, latched input
2
3
X1
IN
X2
OUT
FS21, 2
IN
OUT
IN
4
PCICLK_F
FS11, 2
5
PCICLK0
GND
PCICLK (6:1)
OUT PCI clock output
PWR Ground
OUT PCI clock outputs
7, 13, 21, 31, 34, 44, 45
15, 12, 11, 10, 9, 8
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level,
when input low.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low.
Input to Fanout Buffers for SDRAM outputs.
16
17
SDRAM_STOP#1
IN
PCICLK_STOP#1
IN
IN
18
19
20
BUFFER IN
AVDD
AGND
PWR Supply for core, & CPU 3.3V
PWR Analog ground
FS01, 2
48MHz
SEL24_48#1, 2
24_48MHz
SDATA
IN
OUT 48MHz output clock
Frequency select pin, latched input
22
23
IN
Logic input to select 24 or 48MHz
OUT 24MHz/48MHz clock output
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
25
I/O
IN
26
SCLK
Free running SDRAM clock not affected by SDRAM_STOP# for
power management.
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
Powers down chip, active low except XTAL and CPUCLK_T0
& CPUCLKC0.
27
SDRAM_F
OUT
OUT
IN
28, 29, 32, 33, 36, 37
SDRAM (5:0)
CLK_STOP#1
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the VCO
and the crystal are stopped. The latency of the power down will not
be greater than 3ms.
38
PD#
IN
CPU_STOP#1,
CPUCLKC0
IN
Only stops CPUCLK_CS
"Complementary" clock of differential pair CPU output. This open
drain outputs needs an external 1.5V pull-up.
39
40
OUT
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
OUT CPU clock to the chipset
41
42
CPUCLKT0
OUT
CPUCLK_CS
REF2
FS31, 2
OUT 14.318 Mhz reference clock
46
IN
Frequency select pin, latched Input
47, 48
REF0 (1:0)
OUT 14.318 Mhz reference clock
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-189
Advance Information
Serial Configuration Command Bitmap
Functionality and Frequency Select Register (default = 0)
Bit
Description
PCICLK
PWD
Bit Bit Bit Bit Bit
CPUCLK
(MHz)
166.00
160.00
155.00
150.00
145.00
140.00
136.00
Spread
Precentage
OFF
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(MHz)
41.6
40.0
38.7
37.5
36.2
35.0
34.00
32.5
OFF
OFF
OFF
OFF
OFF
OFF
130.00
127.00
124.00
120.00
118.00
116.00
115.00
114.00
113.00
112.00
111.00
110.00
108.00
106.00
104.00
102.00
95.00
100.00
133.33
100.00
133.33
100.00
133.33
100.00
133.33
OFF
OFF
OFF
OFF
OFF
OFF
OFF
31.7
31.00
40.00
39.3
38.60
38.30
38.00
37.60
37.30
37.00
36.60
36.00
35.30
34.60
34.00
31.70
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
Reserved
00101
OFF
Bit 2:1,
Bit 6:4
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
+/- 0.35% Center Spread
+/- 0.35% Center Spread
0 to - 0.50% Down Spread
0 to - 0.50% Down Spread
+/- 0.60% Center Spread
+/- 0.60% Center Spread
OFF
OFF
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Third party brands and names are the property of their respective owners.
3
ICS9248-189
Advance Information
Byte 0: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
CLK_STOP#
(1 = PD#, 0 = CLK_STOP#)
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
-
-
-
-
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Bit 7
38
0
Bit 6
Bit 5
Bit 4
4
5
0
0
0
FS2
FS1
FS0
22
CPUCLKC0/T0
( 1 = 1X, 0 = 1.5X )
Hardware / Software Frequency
selection
Bit 3
40, 41
1
Bit 3
-
0
Bit 2
Bit 1
Bit 0
42
41
40
1
1
1
CPUCLK_CS
CPUCLKT0
CPUCLKC0
Bit 2
Bit 1
Bit 0
-
46
-
1
0
0
Reserved
FS3
Reserved
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15
12
11
10
9
1
1
1
1
1
1
1
1
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
PCICLK_F
-
0
0
1
1
1
1
1
1
23
SEL24_48#
48MHz
22
23
24_48MHz
SDRAM_F
SDRAM(5:4)
SDRAM(3:2)
SDRAM(1:0)
27
8
28, 29
32, 33
36, 37
5
4
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
FS0 (readback)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
22
5
X
X
X
X
X
1
FS1 (readback)
FS2 (readback)
FS3 (readback)
SEL24_48# (readback)
REF2
4
46
23
46
47
48
1
REF1
1
REF0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
4
ICS9248-189
Advance Information
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 7: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Don’t write into this register, writing into this
register can cause malfunction
Third party brands and names are the property of their respective owners.
5
ICS9248-189
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
VIL
VSS-0.3
0.8
5
V
µA
µA
µA
IIH
VIN = VDD
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
IIL2
-200
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
IDD3.3OP133 CL = 0 pF; Select @ 133MHz
Operating Supply
Current
180
mA
Input frequency
Fi
VDD = 3.3 V;
12
27
14.318
16
5
MHz
pF
CIN
Logic Inputs
Input Capacitance1
Clk Stabilization1
CINX
X1 & X2 pins
45
pF
TSTAB
tCPU-SDRAM
tCPU-PCI
From VDD = 3.3 V to 1% target Freq.
3
ms
-125
-100
-500
125
100
500
Skew1
VT = 50%
ps
tCPU-AGP
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-189
Advance Information
Electrical Characteristics - USB or 48MHz, REF
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
45
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
4
4
ns
ns
%
dt5
55
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLKT0/CPUCLKC0 (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
ZO
CONDITIONS
VO = VX
MIN
TYP
MAX
UNITS
Output Impedance
Ω
Termination to
Vpull-up(external)
Termination to
Vpull-up(external)
VOL = 0.3 V
Output High Voltage
Output Low Voltage
VOH2B
VOL2B
1
1.2
0.4
V
V
Output Low Current
Rise Time1
Fall Time1
IOL2B
tr2B
18
mA
ns
VOL = 0.3 V, VOH = 1.2 V
VOH = 1.2 V, VOL = 0.3 V
0.9
0.9
tf2B
ns
V
Vpullup(external)
+ 0.6
Differential voltage-AC1
Differential voltage-DC1
VDIF
Note 2
Note 2
Note 3
0.4
0.2
Vpullup(external)
+ 0.6
VDIF
VX
V
Differential Crossover
Voltage1
Duty Cycle1
Skew1
Jitter, Cycle-to-cycle1
Jitter, Absolute1
Notes:
550
45
1100
mV
dt2B
tsk2B
tjcyc-cyc2B
tjabs2B
VT = 50%
VT = 50%
VT = VX
55
200
250
+250
%
ps
ps
ps
VT = 50%
-250
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
3 - Vpullup(external) = 1.5V, Min = Vpullup(external)/2-150mV; Max=(Vpullup(external)/2)+150mV
Third party brands and names are the property of their respective owners.
7
ICS9248-189
Advance Information
Electrical Characteristics - CPUCLK_CS
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
55
%
1
Skew
tsk2B
VT = 1.25 V
175
250
150
+250
ps
1
Jitter, Cycle-to-cycle tjcyc-cyc2B VT = 1.25 V
ps
1
Jitter, One Sigma
tj1s2B
VT = 1.25 V
VT = 1.25 V
ps
1
tjabs2B
Jitter, Absolute
-250
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.6
TYP MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-16
V
IOH1
mA
mA
IOL1
19
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
2
2
ns
ns
%
ps
dt1
55
500
Skew1(window)
1
Tsk
VT = 1.5V
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-189
Advance Information
Electrical Characteristics - PCICLK_F
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.6
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
-12
V
IOH1
mA
mA
IOL1
12
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
2
2
ns
ns
%
ps
dt1
55
200
Skew1(window)
1
Tsk
VT = 1.5V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.4
-22
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 50%
4
4
ns
ns
%
ns
ns
dt5
45
-1
55
0.5
1
Jitter, One Sigma1
Jitter, Absolute1
tj1s5
tjabs5
VT = 1.5 V
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-189
Advance Information
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
10
ICS9248-189
Advance Information
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
11
ICS9248-189
Advance Information
CLK_STOP# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part.
CLK_STOP# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to
powering down the clock synthesizer.
Internal clocks are not running after the device is put in power down. When CLK_STOP# is active low all clocks need to be
driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The
power down latency should be as short as possible but conforming to the sequence requirements shown below. CPU_STOP#
is considered to be a don't care during the power down operations. The REF and 48MHz clocks are expected to be stopped in
the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the
LOW state may require more than one clock cycle to complete.
CLK_STOP#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-189 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. CLK_STOP# is an input pin which stops all clocks, expcpt XTAL and CPUCLKT0/CPUCLKC0
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
12
ICS9248-189
Advance Information
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-189. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-189.
3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
13
ICS9248-189
Advance Information
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEE VARIATIONS
SEE VARIATIONS
D
E
E1
e
10.033
7.391
10.668
7.595
.395
.291
.420
.299
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.620
MAX
.630
48
15.748
16.002
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
Ordering Information
ICS9248yF-189-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
Third party brands and names are the property of their respective owners.
14
ICS9248-189
Advance Information
SYMBOL
In Millimeters
COMMON DIMENSIONS
In Inches
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.27
0.20
MIN
-
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
c
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
E
E1
e
6.00
6.20
0.50 BASIC
0.75
.236
.244
0.020 BASIC
L
0.45
.018
.30
SEE VARIATIONS
SEE VARIATIONS
N
0°
-
8°
0°
-
8°
α
aaa
0.10
.004
VARIATIONS
D mm.
D (inch)
N
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
MIN
MAX
MIN
.488
MAX
(240 mil)
48
12.40
12.60
.496
7/6/00 Rev B
MO-153 JEDEC
Doc.# 10-0039
Ordering Information
ICS9248yG-189-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
Third party brands and names are the property of their respective owners.
15
相关型号：
©2020 ICPDF网 联系我们和版权申明