ICS9248-168 [ICSI]
AMD - K7⑩ Clock Generator for Mobile System; AMD - K7 ™时钟发生器为移动系统
| 型号： | ICS9248-168 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | AMD - K7⑩ Clock Generator for Mobile System |
| 文件： | 总14页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-168
AMD - K7™ Clock Generator for Mobile System
Recommended Application:
VIA KT133 style chipset
Pin Configuration
Output Features:
48
VDDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF01
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF
1
•
•
•
•
•
•
•
1 - Differential pair open drain CPU clocks
1 - CPU clock @ 3.3V
7 - SDRAM @ 3.3V
8 - PCI @ 3.3V,
1 - 48MHz, @ 3.3V fixed.
1 - 24/48MHz @ 3.3V
X2
REF2
GND
GND
VDD
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
CPUCLK2
CPUCLKT02
CPUCLKC02
CPU_STOP#*
PD#*
3 - REF @ 3.3V, 14.318MHz.
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
Features:
•
•
Up to 153MHz frequency support
PCICLK6
Support power management: CPU stop and Power down
Mode from I2C programming.
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
•
•
Spread spectrum for EMI control
(
ꢀ.25ꢁ to ꢀ.0ꢁ center, or ꢀ to -ꢀ.5ꢁ or -1.ꢀꢁ down
GND
GND
spread).
Uses external 14.318MHz crystal
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
SDATA
48-Pin 300mil SSOP
*
Internal Pull-up Resistor of 120K to VDD
1
These outputs have double strength to drive 2 loads.
These outputs can be set to 1.5X strength through I2C
2
Functionality
Block Diagram
FS2
0
FS1
0
FS0
0
CPU
PCI
33.33
33.33
Spread Percentage
+/- 0.35% Center Spread
+/- 0.35% Center Spread
PLL2
48MHz
100.00
133.33
100.00
133.33
100.00
133.33
90.00
24_48MHz
0
0
1
/ 2
0
1
0
33.33 0 to - 0.5% Down Spread
33.33 0 to - 0.5% Down Spread
REF (2:0)
CPUCLK
X1
X2
XTAL
OSC
0
1
1
1
0
0
33.33
33.33
30.00
30.00
+/- 0.6% Center Spread
+/- 0.6% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
PLL1
Spread
Spectrum
CPU
DIVDER
1
0
1
Stop
CPUCLKC0
CPUCLKT0
1
1
0
1
1
1
120.00
SEL24_48#
SDATA
PCI
DIVDER
Stop
Stop
PCICLK (6:0)
PCICLK_F
Control
Logic
SCLK
FS (2:0)
SDRAM
DRIVER
PD#
SDRAM (5:0)
SDRAM_F
CPU_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
Config.
Reg.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-168 Rev
B 01/09/01
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9248-168
Pin Descriptions
PIN NUMBER
1, 6, 14, 24,
30, 35, 43
PIN NAME
VDD
TYPE
DESCRIPTION
PWR Power supply, nominal 3.3V
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
Frequency select pin. Latched Input. Internal Pull-up to VDD
Free running PCI clock not affected by PCI_STOP# for power
management.
2
3
X1
IN
X2
OUT
FS21, 2
IN
OUT
IN
4
PCICLK_F
FS11, 2
Frequency select pin. Latched Input. Internal Pull-up to VDD
5
PCICLK0
OUT PCI clock output
7, 13, 20, 21, 31, 34,
44, 45
GND
PWR Ground
15, 12, 11, 10, 9, 8
PCICLK (6:1)
SDRAM_STOP#
OUT PCI clock outputs.
Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level,
16
IN
when input low
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input low
Input to Fanout Buffers for SDRAM outputs.
17
PCICLK_STOP#
IN
IN
18
19
BUFFER IN
AVDD
FS01, 2
PWR Supply for core, & CPU 3.3V
IN Frequency select pin. Latched Input
OUT 48MHz output clock
22
23
48MHz
SEL24_48#1, 2
24_48MHz
SDATA
IN
Logic input to select 24 or 48MHz for pin 25 output
OUT 24MHz/48MHz clock output
25
I/O
IN
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
26
SCLK
Free running SDRAM clock not affected by SDRAM_STOP# for
power management.
27
SDRAM_F
OUT
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
Powers down chip, active low
This asynchronous input halts CPUCLKT, CPUCLKC & SDRAM at
logic "0" level when driven low.
28, 29, 32, 33, 36, 37
SDRAM (5:0)
PD#
OUT
IN
38
39
CPU_STOP#1,
IN
"Complementory" clock of differential pair CPU output. This open
drain outputs needs an external 1.5V pull-up.
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
40
41
CPUCLKC0
CPUCLKT0
OUT
OUT
42
CPUCLK
OUT 3.3V CPU clock output powered by VDDA
OUT 14.318 Mhz reference clock.
46, 47, 48
REF0 (2:0)
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-168
General Description
The ICS9248-168 is a main clock synthesizer chip for AMD-K7 based note book systems with VIA style chipset. This provides
all clocks required for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-168
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Power Groups
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
Third party brands and names are the property of their respective owners.
3
ICS9248-168
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
CPUCLK
PWD
Bit Bit Bit Bit Bit
PCICLK
(MHz)
33.33
33.33
33.33
33.33
33.33
33.33
30.00
30.00
33.43
33.43
33.43
33.43
33.67
33.67
34.00
34.00
34.33
34.33
34.67
34.67
35.00
35.00
35.67
35.67
36.67
36.67
38.33
38.33
33.33
33.33
33.33
33.33
Spread
2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
(MHz)
100.00
133.33
100.00
133.33
100.00
133.33
90.00
Precentage
+/- 0.35% Center Spread
+/- 0.35% Center Spread
0 to - 0.5% Down Spread
0 to - 0.5% Down Spread
+/- 0.6% Center Spread
+/- 0.6% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.60% Center Spread
+/- 0.60% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.35% Center Spread
+/- 0.50% Center Spread
+/- 0.50% Center Spread
0 to -1.0% Down Spread
0 to -1.0% Down Spread
120.00
100.30
133.73
100.30
133.73
101.00
134.66
102.00
136.00
103.00
137.33
104.00
138.66
105.00
140.00
107.00
142.66
110.00
146.66
115.00
153.33
100.00
133.33
100.00
133.33
Reserved
00101
Bit 2,
Bit 7:4
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
Bit 3
Bit 1
Bit 0
0
1
0
0 - Normal
1 - Spread Spectrum Enabled 0.25% Center Spread
0 - Running
1- Tristate all outputs
Note: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Third party brands and names are the property of their respective owners.
4
ICS9248-168
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
PCICLK_F
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
22
1
1
1
1
1
1
1
1
FS0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4
1
1
1
1
1
1
1
1
5
FS1
15
12
11
10
9
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
4
FS2
42
CPUCLK 0=1.5X 1=1X
Reserved
-
41, 40
-
CPUCLKT/C 0=1.5X 1=1X
Reserved
8
42
CPUCLK
5
Byte 3: Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Reserved
SDRAM_F
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
-
1
1
1
1
1
1
1
1
27
28
29
32
33
36
37
23
22
23
48
47
46
-
SEL24_48#
48MHz
24_48MHz
REF0
REF1
REF2
Reserved
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
Reserved
BIT PIN# PWD
DESCRIPTION
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
5
ICS9248-168
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V+/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating Supply Current
Power Down
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
VIL
VSS-0.3
0.8
5
V
IIH
VIN = VDD
uA
uA
uA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL =20 pF; SDRAM not running
-5
IIL2
-200
IDD3.3OP
PD
75
280
180
600
16
mA
uA
Input frequency
Fi
VDD = 3.3 V
12
27
14.318
MHz
CIN
CINX
Logic Inputs
5
45
3
pF
pF
ms
ps
Input Capacitance1
X1 & X2 pins
Clk Stabilization1
Skew window1
TSTAB
From VDD = 3.3 V to 1% target Freq.
Vt=50% CPU - 1.5V PCI; CPU Leads
TCPU-PCI window
250
500
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
Output Impedance1
SYMBOL
RDSP5B
CONDITIONS
MIN
20
TYP
24
MAX UNITS
Ω
VO=VDD*(0.5)
60
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter, Cycle-to-Cycle1
Ω
RDSN5B
VOH5
VOL5
IOH5
VO=VDD*(0.5)
IOH = -12 mA
IOL = 9 mA
20
44
60
2.4
V
0.4
-22
V
mA
mA
VOH = 2.0 V
VOL = 0.8 V
IOL5
16
45
1
tr5
VOL = 0.4 V, VOH = 2.4 V
1.7
1.5
4.0
4.0
ns
ns
%
ps
1
tf5
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
dt5
52.8
770
55
1
VT = 1.5 V
1000
tjcyc-cyc5
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-168
Electrical Characteristics - CPUCLK
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
VOH2B
VOL2B
IOL2B
CONDITIONS
IOH = -12.0 mA
MIN
1
TYP
MAX
1.8
UNITS
V
Output High Voltage
Output Low Voltage
Output Low Current
Output Low Current
IOH = 12.0 mA
VOL = 1.7 V
VOL = 0.7 V
0.8
V
mA
mA
ns
18
18
IOL2B
1
Rise Time1
Fall Time1
Duty Cycle1
VOL = 0.4 V, VOL = 2.0V
VOH = 2.0 V, VOL = 0.4V
0.9
0.8
1.6
1.6
tr2B
1
ns
tf2B
1
%
ps
ps
ps
dt2B
VT = 1.5V
VT = 1.5V
45
51.5
55
Skew window1
Jitter, Cycle-to-cycle1
Jitter, Absolute1
Notes:
1
tsk2B
200
300
250
1
tjcyc-cyc2B VT = 1.5V
125
1
tjabs2B
VT = 1.5V
1 - Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70C; VDD=3.3V +/- 5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
1
Ω
Output Impedance
Output High Voltage
Output Low Voltage
Output Low Current
ZO
VO=VX
60
1.8
0.8
VOH2B
VOL2B
IOL2B
Termination to Vpull-up(external)
Termination to Vpull-up(external)
1
V
V
mA
ns
ns
VOL = 0.3 V
18
1
Rise Time1
VOH = 1.2 V, VOL = 0.3V
VOL = 0.3 V, VOH = 1.2V
0.5
0.3
0.9
0.9
tr2B
1
tf2B
Fall Time1
Differential voltage-AC1
VDIF
VDIF
VX
Note 2
0.4
0.2
1.2
45
Vpull-up(ext) + 0.6
V
V
Differential voltage-DC1
Diff Crossover Voltage1
Duty Cycle1
Note 2
Vpull-up(ext) + 0.6
Note 3
0.82
51.5
1.8
55
V
1
%
dt2B
VT = 50%
VT = 50%
Skew window1
1
tsk2B
200
300
250
ps
ps
ps
Jitter, Cycle-to-cycle1
Jitter, Absolute1
Notes:
1
tjcyc-cyc2B VT = VX
125
1
tjabs2B
VT = 50%
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true" input Level
and VCP is the "complement" input level.
3 - Vpull-up(external) = 2.7V, Min=Vpull-up(external)/2-150mV; Max=Vpull-up(external)/2 +150mV
Third party brands and names are the property of their respective owners.
7
ICS9248-168
Electrical Characteristics - SDRAM_OUT
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
Output Impedance1
SYMBOL
RDSP3
CONDITIONS
MIN
TYP
MAX UNITS
Ω
Ω
10
11
24
24
VO=VDD*(0.5)
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
10
12
RDSN3
VOH3
VOL3
IOH3
VO=VDD*(0.5)
IOH = -11 mA
IOL = 11 mA
VOH = 2.0 V
VOL = 0.8 V
2
V
V
0.4
-12
mA
mA
IOL3
12
45
Rise Time1
Fall Time1
Duty Cycle1
1
tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
0.9
0.8
51.5
220
3
1.5
1.5
55
ns
ns
%
ps
ns
1
tf3
1
dt3
Skew (ouput to output)1
Skew (Buffer In to output)1
tsk3A
tsk3B
VT = 1.5 V
250
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = VDDL = 3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
1
Ω
Ω
Output Impedance
RDSP2B
VO=VDD*(0.5)
12
24
23
55
55
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
Jitter, Cyc-to-Cyc
RDSN2B
VO=VDD*(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
VOH1
VOL1
IOH1
IOL1
2.6
V
V
0.4
-16
mA
mA
19
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.29
1.29
50.2
2.5
2.5
55
ns
ns
%
tf1
dt1
tsk1
VT = 1.5 V
VT = 1.5 V
280
86
400
200
ps
ps
tjcyc-cyc1
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-168
Electrical Characteristics - PCICLK_F
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
Output Impedance1
SYMBOL
RDSP1B
CONDITIONS
MIN
12
TYP
14
MAX UNITS
Ω
VO=VDD*(0.5)
55
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Ω
RDSN1B
VOH1
VOL1
IOH1
VO=VDD*(0.5)
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
13
55
2.6
V
0.4
-12
V
mA
mA
IOL1
12
45
Rise Time1
Fall Time1
Duty Cycle1
Skew window1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.3
2.0
2.0
55
ns
ns
%
ps
ps
tf1
dt1
50.2
280
tsk1
VT = 1.5 V
400
200
Jitter, Cycle-to-Cycle1
tjcyc-cyc1
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 24MHz, 48MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
Output Impedance1
SYMBOL
RDSP5B
CONDITIONS
MIN
TYP
MAX UNITS
Ω
VO=VDD*(0.5)
20
24
44
60
Output Impedance1
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
Fall Time1
Duty Cycle1
Jitter, Cycle-to-Cycle1
Ω
RDSN5B
VOH5
VOL5
IOH5
VO=VDD*(0.5)
IOH = -12 mA
IOL = 9 mA
20
60
2.4
V
0.4
-22
V
mA
mA
VOH = 2.0 V
VOL = 0.8 V
IOL5
16
45
1
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.8
1.8
53
4.0
4.0
55
ns
1
tf5
ns
%
1
dt5
VT = 1.5 V
VT = 1.5 V
24 48 MHz
1
150
500
ps
tjcyc-cyc5
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-168
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
10
ICS9248-168
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) on the ICS9248-
168 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Fig. 1
Third party brands and names are the property of their respective owners.
11
ICS9248-168
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. CPU_STOP# is considered
to be a don't care during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state
as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may
require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-168 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
12
ICS9248-168
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-168. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-168.
3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
13
ICS9248-168
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEEVARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEEVARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
9.652
28
34
48
56
64
9.398
11.303
15.748
18.288
20.828
.370
.445
.620
.720
.820
.380
.455
.630
.730
.830
11.557
16.002
18.542
21.082
Ordering Information
ICS9248yF-168-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
14
information being relied upon by the customer is current and accurate.
相关型号：
©2020 ICPDF网 联系我们和版权申明