ICS9248YF-112-T [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩; 频率发生器和缓冲器集成的赛扬和PII / III⑩
| 型号： | ICS9248YF-112-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
| 文件： | 总12页 (文件大小：385K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS9248-112
Integrated
Circuit
Systems, Inc.
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/III™
Recommended Application:
810/810E type chipset.
Pin Configuration
Output Features:
•
•
2- CPUs @2.5V, up to 150MHz.
9 - SDRAM @ 3.3V, up to150MHz including
1 free running
•
•
•
•
•
•
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz
2 - 3V66MHz @ 3.3V, 2X PCI MHz
1- 48MHz, @3.3V fixed.
1- 24MHz, @3.3V fixed
1- REF @3.3V, 14.318MHz.
Features:
•
•
•
Up to 166MHz frequency support
Support FS0-FS3 strapping status bit for I2C read back.
Support power management: Through Power down
Mode from I2C programming.
•
•
Spread spectrum for EMI control ( ± 0.25% center).
Spread can be enabled or disabled to all 32 frequencies
throuth I2C.
•
Uses external 14.318MHz crystal
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
1 These are double strength.
Skew Specifications:
•
•
•
•
•
•
CPU – CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 – 3V66: <175ps
PCI – PCI: <500ps
CPU-SDRAM<500ps
For group skew specifications, please refer to group
timing relationship.
Block Diagram
Functionality
IOAPIC
1=PCICLK/2 0=PCICLK
IOAPIC
CPU
(MHz)
SDRAM
(MHz)
3V66
(MHz)
PCICLK
(MHz)
FS3 FS2 FS1 FS0
(MHz)
16.70
17.00
16.72
17.17
16.72
18.13
16.72
17.17
17.50
23.33
19.67
20.67
22.28
22.83
18.75
18.13
(MHz)
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.80 100.20 66.80
68.00 102.00 68.00
100.30 100.30 66.87
103.00 103.00 68.67
133.73 100.30 66.87
145.00 108.75 72.50
133.73 100.30 66.87
137.33 103.00 68.67
140.00 105.00 70.00
140.00 140.00 93.33
118.00 118.00 78.67
124.00 124.00 82.67
133.70 133.70 89.13
137.00 137.00 91.33
150.00 112.50 75.00
72.50 108.75 72.50
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
Additional frequencies selectable through I2C programming.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
9248- 112 Rev A 2/7/00
Third party brands and names are the property of their respective owners.
ICS9248-112
Preliminary Product Preview
General Description
Power Groups
The ICS9248-112 is the single chip clock solution for designs
using the 810/810E style chipset. It provides all necessary
clock signals for such a system.
GNDREF, VDDREF=REF0, X1, X2
GNDPCI, VDDPCI=PCICLK[9:0]
GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F,
supply for PLL core
Spread spectrum may be enabled through I2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-112
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
GND3V66,VDD3V66=3V66
GND48 , VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU, VDDLCPU=CPUCLK[1:0]
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection.
Pin Configuration
PIN
PIN NAME
REF1
TYPE
DESCRIPTION
NUMBER
1
OUT 3.3V, 14.318MHz reference clock output.
PWR 3.3V power supply
2, 9, 10, 18,
25, 29, 37
VDD
X1
Crystal input, has internal load cap (33pF) and feedback
3
4
IN
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
X2
OUT
cap (33pF)
5, 6, 14, 21, 28,
33, 41
GND
PWR Ground pins for 3.3V supply
7, 8
3V66 (1:0)
PCICLK01
OUT 3.3V clock outputs for HUB running at 2XPCI MHz
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
11
FS0
PCICLK11
IN
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
IN Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
12
FS1
13, 15, 16,
17, 19, 20
PCICLK (2:7)
OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS
Asynchronous active low input pin used to power down the device into
a low power state. The internal clocks are disabled and the VCO and
22
PD#
IN
the crystal are stopped. The latency of the power down will not be
greater than 3ms.
23
24
SCLK
SDATA
48MHz
FS3
IN
IN
Clock input of I2C input
Data input for I2C serial input.
OUT 3.3V Fixed 48MHz clock output for USB
26
IN
IN
Logic input frequency select bit. Input latched at power on.
Logic input frequency select bit. Input latched at power on.
FS2
27
30
24MHz
OUT 3.3V fixed 24MHz output
OUT 3.3V free running SDRAM not affected by I2C
SDRAM_F
40, 39, 38, 36,
35, 34, 32, 31
SDRAM (7:0)
OUT 3.3V outputs
42
GNDL
PWR Ground for 2.5V power supply for CPU & APIC
OUT 2.5V Host bus clock output.
43, 44
CPUCLK (1:0)
45, 47
46
VDDL
IOAPIC
REF01
PWR 2.5V power supply for CPU, IOAPIC
OUT 2.5V clock output
OUT 3.3V, 14.318MHz reference clock output.
48
"If FREQ_APIC = 0, APIC Clock = PCICLK
If FREQ_APIC = 1, APIC Clock = PCICLK/2 (default)"
FREQ_IOAPIC
IN
Third party brands and names are the property of their respective owners.
2
ICS9248-112
Preliminary Product Preview
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
3
ICS9248-112
Preliminary Product Preview
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
FREQ_IOAPIC
(MHz)
CPUCLK SDRAM
3V66
(MHz)
PCICLK
(MHz)
Bit (2, 7:4)
Spread Precentage
(MHz)
(MHz)
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.80
68.00
100.20
102.00
100.30
103.00
100.30
108.75
100.30
103.00
105.00
140.00
118.00
124.00
133.70
137.00
112.50
108.75
112.50
83.00
66.80
68.00
66.87
68.67
66.87
72.50
66.87
68.67
70.00
93.33
78.67
82.67
89.13
91.33
75.00
72.50
75.00
27.67
73.33
80.00
83.33
69.25
70.00
76.67
96.67
66.50
100.00
66.50
103.33
111.00
76.67
66.50
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
37.50
13.83
36.67
40.00
41.67
34.63
35.00
38.33
48.33
33.25
50.00
33.25
51.67
55.50
38.33
33.25
16.70
17.00
16.72
17.17
16.72
18.13
16.72
17.17
17.50
23.33
19.67
20.67
22.28
22.83
18.75
18.13
18.75
6.92
33.40
34.00
33.43
34.33
33.43
36.25
33.43
34.33
35.00
46.67
39.33
41.33
44.57
45.67
37.50
36.25
37.50
13.83
36.67
40.00
41.67
34.63
35.00
38.33
48.33
33.25
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
100.30
103.00
133.73
145.00
133.73
137.33
140.00
140.00
118.00
124.00
133.70
137.00
150.00
72.50
XXX
Note1
Bit 2,
Bit 7:4
75.00
83.00
110.00
120.00
125.00
69.25
110.00
120.00
125.00
103.88
105.00
115.00
145.00
99.75
18.33
20.00
20.83
17.31
17.50
19.17
24.17
16.63
25.00
16.63
25.83
27.75
19.17
16.63
70.00
76.67
145.00
66.50
150.00
99.75
150.00
99.75
50.00 +/- 0.25% Center*
33.25 +/- 0.25% Center*
155.00
166.50
153.33
133.00
155.00
166.50
115.00
99.75
51.67
55.50
38.33
+/- 0.25% Center
+/- 0.25% Center
+/- 0.25% Center
33.25 +/- 0.25% Center*
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled ± 0.25% Center Spread
0 - Running
Bit 3
Bit 1
Bit 0
0
1
0
1- Tristate all outputs
Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
* These frequencies with spread enabled are equal to original Intel defined frequency with -0.5% down spread.
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
4
ICS9248-112
Preliminary Product Preview
Byte 1: Control Register
(1= enable, 0 = disable)
Byte 2: SDRAM, Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
SDRAM7
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
31
32
34
35
36
38
39
40
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
X
X
X
1
FS3#
FS0#
FS2#
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
-
27
-
24MHz
1
(Reserved)
48MHz
26
-
1
1
(Reserved)
SDRAM_F
30
1
Byte 3: PCI, Control Register
(1= enable, 0 = disable)
Byte 4: Control Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
PCICLK7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
8
0
1
(Reserved)
3V66_1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
17
16
15
13
12
11
1
1
1
1
1
1
1
1
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
7
1
3V66_0
-
X
1
FREQ_IOAPIC#
IOAPIC
46
-
X
1
FS1#
43
44
CPUCLK1
CPUCLK0
1
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
Note: Dont write into this register, writing into this
register can cause malfunction
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
5
ICS9248-112
Preliminary Product Preview
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248-
112 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
6
ICS9248-112
Preliminary Product Preview
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. The REF and 48MHz clocks
are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding
the REF clock outputs in the LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
7
ICS9248-112
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Timing Relationship Table
Group
CPU 66MHz
CPU 100MHz
Offset Tolerance
5.0ns 500ps
CPU 133MHz
Offset Tolerance
0.0ns 500ps
Offset
Tolerance
500ps
CPU to SDRAM
CPU to 3V66
2.5ns
7.5ns
0.0ns
500ps
5.0ns
0.0ns
500ps
500ps
0.0ns
0.0ns
500ps
500ps
SDRAM to 3V66
500ps
3V66 to PCI
PCI to PCI
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
1.5-3.5ns
0.0ns
500ps
1.0ns
N/A
USB & DOT
Asynch
Asynch
Asynch
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
-5
0.8
5
A
µ
IIH
VIN = VDD
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66M
-5
2.0
-100
60
A
µ
IIL2
-200
IDD3.3OP
100
600
mA
Supply Current
Power Down
A
µ
IDD3.3PD CL = 0 pF; With input address to Vdd or GND
400
Supply Current
Input frequency
Pin Inductance
Fi
VDD = 3.3 V;
14.318
MHz
nH
pF
Lpin
CIN
7
5
Input Capacitance1
Logic Inputs
Cout
CINX
Ttrans
Ts
Out put pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
Delay
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
mS
mS
mS
nS
3
TSTAB
3
t
PZH,tPZH output enable delay (all outputs)
1
1
10
10
tPLZ,tPZH
output disable delay (all outputs)
nS
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-112
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
13.5
13.5
2
TYP MAX UNITS
1
RDSP2B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
45
45
Ω
Ω
1
RDSN2B
VOH2B
VOL2B
IOH2B
IOL2B
V
IOL = 1 mA
0.4
-27
30
V
VOH @MIN= 1.0V , VOH@ MAX= 2.375V
VOL @MIN= 1.2V , VOL@ MAX= 0.3V
VOL = 0.4 V, VOH = 2.0 V
VOH = 0.4 V, VOL = 2.0 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
%
1
tr2B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf2B
1
Duty Cycle
dt2B
50
1
Skew
tsk2B
VT = 1.25 V
250
250
ps
ps
1
tjcyc-cyc
VT = 1.25 V
Jitter
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
175
500
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-112
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
1
RDSP4B
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -5.5 mA
IOL = 9.0 mA
9
9
2
30
30
Ω
Ω
1
RDSN4B
VOH4\B
VOL4B
IOH4B
V
0.4
-27
30
V
VOH@ min = 1.0 V, VOH@ MAX = 2.375 V
VOL@ MIN = 1.2 V, VOL@ MAX= 0.3 V
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
-27
27
mA
mA
ns
ns
%
IOL4B
1
tr4B
0.4
0.4
45
1.6
1.6
55
1
Fall Time
tf4B
1
Duty Cycle
dt4B
Jitter
tjcyc-cyc
VT = 1.25 V
500
250
ps
ps
1
tsk4
Skew
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP MAX UNITS
1
RDSP3
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
24
24
Ω
Ω
1
RDSN3
10
VOH3
VOL3
IOH3
IOL3
2.4
V
IOL = 1 mA
0.4
-46
53
V
VOH @MIN= 2.0 V, VOH@ MAX=3.135 V
VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-54
54
mA
mA
ns
ns
%
1
Tr3
0.4
0.4
45
1.6
1.6
55
1
Fall Time
Tf3
1
Duty Cycle
Dt3
1
Skew
Tsk3
VT = 1.5 V
250
250
ps
ps
Jitter
tjcyc-cyc VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
10
ICS9248-112
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
12
TYP MAX UNITS
1
RDSP1
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = -1 mA
55
55
Ω
Ω
1
RDSN1
12
VOH1
VOL1
IOH1
IOL1
2.4
V
IOL = 1 mA
0.55
-33
38
V
VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33
mA
mA
ns
ns
%
VOL@ MIN = 1.95 V, VOL@ MAX= 0.4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
30
0.5
0.5
45
1
tr1
2
1
Fall Time
tf1
2
1
Duty Cycle
dt1
55
1
Skew
tsk1
VT = 1.5 V
500
500
ps
ps
Jitter
tjcyc-cyc
VT = 1.5 V
1Guarenteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
20
TYP MAX UNITS
1
RDSP5
VO = VDD*(0.5)
VO = VDD*(0.5)
IOH = 1 mA
60
60
Ω
Ω
1
RDSN5
20
VOH5
VOL5
IOH5
IOL5
2.4
V
IOL = -1 mA
0.4
-23
27
V
VOH @MIN=1 V, VOH@MAX= 3.135 V
VOL@MIN=1.95 V, VOL@MIN=0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
mA
mA
nS
nS
%
1
tr5
1.8
1.7
4
1
Fall Time
tf5
4
1
Duty Cycle
dt5
45
55
1
Jitter
tjcyc-cyc
VT = 1.5 V; Fixed Clocks
VT = 1.5 V; Ref Clocks
VT = 1.5 V
500
1000
250
pS
pS
pS
1
tjcyc-cyc
Skew
Tsk
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ICS9248-112
Preliminary Product Preview
Pin 1
.093
DIA. PIN (Optional)
D/2
Index
Area
E/2
PARTING LINE
H
L
DETAIL “A”
TOP VIEW
BOTTOM VIEW
-e-
B
A2
c
A
C
.004
SEE
DETAIL “A”
-E-
SEATING
PLANE
-D-
-C-
END VIEW
A1
SIDE VIEW
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.087
.008
.005
NOM.
.102
.012
.090
MAX.
.110
.016
.094
.0135
.010
MIN.
.620
NOM.
.625
MAX.
.630
A
A1
A2
B
AC
48
-
-
c
D
E
e
H
h
L
See Variations
.295
0.025 BSC
.291
.299
“For current dimensional specifications, see JEDEC 95.”
Dimensions in inches
.395
.010
.020
-
.420
.016
.040
.013
-
N
See Variations
0°
-
8°
48 Pin 300 mil SSOP Package
Ordering Information
ICS9248yF-112-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
Third party brands and names are the property of their respective owners.
12
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