ICS9248YF-114-T [ICSI]
AMD - K7⑩ System Clock Chip; AMD - K7 ™系统时钟芯片
| 型号： | ICS9248YF-114-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | AMD - K7⑩ System Clock Chip |
| 文件： | 总14页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-114
AMD - K7™ System Clock Chip
Recommended Application:
VIA K7 style chipset
Output Features:
Pin Configuration
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD1
REF0/CPU_STOP#*
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
REF1/FS2*
GND
CPUCLKT1
•
•
•
•
•
•
•
1 - Differential pair open drain CPU clocks
1 - Single-ended open drain CPU clock
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V fixed.
X1
X2
VDD2
GND
CPUCLKC0
CPUCLKT0
VDDL
PD#*
SDRAM_OUT
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
*MODE/PCICLK_F
*FS3/PCICLK0
GND
1 - 24/48MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
*SEL24_48#/PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
Features:
•
•
Up to 155MHz frequency support
BUFFER IN
Support power management: CPU stop and Power down
Mode from I2C programming.
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
•
Spread spectrum for EMI control (0 to -0.5% down
spread, 0.25% center spreadꢀ.
•
Uses external 14.318MHz crystal
Skew Specifications:
SDATA
SCLK
48MHz/FS0*
24/48MHz/FS1*
•
•
•
CPUT – CPUC: <200ps
PCI – PCI: <500ps
CPU – PCI: <500ps
48-Pin 300mil SSOP
*
Internal Pull-up Resistor of 120K to VDD
Functionality
Block Diagram
CPU
PCICLK
(MHz)
41.33
37.50
41.65
33.40
34.33
37.33
44.43
33.33
40.00
38.33
36.67
35.00
35.00
37.50
31.00
33.33
PLL2
48MHz
FS3
FS2
FS1
FS0
(MHz)
124.00
75.00
83.30
66.80
103.00
112.00
133.30
100.00
120.00
115.00
110.00
105.00
140.00
150.00
124.00
133.30
24_48MHz
/ 2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X1
X2
XTAL
OSC
REF (1:0)
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
CPUCLKC0
CPUCLKT (1:0)
SEL24_48#
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
Control
Logic
SDATA
SCLK
FS (3:0)
Config.
Reg.
SDRAM
DRIVER
SDRAM (11:0)
SDRAM_OUT
PD#
CPU_STOP#
BUFFER IN
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-114 Rev C 01/24/01
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9248-114
Pin Descriptions
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDD1
PWR REF, XTAL power supply, nominal 3.3V
14.318 Mhz reference clock.This REF output is the STRONGER
buffer for ISA BUS loads
REF0
OUT
2
This asynchronous input halts CPUCLKT, CPUCLKC & SDRAM at
logic "0" level when driven low.
CPU_STOP#1, 2
IN
3,9,16,22,
33,39,45, 47
GND
X1
PWR Ground
Crystal input, has internal load cap (36pF) and feedback
4
IN
resistor from X2
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
5
X2
OUT
6,14
VDD2
PCICLK_F
PWR Supply for PCICLK_F and PCICLK, nominal 3.3V
Free running PCI clock not affected by PCI_STOP# for power
management.
OUT
7
Pin 2 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
MODE1, 2
IN
FS31, 2
PCICLK0
SEL24_48#1, 2
PCICLK1
PCICLK (4:2)
BUFFER IN
IN
Frequency select pin. Latched Input. Internal Pull-down to GND
8
OUT PCI clock output
IN
Logic input to select 24 or 48MHz for pin 25 output
10
OUT PCI clock output.
OUT PCI clock outputs.
13, 12, 11
15
IN
Input to Fanout Buffers for SDRAM outputs.
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
SDRAM (11:0)
OUT
19,30,36
23
VDD3
PWR Supply for SDRAM nominal 3.3V.
SDATA
SCLK
IN
IN
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
24
24_48MHz
FS11, 2
OUT 24MHz/48MHz clock output
IN Frequency select pin. Latched Input.
OUT 48MHz output clock
25
26
48MHz
FS01, 2
IN
Frequency select pin. Latched Input
27
40
41
42
VDD4
PWR Power for 24 & 48MHz output buffers and fixed PLL core.
OUT Reference clock for SDRAM zero delay buffer
SDRAM_OUT
PD#1, 2
IN
Powers down chip, active low
VDD
PWR Supply for core 3.3V
"True" clocks of differential pair CPU outputs. These open drain
outputs need an external 1.5V pull-up.
"Complementory" clocks of differential pair CPU outputs. These
open drain outputs need an external 1.5V pull-up.
46, 43
44
CPUCLKT (1:0)
CPUCLKC0
OUT
OUT
REF1
FS21, 2
OUT 14.318 MHz reference clock.
IN Frequency select pin. Latched Input
48
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-114
General Description
The ICS9248-114 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks
required for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-114
employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature
variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Mode Pin - Power Management Input Control
MODE, Pin 7
Pin 2
(Latched Input)
CPU_STOP#
0
(Input)
REF0
(Output)
1
Third party brands and names are the property of their respective owners.
3
ICS9248-114
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
CPUCLK
PWD
PCICLK
(MHz)
41.33
37.50
41.65
33.40
34.33
37.33
44.43
33.33
40.00
38.33
36.67
35.00
35.00
37.50
31.00
33.33
30.00
30.83
31.67
32.50
33.83
42.33
34.13
33.33
40.00
39.17
40.67
35.83
36.25
38.75
32.50
33.32
Spread
Precentage
Bit (2, 7, 6, 5, 4)
(MHz)
124.00
75.00
83.30
66.80
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
-0.5% Down Spread
-0.5% Down Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
0.25% Center Spread
-0.5% Down Spread
103.00
112.00
133.30
100.00
120.00
115.00
110.00
105.00
140.00
150.00
124.00
133.30
90.00
00100
Note1
Bit 2,
Bit 7:4
92.50
95.00
97.50
101.50
127.00
136.50
100.00
120.00
117.50
122.00
107.50
145.00
155.00
130.00
133.30
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 2, 7:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
1- Tristate all outputs
Bit 3
Bit 1
Bit 0
0
1
0
Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
The I2C readback of the power up default could indicate the manufacture ID in bits 2, 7:4 as shown.
Third party brands and names are the property of their respective owners.
4
ICS9248-114
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
-
-
X
1
FS2#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
X
1
1
1
1
1
1
1
FS0#
(Reserved)
(Reserved)
FS3#
7
PCICLK_F
(Reserved)
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
-
1
-
-
40
-
X
1
13
12
11
10
8
SDRAM_OUT
(SEL24_48#)#
X
CPUCLK0 enable (both
differential pair. "True" and
Complimentary")
Bit 1
Bit 0
43,44
46
1
1
CPUCLKT enable
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: SDRAM , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
28
29
31
32
34
35
37
38
1
1
1
1
1
1
1
1
SDRAM 7
SDRAM 6
SDRAM 5
SDRAM 4
SDRAM 3
SDRAM 2
SDRAM 1
SDRAM 0
-
1
1
1
1
1
1
1
1
-
(Reserved)
48MHz
26
25
17
18
20
21
24_48MHz
SDRAM 11
SDRAM 10
SDRAM 9
SDRAM 8
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
(Reserved)
(Reserved)
MODE#
FS1#
-
1
-
X
X
1
-
-
(Reserved)
REF1
48
2
1
1
REF0
Note: Don’t write into this register, writing into this
register can cause malfunction
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
5
ICS9248-114
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
IIH
VIN = VDD
µ
A
IIL1
VIN = 0V; Inputs with no pull-up resistors
-5
µ
A
IIL2
VIN = 0V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66 MHz
-200
µ
180
180
180
600
16
mA
mA
mA
IDD3.3OP66
IDD3.3OP100
IDD3.3OP133
IDD3.3PD
Fi
Operating Supply
Current
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Select @ 133 MHz
CL = 0 pF; Input address to VDD or GND
Powerdown Current
A
µ
MHz
Input Frequency
VDD = 3.3 V
Logic Inputs
X1 & X2 pins
12
27
14.318
CIN
5
pF
Input Capacitance1
Clk Stabilization1
CINX
45
pF
TSTAB
From VDD = 3.3 V to 1% target frequency
3
ms
ps
ps
TCPU-PCI
TCPU-PCI
TCPU-PCI
CPU VT = VX, PCI VT = 1.5V, CPU=66MHz -100
CPU VT = VX, PCI VT = 1.5V, CPU=100MHz -100
-5509
-2946
100
100
Skew1
CPU VT = VX, PCI VT = 1.5V, CPU=133MHz
-100
-1637
100
ps
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-114
Electrical Characteristics - CPUCLK (Open Drain)
TA = 0 - 70º C; VDD = 3.3 V +/-5%; CL = 20 pF (unless otherwise stated).
PARAMETER
Output Impedance
Output High Voltage
Output Low Voltage
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
60
UNITS
1
ZO
VO = VX
Ω
VOH2B
VOL2B
IOL2B
Termination to Vpull-up (external)
Termination to Vpull-up (external)
VOL = 0.3 V
1
1.2
V
0.4
V
18
mA
ns
1
VOL = 0.3 V, VOH = 1.2 V
VOH = 1.2 V, VOL = 0.3 V
VT = VX
1.93
0.81
49.3
2.6
2.6
55
tr2B
1
Fall Time
ns
tf2B
1
Duty Cycle
Differential
Voltage-AC
Differential
Voltage-DC
Differential
Crossover Voltage
Skew
45
%
dt2B
1
Note 2
Note 2
Note 3
0.4
1.18 Vpull-up (external) + 0.6
Vpull-up (external) + 0.6
V
V
VDIF
1
0.2
VDIF
1
550
958
1100
mV
VX
1
VT = 1.5 V
VT = VX
94
200
250
ps
ps
tsk2B
1
158
tjcyc-cyc2B
Jitter, Cycle-to-cycle
Notes:
1 - Guaranteed by design, not 100% tested in production.
2 - VDIF specifies the minimum input differential voltages (VTR-VCP) required for switching, where VTR is the "true"
input level and VCP is the "complement" input level.
3 - Vpull-up(external) = 1.5V, Min = (Vpull-up(external)/2) - 150mV; Max = (Vpull-up(external)/2) + 150mV
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH3
CONDITIONS
MIN
2.4
TYP
3
MAX UNITS
V
IOH = -28 mA
IOL = 20 mA
VOH = 2.0 V
VOL = 0.8 V
VOL3
IOH3
0.18
-110
86
0.4
-40
V
mA
mA
IOL3
41
45
tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.42
1.78
56.7
225
2
2
ns
ns
%
ps
Fall Time1
Duty Cycle1
Skew window1
tf3
dt3
55
250
tsk3
VT = 1.5 V
Propagation Time1
VT = 1.5 V
Tprop
3.41
ns
(Buffer In to Output)
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-114
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.15
0.13
-97
MAX UNITS
V
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
IOH1
0.4
-40
V
mA
mA
IOL1
41
69
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.69
1.75
51.7
400
2.0
2.0
55
ns
ns
%
ps
ps
Fall Time1
Duty Cycle1
Skew window1
tf1
dt1
45
tsk1
VT = 1.5 V
500
500
1
Jitter,Cycle-to-Cycle
tjcyc-cyc1
VT = 1.5 V
-500
135
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - PCICLK_F
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.15
0.13
-97
MAX UNITS
V
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
IOH1
0.4
-40
V
mA
mA
IOL1
41
69
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.90
1.79
49.9
400
2.0
2.0
55
ns
ns
%
ps
ps
Fall Time1
Duty Cycle1
Skew window1
tf1
dt1
45
tsk1
VT = 1.5 V
500
500
1
Jitter,Cycle-to-Cycle
tjcyc-cyc1
VT = 1.5 V
-500
110
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-114
Electrical Characteristics - REF, 48MHz, 24MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
3.03
0.23
-50
MAX UNITS
V
IOH = -16 mA
IOL = 9 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
IOH5
0.4
-22
V
mA
mA
IOL5
16
40
tr5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.47
1.98
54.4
552
4.0
4.0
ns
ns
%
ps
ps
Fall Time1
tf5
Duty Cycle1
dt5
45
-1
55
1
Jitter, Cycle-to-Cycle
tjcyc-cyc5, Ref
VT = 1.5 V
1000
500
1
Jitter, Cycle-to-Cycle
tjcyc-cyc5, Fixed
VT = 1.5 V
421
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-114
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 5
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
10
ICS9248-114
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) on the ICS9248-
114 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
11
ICS9248-114
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-114. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PD# (High)
CPUCLKT (1:0)
CPUCLKC0
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-114.
3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
12
ICS9248-114
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and
CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to
be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock
outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLKT
CPUCLKC
PCICLK
VCO
Crystal
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-114 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
13
ICS9248-114
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.620
MAX
.630
48
15.748
16.002
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
Ordering Information
ICS9248yF-114-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
14
information being relied upon by the customer is current and accurate.
相关型号：
©2020 ICPDF网 联系我们和版权申明