ICS9248YF-126-T [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ & K6; 频率发生器和缓冲器集成的赛扬和PII / III⑩ ＆ K6
| 型号： | ICS9248YF-126-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ & K6 |
| 文件： | 总12页 (文件大小：472K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-126
Frequency Generator & Integrated Buffers for Celeron & PII/III™ & K6
Recommended Application:
Pin Configuration
Motherboard Single chip clock solution for Pentium II/III and
K6 processors, using SIS540/SIS630 style chipset"
Output Features:
VDDREF
*1REF0/FS3
GND
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1
VDDLCPU
CPUCLK0
CPUCLK1
GND
CPUCLK2
VDDSDR
SDRAM13
SDRAM12
GND
SDRAM11
SDRAM10
VDDSDR
SDRAM9
SDRAM8
GNDSDR
SDRAM7
SDRAM6
VDDSDR
SDRAM5
SDRAM4
VDDSDR
48MHz/FS0*1
24_48MHz/CPU2.5_3.3#*
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X1
X2
•
•
•
•
•
3- CPUs @ 2.5/3.3V, up to 166MHz.
14 - SDRAM @ 3.3V
VDDPCI
*PCICLK0/FS1
*PCICLK1/FS2
PCICLK2
GND
7- PCI @3.3V,
PCICLK3
PCICLK4
PCICLK5
PCICLK6
VDDSDR
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
1- 48MHz, @3.3V fixed.
1- 24/48MHz, @3.3V selectable by I2C
(Default is 24MHz).
•
2- REF @3.3V, 14.318MHz.
Features:
•
•
•
Up to 166MHz frequency support
Support FS0-FS3 trapping status bit for I2C read back.
SDATA
SCLK
Support power management: CPU, PCI, SDRAM stop
and Power down Mode form I2C programming.
•
•
Spread spectrum for EMI control (0 to -0.5%, ± 0.25%).
48-Pin 300mil SSOP
* These inputs have a 120K pull down to GND"
1 These are double strength"
FS0, FS1, FS3 must have a internal 120K pull-Down
to GND.
•
Uses external 14.318MHz crystal
Skew Specifications:
•
•
•
•
•
CPU - CPU: < 175ps
SDRAM - SDRAM < 500ps
PCI - PCI: < 500ps
CPU - SDRAM: < 500ps
CPU - PCI: 1 - 4ns
Functionality
Block Diagram
CPU
(MHz)
66.6
100.0
150.0
133.3
66.8
100.0
100.0
133.3
66.8
97.0
70.0
95.0
95.0
112.0
97.0
96.2
SDRAM PCICLK
FS3 FS2 FS1 FS0
PLL2
48MHz
(MHz)
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.8
(MHz)
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.3
35.0
31.7
31.7
37.3
32.2
32.1
24_48MHz
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
/ 2
X1
X2
XTAL
OSC
REF (1:0)
2
PLL1
Spread
Spectrum
CPU
CLOCK
DIVDER
CPUCLK (2:0)
SDRAM (13:0)
3
SDRAM
CLOCK
DIVDER
4
LATCH
14
FS(3:0)
97.0
105.0
95.0
PCI
CLOCK
DIVDER
PCICLK (6:0)
Control
Logic
7
126.7
112.0
129.3
96.2
CPU2.5_3.3#
Config.
Reg.
SDATA
SCLK
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-126 Rev C 9/6/00
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9248-126
General Description
Power Groups
VDDREF = REF, X1, X2
The ICS9248-126 is the single chip clock solution for
Desktop/Notebook designs using the SIS 540/630 style
chipset" It provides all necessary clock signals for such a
system"
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM, supply for PLL core,
VDD48 = 48MHz, 24MHz
VDDLCPU = CPUCLKs
Spread spectrum may be enabled through I2C programming"
Spread spectrum typically reduces system EMI by 8dB to
10dB" This simplifies EMI qualification without resorting to
board design iterations or costly shielding" The ICS9248-126
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations"
Serial programming I2C interface allows changing functions,
stop clock programming and frequency selection"
Pin Configuration
PIN NUMBER
1, 6, 15, 19, 27, 30,
36, 42
PIN NAME
TYPE
DESCRIPTION
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
14.318 MHz reference clock.
VDD
PWR
REF0
FS3
OUT
IN
2
Frequency select pin.
3, 10, 16, 22,
33, 39, 44
GND
PWR
Ground pin for 3V outputs.
4
5
X1
X2
IN
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
OUT
IN
FS1
7
PCICLK0
FS2
OUT
IN
PCI clock outputs.
Frequency select pin.
8
PCICLK1
PCICLK (6:2)
OUT
OUT
PCI clock outputs.
14, 13, 12, 11, 9
PCI clock outputs.
41, 40, 38, 37, 35,
34, 32, 31, 29, 28,
21, 20, 18, 17
SDRAM (13:0)
OUT
SDRAM clock outputs
Data pin for I2C circuitry 5V tolerant
Clock input of I2C input, 5V tolerant input
Voltage select 2.5V when high - 3.3V when low
Clock output for super I/O/USB default is 24MHz
Frequency select pin.
23
24
SDATA
SCLK
I/O
IN
CPU2.5_3.3#
24_48MHz
FS0
IN
25
26
OUT
IN
48MHz
OUT
OUT
PWR
OUT
48MHz output clock
43, 45, 46
CPUCLK (2:0)
VDDLCPU
REF1
CPU clock outputs.
47
48
Power pin for the CPUCLKs. 2.5V
14.318 MHz reference clock.
Third party brands and names are the property of their respective owners.
2
ICS9248-126
General I2C serial interface information
The information in this section assumes familiarity with I2C programming"
For more information, contact ICS for an I2C programming application note"
How to Write:
Controller (host) sends a start bitꢀ
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bitꢀ
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a timeꢀ
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Dummy Byte Count
Byte 0
Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1"
The ICS clock generator is a slave/receiver, I2C component" It can read back the data stored in the latches for
verification" Read-Back will support Intel PIIX4 "Block-Read" protocol"
2"
3"
4"
5"
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3"3V logic levels"
The data byte format is 8 bit bytes"
To simplify the clock generator I2C interface, the protocol is set to use only ꢀBlock-Writesꢀ from the controller" The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred" The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes" The data is loaded until a Stop sequence is issued"
6"
At power-on, all registers are set to a default condition, as shown"
Third party brands and names are the property of their respective owners.
3
ICS9248-126
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
CPU
PWD
Bit7 Bit2 Bit6 Bit5 Bit4
SDRAM
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.8
PCI
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.3
35.0
31.7
31.7
37.3
32.3
32.1
33.4
33.4
27.7
33.4
37.5
31.3
35.0
33.4
36.8
38.3
30.0
34.5
35.0
36.3
36.9
26.7
SS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.6
100.0
150.0
133.3
66.8
0 to-0.5%
0 to-0.5%
±0.25%
0 to-0.5%
0 to-0.5%
0 to-0.5%
±0.25%
0 to-0.5%
±0.25%
0 to-0.5%
±0.25%
±0.25%
±0.25%
±0.25%
0 to-0.5%
0 to-0.5%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
±0.25%
100.0
100.0
133.3
66.8
97.0
97.0
70.0
105.0
95.0
95.0
95.0
126.7
112.0
129.3
96.2
112.0
97.0
00010
Note1
96.2
Bit 7, 2,
Bit 6:4
66.8
100.2
100.2
110.7
133.6
100.0
125.0
140.0
133.6
147.0
153.3
120.0
138.0
140.0
145.0
147.5
160.0
100.2
166.0
100.2
75.0
83.3
105.0
133.6
110.3
115.0
120.0
138.0
140.0
145.0
147.5
160.0
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 7, 2, 6:4
0 - Normal
1 - Spread Spectrum Enabled
0 - Running
Bit 3
Bit 1
Bit 0
0
1
0
1- Tristate all outputs
Note1:
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3"
The I2C readback for Bits 7, 2, 6:4 indicate the revision code"
Note: PWD = Power-Up Default
I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
4
ICS9248-126
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
(CPU2.5_3.3#)
BIT PIN# PWD
DESCRIPTION
SEL24_48#
(48MHz when set to 0)
(24MHz when set to 1)
Reserved
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
1
1
1
1
1
1
1
1
Bit 7
-
1
14
13
12
11
9
PCICLK6 (Act/Inact)
PCICLK5 (Act/Inact)
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0 (Act/Inact)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
Reserved
-
Reserved
43
45
46
-
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
Reserved
8
7
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN# PWD
DESCRIPTION
SDRAM 7 (Act/Inact)
SDRAM 6 (Act/Inact)
SDRAM 5 (Act/Inact)
SDRAM 4 (Act/Inact)
SDRAM 3 (Act/Inact)
SDRAM 2 (Act/Inact)
SDRAM 1 (Act/Inact)
SDRAM 0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
25
26
41
40
38
37
35
34
1
1
1
1
1
1
1
1
24_48MHz
48MHz
32
31
29
28
21
20
18
17
1
1
1
1
1
1
1
1
SDRAM13
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
BIT PIN# PWD
DESCRIPTION
BIT PIN# PWD
DESCRIPTION
Reserved
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
-
-
-
-
-
-
-
-
0
0
0
0
0
1
1
0
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Reserved (Note)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
1
1
1
1
1
1
1
1
Reserved
FS3#
-
-
FS2#
-
FS1#
-
FS0#
48
2
REF1 (Act/Inact)
REF0 (Act/Inact)
Note: Dont write into this register, writing into this
register can cause malfunction
Notes:
1" Inactive means outputs are held LOW and are disabled
from switching"
2" Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions"
Third party brands and names are the property of their respective owners.
5
ICS9248-126
Absolute Maximum Ratings
Supply Voltage " " " " " " " " " " " " " " " " " " " " " " " " " " " " 5"5 V
Logic Inputs " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " GND 0"5 V to VDD +0"5 V
Ambient Operating Temperature " " " " " " " " " " " " " 0°C to +70°C
Case Temperature " " " " " " " " " " " " " " " " " " " " " " " " " " 115°C
Storage Temperature " " " " " " " " " " " " " " " " " " " " " " " 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device" These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied" Exposure to absolute maximum rating conditions for extended periods
may affect product reliability"
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Operating
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
0.8
V
V
VIL
VSS-0.3
IDD3.3OP66 CL = 0 pF; Select @ 66MHz
IDD3.3OP100 CL = 0 pF; Select @ 100MHz
IDD3.3OP133 CL = 0 pF; Select @ 133MHz
148
150
180
mA
mA
mA
MHz
pF
Supply Current
180
161
Input frequency
Input Capacitance1
Fi
VDD = 3.3 V;
11
27
14.318
16
5
CIN
Logic Inputs
CINX
Ttrans
X1 & X2 pins
36
45
3
pF
Transition Time1
Clk Stabilization1
Skew
To 1st crossing of target Freq.
ms
ms
ns
TSTAB
tCPU-PCI
From VDD = 3.3 V to 1% target Freq.
VT = 1.5 V
3
1
2.39
4
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Operating
SYMBOL
CONDITIONS
MIN
TYP
6.13
9.22
11.6
273
MAX UNITS
IDD2.5OP66 CL = 0 pF; Select @ 66.8 MHz
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz
IDD2.5OP133 CL = 0 pF; Select @ 133 MHz
tCPU-SDRAM VT = 1.5 V; VTL = 1.25 V
30
mA
mA
mA
ps
Supply Current
Skew1
500
4
tCPU-PCI
VT = 1.5 V; VTL = 1.25 V
1
2.25
ns
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-126
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP
36.5
29
MAX UNITS
1
RDSP2A
VO=VDD*(0.5)
VO=VDD*(0.5)
IOH = -20.0 mA
IOL = 12 mA
40
40
Ω
Ω
V
1
RDSN2A
10
VOH1a
VOL1a
IOH1a
IOL1a
2
2.85
0.31
-45
0.4
-19
V
VOH = 2 V
mA
mA
ns
VOL = 0.8 V
22
0.4
0.4
45
29
1
tr1a
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.24
1.6
2
1
Fall Time
tf1a
2
ns
1
Duty Cycle
dt1a
52.6
80.8
128
62
175
250
%
1
Skew
tsk1a
VT = 1.5 V
ps
1
tjcyc-cyc1a
VT = 1.5 V
Jitter, Cycle-to-cycle
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated)
PARAMETER
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
CONDITIONS
MIN
10
TYP
36.5
29
MAX UNITS
1
RDSP2A
VO=VDD*(0.5)
VO=VDD*(0.5)
IOH = -12.0 mA
IOL = 12 mA
40
40
Ω
Ω
V
1
RDSN2A
10
VOH1B
VOL1B
IOH1B
IOL1B
2
2.3
0.31
-39
0.4
-21
V
VOH = 1.7 V
mA
mA
ns
VOL = 0.7 V
19
45
26
1
tr1B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.5 V
1.03
1.26
51.7
66.1
170
124.5
1.6
1.6
55
1
Fall Time
tf1B
ns
1
Duty Cycle
dt1a
%
1
Skew
tsk1a
VT = 1.5 V
175
250
350
ps
1
Jitter, Cycle-to-cycle
tjcyc-cyc1B
VT = 1.25 V CPU, SDRAM Synchronous
VT = 1.25 V CPU, SDRAM Asynchronous
ps
1
tjcyc-cyc1B
ps
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-126
Electrical Characteristics - 48MHz, REF_0
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
21
MAX UNITS
1
Output Impedance
RDSP1
VO=VDD*(0.5)
55
55
Ω
Ω
V
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1 48MHz
Fall Time1 48MHz
Duty Cycle1 48MHz
Rise Time1 REF_0
Fall Time1 REF_0
RDSP1
VO=VDD*(0.5)
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
21
3.3
0.17
-62
57
VOH2
VOL2
IOH2
IOL2
2.4
0.4
-22
V
mA
mA
16
45
tr2
tf2
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.78
1.92
52
2
2
ns
ns
%
ns
ns
dt2
tr2
tf2
55
2
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
1.32
1.56
2
Duty Cycle1 REF_0
Jitter, 48MHz
Jitter, REF_0
dt2
tjcyc2
VT = 1.5 V
VT = 1.5 V
45
52.2
500.6
1243
55
%
ps
ps
700
VT = 1.5 V
tjcyc2
-350
1500
Electrical Characteristics - REF_1;24/48MHz
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 20 pF
PARAMETER
SYMBOL
CONDITIONS
VO=VDD*(0.5) Output P
MIN
TYP
MAX UNITS
1
Output Impedance
Output Impedance
RDSP5
20
20
42
43
60
60
Ω
Ω
RDSN5
1
VO=VDD*(0.5) Output N
IOH = -14 mA
IOL = 6mA
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1 24_48MHz
Fall Time1 24_48MHz
Duty Cycle1 24_48MHz
Rise Time1 REF_1
VOH4
VOL4
IOH4
IOL4
2.4
2.6
0.3
-26
22
V
0.4
-22
V
VOH = 2.0 V
mA
mA
VOL = 0.8 V
16
45
tr4
tf4
dt4
tr4
tf4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.75
1.88
52
4
4
ns
ns
%
ns
ns
55
4
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
2.22
2.43
Fall Time1 REF_1
4
Duty Cycle1 REF_1
Jitter, 24_48MHz
Jitter, REF_1
dt4
tjcyc4
VT = 1.5 V
VT = 1.5 V
45
-1
51.1
727
55
%
ps
ns
1000
1500
tjcyc4
VT = 1.5 V
1208
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-126
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; VDDL = 2.5 V +/-5%; CL = 30 pF
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
21
MAX UNITS
1
Output Impedance
RDSP1
VO=VDD*(0.5)
55
55
Ω
Ω
V
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSP1
VO=VDD*(0.5)
IOH = -18 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
12
21
3.3
0.17
-62
43
VOH2
VOL2
IOH2
IOL2
2.4
0.4
-33
V
mA
mA
38
tr2
tf2
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.62
1.81
49.8
2.2
2.2
55
ns
ns
%
Fall Time1
Duty Cycle1
dt2
45
Skew1
tsk2
tjcyc2
VT = 1.5 V
VT = 1.5 V
200
306
500
350
ps
ps
Jitter, Cycle-to-cycle
-350
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
1
Output Impedance
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
RDSP2A
VO=VDD*(0.5)
VO=VDD*(0.5)
IOH = -25 mA
IOL = 20 mA
VOH = 2.0 V
VOL = 0.8 V
10
10
17
18
20
20
Ω
Ω
1
RDSN2A
VOH3
VOL3
IOH3
IOL3
2.4
2.9
V
0.32
-73
50
0.4
-40
V
mA
mA
ns
41
0.4
0.4
47
1
Tr3
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.14
1.38
51.8
2
2
1
Fall Time
Tf3
ns
1
Duty Cycle
Dt3
57
250
%
Skew1
Tsk1
VT = 1.5 V
155.5
ps
(0-1,2,4,5,7,10,11)
Skew1
Tsk1
tjcyc
VT = 1.5 V
VT = 1.5 V
298.5
500
650
ps
ps
(0-6,6,8,9,12,13)
Jitter, Cycle-to-cycle
369.17
1Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-126
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is usedꢀ With no jumper is installed
the pin will be pulled highꢀ With the jumper in place the pin
will be pulled lowꢀ If programmability is not necessary, than
only a single resistor is necessaryꢀThe programming resistors
should be located close to the series termination resistor to
minimize the current loop areaꢀ It is more important to locate
the series termination resistor close to the driver than the
programming resistorꢀ
The I/O pins designated by (input/output) on the ICS9248-
126 serve as dual signal functions to the deviceꢀ During initial
power-up, they act as input pinsꢀ The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latchꢀ At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output functionꢀ
In this mode the pins produce the specified buffered clocks
to external loadsꢀ
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potentialꢀ A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating periodꢀ
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
10
ICS9248-126
Ferrite
Bead
Ferrite
Bead
General Layout Precautions:
1) Use a ground plane on the top routing
layer of the PCB in all areas not used
by traces"
C2
22µF/20V
Tantalum
C2
22µF/20V
Tantalum
VDD
VDD
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance"
1
2
48
2.5V Power Route
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
C3
3
1
C1
C1
Clock Load
4
C3
Notes:
5
1 All clock outputs should have
provisions for a 15pf capacitor
between the clock output and series
terminating resistor" Not shown in all
places to improve readability of
diagram"
2
6
7
8
9
3.3V Power Route
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2 Optional crystal load capacitors are
recommended" They should be
included in the layout but not
inserted unless needed"
3.3V Power Route
Component Values:
C1 : Crystal load values determined by user
C2 : 22µF/20V/D case/Tantalum
AVX TAJD226M020R
C3 : 15pF capacitor
FB = Fair-Rite products 2512066017X1
All unmarked capacitors are 0"01µF ceramic
= Routed Power
Connections to VDD:
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
Third party brands and names are the property of their respective owners.
11
ICS9248-126
SYMBOL
In Millimeters
In Inc hes
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
A
A1
b
2.413
0.203
0.203
0.127
.0135
.010
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
9.652
28
34
48
56
64
9.398
11.303
15.748
18.288
20.828
.370
.445
.620
.720
.820
.380
.455
.630
.730
.830
11.557
16.002
18.542
21.082
J E DE C MO- 118
6/ 1/ 00
DOC# 10-0034
REVB
Ordering Information
ICS9248yF-126-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
12
information being relied upon by the customer is current and accurate.
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