ICS9248YF-128 [ICSI]
Frequency Generator & Integrated Buffers; 频率发生器和集成缓冲器
| 型号： | ICS9248YF-128 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers |
| 文件： | 总16页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-128
Frequency Generator & Integrated Buffers
RecommendedApplication:
SIS 530/620 style chipset
Pin Configuration
VDDR/X
*MODE/REF0
GNDREF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC
Output Features:
•
•
•
•
•
•
•
- 3 CPU @ 2.5V/3.3V up to 133.3 MHz.
- 6 PCI @ 3.3V (including 1 free-running)
- 13 SDRAMs @ 3.3V up to 133.3MHz.
- 3 REF @ 3.3V, 14.318MHz
REF1/SD_SEL#*
GNDLAPIC
REF2/CPU2.5_3.3#*
CPUCLK1
VDDLCPU
CPUCLK2
CPUCLK3
GNDCPU
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GNDSDR
X1
X2
VDDPCI
*FS1/PCICLK_F
*FS2.PCICLK0
GNDPCI
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
SDRAM12
GNDSDR
- 1 clock @ 24/14.3 MHz selectable output for SIO
- 1 Fixed clock at 48MHz (3.3V)
- 1 IOAPIC @ 2.5V / 3.3V
Features:
*CPU_STOP# /SDRAM11
*PCI_STOP# /SDRAM10
VDDSD/C
*SDRAM_STOP# /SDRAM9
*PD# /SDRAM8
GNDFIX
•
•
Up to 133MHz frequency support
Support power management: CPU, PCI, SDRAM stop and
Power down Mode from I2C programming.
•
Spread spectrum for EMI control ( ± 0.25% center spread
& 0 to -0.5% down spread).
SDATA
SCLK
48MHz/FS0*
SIO/SEL24_14#MHz
*
•
•
Uses external 14.318MHz crystal
FS pins for frequency select
48-Pin SSOP
* Internal Pull-up Resistor of
120K to 3.3V on indicated inputs
Key Specifications:
•
•
CPU – CPU<175ps
SDRAM – SDRAM < 350ps
•
•
•
CPU–SDRAM < 500ps
CPU(early) – PCI : 1-4ns (typ. 2ns)
PCI – PCI <500ps
Block Diagram
Functionality
CPU SDRAM
PCI
MHZ
SD_SEL FS2 FS1 FS0
PLL2
48MHz
SIO
MHZ
MHZ
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
90.00
90.00
30.00
/2
66.70 100.05 33.35
SEL24_14#
95.00
63.33
31.66
33.33
30.00
37.33
31.00
32.33
33.35
30.00
33.32
31.66
X1
X2
XTAL
OSC
100.00 66.66
100.00 75.00
112.00 74.66
124.00 82.66
REF(2:0)
IOAPIC
3
PLL1
Spread
Spectrum
STOP
CPUCLK (3:1)
SDRAM (12:0)
3
13
5
97.00
66.70
75.00
83.30
95.00
97.00
66.70
75.00
83.30
95.00
CPU_STOP
MODE
FS(2:0)
CPU3.3#_2.5
SD_SEL#
LATCH
3
PCI
CLOCK
DIVDER
STOP
PCICLK (4:0)
PCICLK_F
5
POR
SDRAM_STOP#
CPU_STOP#
PCI_STOP#
PD#
PCI_STOP
100.00 100.00 33.33
112.00 112.00 37.33
124.00 124.00 31.00
133.30 133.30 33.33
Control
Logic
Config.
Reg.
SDATA
SCLK
Note: REF, IOAPIC = 14.318MHz
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-128 Rev B 11/16/00
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9248-128
Pin Descriptions
Pin number
Pin name
Type Description
1
VDDR/X
REF0
Mode
Power Isolated 3.3 V power for crystal & reference
Output 3.3V, 14.318 MHz reference clock output.
21,2
Input
Function select pin, 1=desk top mode, 0=mobile mode. Latched input.
3,9,16,22,
27,33,39
GND
Power 3.3 V Ground
4
5
6,14
X1
X2
VDDPCI
FS1
PCICLK_F
PCICLK 0
FS2
Input
14.318 MHz crystal input
Output 14.318 MHz crystal output
Power 3.3 V power for the PCI clock outputs
Input
Output 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
Output 3.3 V PCI clock outputs, generating timing requirements for Pentium II
Input
Logic input frequency select bit. Input latched at power-on.
71,2
81,2
Logic input frequency select bit. Input latched at power-on.
13, 12, 11, 10
15,28,29,31,32,
34,35,37,38
PCICLK (4:1)
SDRAM 12,
SDRAM (7:0)
SDRAM 11
Output 3.3 V PCI clock outputs, generating timing requirements for Pentium II
Output SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
Output SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
Asynchronous active low input pin used to stop the CPUCLK in low state,
1
17
CPU_STOP#
Input
all other clocks will continue to run. The CPUCLK will have a "Turnon" latency
of at least 3 CPU clocks.
SDRAM 10
PCI-STOP#
Output SDRAM clock outputs. Frequency is selected by SD-SEL latched input.
1
18
Synchronous active low input used to stop the PCICLK in a low state. It will not
Input
effect PCICLK_F or any other outputs.
19
VDDSD/C
SDRAM 9
Power 3.3 V power for SDRAM outputs and core
Output SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
1
20
Asynchronous active low input used to stop the SDRAM in a low state.
It will not effect any other outputs.
SDRAM_STOP#
SDRAM 8
Input
Output SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
Asynchronous active low input pin used to power down the device into a low
21 1
PD#
Input
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Data input for I2C serial input.
Clock input of I2C input
23
24
SDATA
SCLK
Input
Input
This input pin controls the frequency of the SIO. If logic 0 at power on
SIO=14.318 MHz . If logic 1 at power-on SIO=24MHz.
SEL24_14#
Input
1,2
25
SIO
FS0
Output Super I/O output. 24 or 14.318 MHz. Selectable at power-up by SEL24_14MHz
Input
Logic input frequency select bit. Input latched at power-on.
3.3 V 48 MHz clock output, fixed frequency clock typically used with
USB devices
1,2
26
48 MHz
Output
30,36
40,41,43
42
VDDSDR
CPUCLK (3:1)
VDDLCPU
REF2
Power 3.3 V power for SDRAM outputs
0utput 2.5 V CPU and Host clock outputs
Power 2.5 V power for CPU
Output 3.3V, 14.318 MHz reference clock output.
1,2
44
This pin selects the operating voltage for the CPU. If logic 0 at power on
CPU=3.3 V and if logic 1 at power on CPU=2.5 V operating voltage.
CPU3.3#_2.5
Input
45
GNDL
REF1
SD_SEL#
IOAPIC
Power 2.5 V Ground for the IOAPIC or CPU
Output 3.3V, 14.318 MHz reference clock output.
1,2
46
Input
This input pin controls the frequency of the SDRAM.
47
48
Output 2.5V fixed 14.318 MHz IOAPIC clock outputs
Power 2.5 V power for IOAPIC
VDDLAPIC
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-128
General Description
The ICS9248-128 is the single chip clock solution for Desktop/Notebook designs using the SIS style chipset. It provides all
necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-128 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the CPUCLK frequency(SD_SEL=1) or other clock frequencies
(SD_SEL=0)
Mode Pin - Power Management Input Control
MODE, Pin 2
(Latched Input)
Pin 17
Pin 18
Pin 20
Pin 21
CPU_STOP#
(INPUT)
PCI_STOP#
(INPUT)
SDRAM_STOP#
(INPUT)
PD#
(INPUT)
0
SDRAM 11
(OUTPUT)
SDRAM 10
(OUTPUT)
SDRAM9
(OUTPUT)
SDRAM8
(OUTPUT)
1
Power Management Functionality
PCICLK
PD# CPU_STOP# PCI_STOP# SDRAM_STOP
(0:4)
SDRAM
(0:12)
Crystal
OSC
PCICLK_F CPUCLK
VCO
Stopped
Low
Running
Stopped
Low
Running
Stopped
Low
Stopped
Low
Running
Stopped
Low
Running
Stopped
Low
Running
Stopped
Low
Running
0
1
1
X
1
1
X
1
1
X
1
0
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped
Low
Stopped
Low
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
0
1
0
1
0
Running
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
Running
Running
Running
Stopped
Low
Stopped
Low
Stopped
Low
Running
Stopped
Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Buffer Selected
Input level
for operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
Third party brands and names are the property of their respective owners.
3
ICS9248-128
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit
PWD
1
Description
0 - ±0.25% Center Spread Spectrum
1 - 0 to -0.5% Down Spread Spectrum
Bit 7
Bit (2, 6:4)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CPUCLK
90.00
66.70
SDRAM
90.00
100.05
63.33
66.66
75.00
74.66
82.66
97.00
66.70
75.00
83.30
95.00
100.00
112.00
124.00
133.30
PCICLK
30.00
33.35
31.66
33.33
30.00
37.33
31.00
32.33
33.35
30.00
33.32
31.66
33.33
37.33
31.00
33.33
95.00
100.00
100.00
112.00
124.00
97.00
66.70
75.00
83.30
95.00
100.00
112.00
124.00
133.30
0,001
Bit
(2, 6:4)
Note 1
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 6:4
0 - Normal
1 - Spread spectrum enabled
0 - Running
1 - Tristate all outputs
Bit 3
Bit 1
Bit 0
0
1
0
Note 1: Default at power-up will be for latched logic inputs to define frequency.
I2C readback of the power up default indicates the revision ID code in bit 2, 6:4 as shown.
Third party brands and names are the property of their respective owners.
4
ICS9248-128
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
Bit
Pin #
-
-
-
-
40
41
43
-
PWD
1
1
1
1
1
1
1
X
Description
(Reserved)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
X
1
1
1
1
1
1
1
FS1#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
-
PCICLK_F
(Reserved)
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
(Reserved)
(Reserved)
(Reserved)
CPUCLK3
CPUCLK2
CPUCLK1
FS0#
13
12
11
10
8
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
28
29
31
32
34
35
37
38
PWD
Description
SDRAM7
Bit
Pin #
-
PWD
Description
(Reserved)
24/14MHz
48MHz
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
25
26
15
17
18
20
21
Notes:
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
-
-
-
47
-
44
46
2
PWD
Description
(Reserved)
FS2#
(Reserved)
IOAPIC
SD_SEL#
REF2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
X
1
1
X
1
1
1
REF1
REF0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Third party brands and names are the property of their respective owners.
5
ICS9248-128
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
VIL
VSS-0.3
V
µA
IIH
VIN = VDD
5
µ
A
A
IIL1
VIN = 0V; Inputs with no pull-up resistors
-5
µ
Input Low Current
Operating Supply
Current
IIL2
VIN = 0V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66 MHz
-200
150
170
180
180
mA
mA
IDD3.3OP66
IDD3.3OP100
IDD3.3PD
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Input address to VDD or GND
Powerdown Current
µ
A
260
600
16
5
Input Frequency
Fi
VDD = 3.3 V
Logic Inputs
X1 & X2 pins
11
27
14.318
MHz
pF
CIN
CINX
Input Capacitance1
45
pF
Transition time1
Clk Stabilization1
Ttrans
To 1st crossing of target frequency
3
ms
TSTAB
From VDD = 3.3 V to 1% target frequency
3
500
4
ms
ps
ns
TCPU100SDRAM100 VT = 1.5V
300
2.6
Skew1
TCPU-PCI VT = 1.5V
1
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/- 5%, VDDL = 2.5V+/- 5% (unless otherwise stated).
PARAMETER
Operating Supply
Current
SYMBOL
IDD2.5OP66
IDD2.5OP100
CONDITIONS
CL = 0 pF; Select @ 66 MHz
MIN
TYP
60
MAX UNITS
72
mA
80
100
mA
CL = 0 pF; Select @ 100 MHz
TCPU100SDRAM100 VT = 1.5V; VTL = 1.25V
TCPU-PCI VT = 1.5V; VTL = 1.25V
230
2.6
500
4
ps
ns
Skew1
1
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9248-128
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = VDDL = 3.3 V +/-5%; CL = 10 - 20 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2.4
TYP
2.2
MAX UNITS
V
IOH = -12 mA
IOL = 12 mA
VOH = 2 V
0.3
0.4
-19
V
-16
22
mA
mA
ns
IOL2B
VOL = 0.8 V
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.45
0.95
46
2
1
Fall Time
tf2B
2
ns
1
Duty Cycle
dt2B
55
%
1
Skew
tsk2B
VT = 1.5 V
65
175
250
ps
1
tjcyc-cyc2B
VT = 1.5 V @ CPU & SDRAM = 100 MHz
210
ps
Jitter, Cycle-to-cycle
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/- 5 %; CL = 10 - 20 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
2.2
0.25
-15
23
MAX UNITS
V
IOH = -12 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1.4
1.2
48
1.6
1.6
55
1
Fall Time
tf2B
ns
%
ps
1
Duty Cycle
dt2B
1
Skew
tsk2B
VT = 1.25 V
50
175
VT = 1.25 V @ CPU &
SDRAM = 100 MHz
1
tjcyc-cyc2B
210
250
ps
Jitter, Cycle-to-cycle
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9248-128
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; CL = 30 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
2.6
0.3
-18
24
MAX UNITS
V
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
22
V
IOH1
mA
mA
ns
IOL1
16
45
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4V, VOL = 0.4 V
VT = 1.5 V
1.8
1.7
49
2
1
Fall Time
tf1
2
ns
1
Duty Cycle
dt1
55
%
1
Skew
tsk1
VT = 1.5 V
260
150
500
500
ps
1
tjcyc-cyc
VT = 1.5 V
ps
Jitter, Cycle-to-cycle
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; CL = 30 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
2.6
0.3
-18
24
MAX UNITS
V
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.4
22
V
IOH1
mA
mA
ns
ns
%
IOL1
16
1
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4V, VOL = 0.4 V
1.6
1.6
50
2
1
Fall Time
tf1
2
1
dt1
VT = 1.5 V; divide by 2 selects < 124 MHz 47
57
1
Duty Cycle
dt2
VT = 1.5 V; divide by 3 selects
VT = 1.5 V; selects >= 124 MHz
VT = 1.5 V; SDRAM 8, 9, 11 & 12
VT = 1.5 V; all except SDRAM 8, 9, 11 & 12
VT = 1.5 V; all SDRAMs
45
43
50
55
%
1
dt3
50
53
%
1
tsk1
110
100
220
200
250
250
350
500
ps
ps
ps
ps
1
Skew
tsk2
1
tsk3
1
tjcyc-cyc
VT = 1.5 V
Jitter, Cycle-to-cycle
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9248-128
Electrical Characteristics - REF/48MHz/SIO
TA = 0 - 70º C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; CL = 20 pF (unless otherwise stated).
PARAMETER
Output High
Voltage
SYMBOL
VOH5
CONDITIONS
MIN
TYP
2.6
MAX UNITS
V
IOH = -12 mA
IOL = 10 mA
2.4
Output Low Voltage
Output High Current
VOL5
0.3
-18
0.4
22
V
IOH5
IOL5
VOH = 2.0 V
VOL = 0.8 V
mA
Output Low Current
Rise Time
16
45
24
2.1
2.1
51
mA
ns
1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4V, VOL = 0.4 V
VT = 1.5 V
4
4
tr5
1
Fall Time
ns
tf5
1
Duty Cycle
55
%
dt5
Jitter, Cycle-to-
Cycle, REF
Jitter, Cycle-to-
Cycle, fixed clock
1
VT = 1.5 V
600
400
1000
500
ps
ps
tjcyc-cyc, REF
1
tjcyc-cyc, fixed
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
ICS9248-128
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
ACK
Stop Bit
Stop Bit
Notes:
1.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
3.
4.
5.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
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10
ICS9248-128
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-128. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-128.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
Third party brands and names are the property of their respective owners.
11
ICS9248-128
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an sychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
SDRAM_STOP# is synchronized by the ICS9248-128. All other clocks will continue to run while the SDRAM clocks are
disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse
width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to
the SDRAM clocks inside the ICS9248-128.
3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
12
ICS9248-128
PCI_STOP# Timing Diagram
PCI_STOP# is an synchronous input to the ICS9248-128. It is used to turn off the PCICLK (0:4) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-128 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
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13
ICS9248-128
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary.The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programmingresistor.
The I/O pins designated by (input/output) on the ICS9248-
128 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(seeAC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
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14
ICS9248-128
Ferrite
Bead
Ferrite
Bead
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
C2
22µF/20V
Tantalum
C2
22µF/20V
Tantalum
VDD
VDD
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
1
2
48
C3
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
3
C1
C1
4
2.5V Power Route
Notes:
5
1
1) All clock outputs should have a
series terminating resistor, and a 20pF
capacitor to ground between the
resistor and clock pin. Not shown in
all places to improve readibility of
diagram.
C4
Clock Load
6
7
C3
8
9
3.3V Power Route
Ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2) Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
3.3V Power Route
Connections to VDD:
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
Third party brands and names are the property of their respective owners.
15
ICS9248-128
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
A1
b
2.413
0.203
0.203
0.127
2.794
0.406
0.343
0.254
.095
.008
.008
.005
.110
.016
.0135
.010
c
SEE VARIATIONS
SEE VARIATIONS
D
E
E1
e
10.033
7.391
10.668
7.595
.395
.291
.420
.299
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.620
MAX
.630
48
15.748
16.002
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
Ordering Information
ICS9248yF-128
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
16
information being relied upon by the customer is current and accurate.
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