ICS9248YF-65 [ICSI]
Frequency Timing Generator for PENDIUM II Systems; 频率时序发生器PENDIUM II系统
| 型号： | ICS9248YF-65 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Timing Generator for PENDIUM II Systems |
| 文件： | 总10页 (文件大小：266K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9248-65
Frequency Timing Generator for PENTIUM II Systems
Features
Key Specification
CPU Output Jitter: <250ps
Generates the following system clocks:
-3 CPUclocks(2.5V,100/133MHz)
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCIOutputJitter:<500ps
PCI Output Jitter. <500ps
Ref Output Jitter. <1000ps
CPU 0:2 Output Skew: <175ps
PCI_F, PCI1:7OutputSkew:<500ps
3V66_0:2OutputSkew<250ps
CPU to 3V66_0:2 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4ns (CPU leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
- 10 PCI clocks, including 1 free-running
(3.3V, 33.3MHz)
-1CPU/2clocks(2.5V, 50/66.6MHz)
-1IOAPICclocks(2.5V,16.67MHz)
-3Fixedfrequency66MHzclocks(3.3V, 66.6MHz)
-2REFclocks(3.3V,14.318MHz)
-1USBclock(3.3V,48MHz)
Efficient power management through PD#.
0 to -0.5% typical down spread modulation on CPU, PCI,
IOAPIC, 3V66 and CPU/2 output clocks.
Usesexternal14.318MHzcrystal.
Block Diagram
Pin Configuration
48-pin SSOP
Third party brands and names are the property of their respective owners.
9248-65 Rev C 7/28/99
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-65
General Description
Power Groups:
VDDREF,GNDREF=REF,X1,X2
GNDPCI,VDDPCI=PCICLK
VDD66,GND66=3V66
The ICS9248-65 is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator(DRCG) chip such as
theICS9211-01.
VDD48,GND48=48MHz
VDDCOR,GNDCOR=PLLCore
VDDLCPU/2,GNDLCPU/2=CPU/2
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without
resorting to board design iterations or costly shielding. The
ICS9248-65 employs a proprietary closed loop design, which
tightly controls the percentage of spreading over process
and temperature variations.
VDDLIOAPIC,GNDIOAPIC=IOAPIC
The CPU/2 clocks are inputs to the DRCG.
Pin Descriptions
Pin number Pin name Type
Description
1,2
3, 9, 17, 24,
28, 34
REF
Output 3.3V, 14.318 MHz reference clock output.
Power 3.3 V power for clock outputs.
Input 14.318 MHz crystal input
VDD
4
5
X1
X2
Output 14.318 MHz crystal output
6,14, 20, 26,
33, 45, 48
7
GND
Power Ground for clock outputs
PCICLK_F
Output 3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
8,10,11,12,13,
15,16,18,19
21,22,23
PCICLK (1:9) Output 3.3 V PCI clock outputs, generating timing requirements for
3V66
Output 3.3 V 66 MHz clock output, fixed frequency clock typically used with AGP
Control for the frequency of clocks at the CPU output pins. If logic "0" is used the
SEL
25
Input
100 MHz frequency is selected. If Logic "1" is used, the 133 MHz frequency is
selected. The PCI clock is multiplexed to run at 33.3 MHz for both selected cases.
133/100#
3.3 V 48 MHz clock output, fixed frequency clock typically used with USB
devices
Frequency select pin , logic input.
Power-on spread spectrum enable option. Active low = spread spectrum clocking
enable. Active high = spread spectrum clocking disable.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped.
27
29,30
31
48 MHz
SEL (0:1)
SPREAD#
Output
Input
Output
32
PD#
Input
35,39
GNDLCPU
CPUCLK
(0:2)
Power Ground for the CPU and Host clock outputs
36,37,40
0utput 2.5 V CPU and Host clock outputs
38,41
42
43
VDDLCPU
GNDLCPU/2
CPU/2
Power 2.5 V power for the CPU and Host clock outputs
Power Ground for the CPU and Host clock outputs
Output Output running at 1/2 CPU clock frequency.Synchronous to the CPU outputs.
Power 2.5 V power for the CPU/2 clock outputs
44
VDDLCPU/2
46
IOAPIC(0:1) Output 2.5V fixed 16.6 MHz IOAPIC clock outputs
47
VDDIOAPIC
Power 2.5V power for IOAPIC clock
2
ICS9248-65
Frequency Select:
SEL
133/100#
CPU
CPU/2
MHz
Hi-Z
3V66
MHz
Hi-Z
N/A
PCI
MHz
Hi-Z
N/A
48
REF IOAPIC
SEL1 SEL0
Comments
MHz
Hi-Z
N/A
MHz
Hi-Z
N/A
MHz
Hi-Z
N/A
MHz
Hi-Z
N/A
0
0
0
0
0
1
Tri-state
Reserved
N/A
48MHz PLL
disabled
0
1
0
100
100
50
50
66.6
66.6
33.3
33.3
Hi-Z
48
14.318
14.318
16.67
16.67
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK TCLK/16 Test mode (1)
N/A
133.3
133.3
N/A
66
66
N/A
66
66
N/A
33
33
N/A
Hi-Z
48
N/A
14.318
14.318
N/A
16.67
16.67
Reserved
Note:
1. TCLK is a test clock driven on the x1 input during test mode.
ICS9248-65 Power Management Features:
REF.
48MHz
PD#
CPUCLK CPU/2 IOAPIC 3V66 PCI PCI_F
Osc VCOs
0
1
LOW
ON
LOW
ON
LOW
ON
LOW LOW LOW
ON ON ON
LOW
ON
OFF
ON
OFF
ON
Note:
1. LOW means outputs held static LOW as per latency requirement next page.
2. On means active.
3. PD# pulled Low, impacts all outputs including REF and 48 MHz outputs.
Power Management Requirements:
Latency
Singal
Singal State
No. of rising edges
of PCICLK
1 (normal operation)
0 (power down)
3mS
PD#
2max.
Note:
1. Clock on/off latency is defined in the number of rising edges of free running PCICLKs between the clock disable goes low/
high to the first valid clock comes out of the device.
2. Power up latency is when PWR_DWN# goes inactive (high to when the first valid clocks are dirven from the device.
3
ICS9248-65
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP#
are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in
the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the
LOW state may require more than one clock cycle to complete.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device).
2. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
4. The shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
4
ICS9248-65
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Group Offset
Group
Offset
Measurement Loads
CPU @ 20pF, 3V66 @ 30pF
3V66 @ 30pF, PCI @ 30pF
Measure Points
CPU @1.25V, 3V66 @ 1.5V
3V66 @ 1.5V, PCI @ 1.5V
CPU to 3V66
3V66 to PCI
CPU to IOAPIC
0.0-1.5ns CPU leads
1.5-4.0ns 3V66 leads
1.5-4.0ns CPU leads
CPU @ 20pF, IOAPIC @ 20pF CPU @1.25V, IOAPIC @ 1.5V
Note: 1. All offsets are to be measured at rising edges.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = VDDL = 3.3 V +/-5%, (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
A
µ
IIH
VIN = VDD
0.1
2.0
-100
65
µA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
A
µ
IIL2
-200
IDD3.3OP100 CL = 0 pF; Select @ 100 MHz
IDD3.3OP133 CL = 0 pF; Select @ 133.3 MHz
IDD3.3OP144 CL = 0 pF; Select @ 144 MHz
IDD3.3OP154 CL = 0 pF; Select @ 154 MHz
IDD3.3PD CL = 0 pF; PWRDWN# = 0
71
Operating
160
200
mA
75
78
A
µ
Power Down
Supply Current
Input frequency
Input Capacitance1
64
Fi
VDD = 3.3 V
12
27
14.318
16
5
MHz
pF
CIN
Logic Inputs
CINX
Ttrans
Ts
X1 & X2 pins
36
1
45
3
pF
Transition Time1
Settling Time1
Clk Stabilization1
To 1st crossing of target Freq.
From 1st crossing to 1% target Freq.
From VDD = 3.3 V to 1% target Freq.
ms
ms
ms
ns
0.5
TSTAB
3
4
Skew1
Skew1
Skew1
tCPU-PCI VT = 1.5 V; VTL = 1.25 V
tCPU-3V66 VT = 1.5 V; VTL = 1.25 V
t3V66-PCI VT = 1.5 V
1.5
2.4
1.4
1.4
1.5
4
ns
ns
1Guaranteed by design, not 100% tested in production.
5
ICS9248-65
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V+/-5%, VDDL = 2.5 V+/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
IDD2.5OP100 CL = 0 pF; Select @ 100 MHz
IDD2.5OP133 CL = 0 pF; Select @ 133.3 MHz
IDD2.5OP144 CL = 0 pF; Select @ 144 MHz
IDD2.5OP154 CL = 0 pF; Select @ 154 MHz
14
18
19
20
0.3
30
30
mA
Operating
Supply Current
30
30
µA
Power Down
IDD2.5PD
CL = 0 pF; PWRDWN# = 0
100
Supply Current
Skew1
Skew1
Skew1
tCPU-PCI
V = 1.5 V; V = 1.25 V
1.5
2.4
1.4
1.4
4
1.5
4
ns
ns
ns
T
TL
tCPU-3V66
V = 1.5 V; V = 1.25 V
T TL
tCPU-IOAPIC V = 1.25 V
TL
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
2.3
0.31
-39
27
0.4
-19
V
mA
mA
ns
IOL2B
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V, Freq. < 124 MHz
VT = 1.25 V
0.95
1
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
50
55
%
1
Skew
tsk2B
22
175
150
+250
250
ps
1
Jitter, One Sigma
Jitter, Absolute
tj1σ2B
VT = 1.25 V
21
ps
1
tjabs2B
VT = 1.25 V
-250
55
ps
1
tjcyc-cyc2B VT = 1.25 V
Jitter, Cycle-to-cycle
110
ps
1Guaranteed by design, not 100% tested in production.
6
ICS9248-65
Electrical Characteristics - CPU/2
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
CONDITIONS
MIN
2
TYP
2.3
0.31
-33
27
MAX UNITS
V
IOH = -12.0 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.4
-19
V
mA
mA
ns
IOL2B
19
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V, Freq. < 124 MHz
VT = 1.25 V
1.1
1
1.6
1.6
1
Fall Time
tf2B
ns
1
Duty Cycle
dt2B
45
48
55
%
1
Jitter, One Sigma
Jitter, Absolute
tj1σ2B
13
150
+250
250
ps
1
tjabs2B
VT = 1.25 V
-250
42
ps
1
tjcyc-cyc2B VT = 1.25 V
Jitter, Cycle-to-cycle
100
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.1
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.17
-61
45
0.4
-22
V
IOH1
mA
mA
IOL1
25
0.5
0.5
45
Rise Time1
Fall Time1
Duty Cycle1
Skew1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
1.7
51
2
ns
ns
%
2
dt1
tsk1
55
VT = 1.5 V
37
500
150
250
500
ps
ps
ps
ps
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Cycle-to-cycle1
tj1 1
σ
VT = 1.5 V
16
tjabs1
VT = 1.5 V
-250
50
tjcyc-cyc1 VT = 1.5 V
130
1Guaranteed by design, not 100% tested in production.
7
ICS9248-65
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH1
CONDITIONS
MIN
2.4
TYP
3.1
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
VOL1
0.17
-62
45
0.4
-22
V
IOH1
mA
mA
IOL1
25
45
Rise Time1
Fall Time1
Duty Cycle1
tr1
tf1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.5
1.6
50
2
ns
ns
%
2
dt1
tsk1
55
Skew1
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Cycle-to-cycle1
VT = 1.5 V
310
11
500
150
250
500
ps
ps
ps
ps
tj1 1
σ
VT = 1.5 V
tjabs1
VT = 1.5 V
-250
45
tjcyc-cyc1 VT = 1.5 V
105
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - IOAPIC
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH4B
VOL4B
IOH4B
CONDITIONS
MIN
2
TYP
2.4
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
0.17
-61
53
0.4
-19
V
mA
mA
IOL4B
19
Rise Time1
Fall Time1
Duty Cycle1
Tr4B
Tf4 B
Dt4B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
0.75
0.675
49.5
26
2.2
2
ns
ns
%
ps
ps
ps
45
55
Jitter, One Sigma1
Jitter, Absolute1
Jitter, Cycle-to-cycle1
Tj1 4B
VT = 1.25 V
150
500
500
σ
Tjabs4B
VT = 1.25 V
-500
137
tjcyc-cyc4B VT = 1.25 V
200
1Guaranteed by design, not 100% tested in production.
8
ICS9248-65
Electrical Characteristics - REF, 48MHz
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
VOH5
CONDITIONS
MIN
2.4
TYP
2.9
MAX UNITS
V
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
IOH = -12 mA
IOL = 10 mA
VOH = 2.0 V
VOL = 0.8 V
VOL5
0.33
-31
23
0.4
-22
V
IOH5
mA
mA
IOL5
16
Rise Time1
Fall Time1
Duty Cycle1
tr5
tf5
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.8
2.1
52
4
ns
ns
%
4
dt5
45
55
Jitter, One Sigma1
Jitter, Absolute1
Jitter, One Sigma1
Jitter, Absolute1
tj1 5
VT = 1.5 V, REF
85
150
500
150
250
ps
ps
ps
ps
σ
tjabs5
VT = 1.5 V, REF
-500
-250
285
32
tj1 5
σ
VT = 1.5 V, 48 MHz
VT = 1.5 V, 48 MHz
tjabs5
110
1Guaranteed by design, not 100% tested in production.
9
ICS9248-65
SYMBOL
COMMON DIMENSIONS
VARIATIONS
D
N
MIN.
.095
.008
.088
.008
.005
NOM.
.101
.012
.090
.010
-
MAX.
.110
.016
.092
.0135
.010
MIN.
.620
NOM. MAX.
.625 .630
A
A1
A2
B
AC
48
C
D
E
See Variations
.296
.292
.299
e
H
h
0.025 BSC
.406
.013
.400
.010
.024
.410
.016
.040
48 Pin SSOP Package
L
.032
N
See Variations
5°
0°
8°
X
.085
.093
.100
Ordering Information
ICS9248yF-65
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
10
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