ICS9250-22 [ICSI]
Frequency Generator for P IV⑩; 频率发生器的P IV ™
| 型号： | ICS9250-22 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator for P IV⑩ |
| 文件： | 总11页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Inc.
ICS9250-22
Frequency Generator for P IV™
Recommended Application:
P IV Chipset Support
Output Features:
Pin Configuration
GND
MULTSEL0/REF
MULTSEL1/REF
VDDREF
X1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDMREF
3VMREF
•
•
4 Differential CPU Clock Pairs @ 3.3V
2 - 3V MREF clocks for memory reference seeds,
(separate single ended but 180 degrees out of phase)
3VMREF_B
GNDMREF
SPREAD#
CPUCLKST3
CPUCLKSC3
VDDCPU
CPUCLKST2
CPUCLKSC2
GNDCPU
CPUCLKST1
CPUCLKSC1
VDDCPU
CPUCLKST0
CPUCLKSC0
GNDCPU
I REF
VDDA
GNDA
VDD3V66
3V66-3
3V66-2
GND3V66
GND3V66
3V66-1
3V66-0
VDD3V66
X2
•
•
•
4 - 66MHz reference output
10 - 3V 33MHz PCI clocks
2 - 48MHz clocks
GNDREF
PCICLK0
PCICLK1
VDDPCI
PCICLK2
PCICLK3
GNDPCI
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PCICLK8
PCICLK9
VDDPCI
•
2 - 14.318 reference output
Features:
•
•
Support power management: Power Down Mode
Supports Spread Spectrum modulation: 0 to -0.5% down
spread.
•
•
Uses external 14.318MHz crystal
Select logic for Differential Swing Control, Test mode,
Tristate, Power down, Spread Spectrum, limited
frequency select, selective clock enable.
SEL100/133
GND48
FS0/48MHz
FS1/48MHz
VDD48
•
•
External resistor for current reference
FS pins for frequency select
Key Specifications:
PD#
•
•
•
3V66 Output jitter <300ps
CPU Output Jitter <200ps
MREF Output jitter <250ps
56-Pin 300mil SSOP &TSSOP
Block Diagram
Functionality
SEL133/
100
FS0 FS1
Function
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Active 100MHz
(Reserved)
PLL2
48MHz
2
0
0
(Reserved)
0
Tristate all outputs
Active 133MHz
(Reserved)
X1
X2
XTAL
OSC
REF
2
1
1
PLL1
Spread
Spectrum
CPUCLKST (3:0)
CPUCLKSC (3:0)
CPU
DIVDER
4
1
(Reserved)
4
1
Test Mode
3VMREF
DIVDER
3VMREF
3VMREF_B
Control
Logic
PD#
SPREAD#
PCI
DIVDER
PCICLK (9:0)
3V66 (3:0)
10
4
Power Groups
MULTSEL (1:0)
SEL100/133
FS(1:0)
Config.
Reg.
VDDREF, GNDREF=REF, X1, X2
3V66
DIVDER
VDDPCI, GNDPCI=PCICLK
VDD48, GND48=48MHz, PLL2
VDD3V66,GND3V66=3V66
VDDCPU, GNDCPU=CPUCLK
VDDMREF, GNDMREF=3VMREF, 3VMREF_B
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9250-22 Rev B 12/08/00
Third party brands and names are the property of their respective owners.
information being relied upon by the customer is current and accurate.
ICS9250-22
General Description
The ICS9250-22 is a single chip clock solution.
Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9250-22 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and temperature variations.
Pin Configuration
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
Ground pins for 3.3V supply
1, 7, 13, 19, 24, 32,
33, 37, 40, 46, 53
GND
PWR
MULTSEL0 and MULTSEL1 inputs are sensed on power-up and
then internally latched prior to the pin being used for output on 3V
14.318MHz clocks.
3, 2
REF/MULTSEL (1:0)
VDD
IN
4, 10, 16, 22, 27, 29,
36, 38, 43, 49, 56
PWR
3.3V power supply
5
6
X1
X2
X2 Crystal Input 14.318MHz Crystal input
X1 Crystal Output 14.318MHz Crystal output
21, 20, 18, 17, 15,
14, 12, 11, 9, 8
PCICLK (9:0)
OUT
PCI clock outputs
23
SEL100/133
FS (1:0)
48MHz
IN
IN
CPU Frequency Select. Low=100MHz, High=133MHz
Frequency select pins
26, 25
OUT
IN
48MHz clock output
28
PD#
Invokes power-down mode. Active Low.
66MHz reference clocks
35, 34, 31, 30
3V66 (3:0)
OUT
This pin establishes the reference current for the CPUCLK pairs.
This pin takes a fixed precision resistor tied to ground in order to
establish the appropriate current.
39
I REF
OUT
OUT
OUT
"True" clocks of differential pair CPU outputs. These are switched
current outputs and external resistors are required for voltage bias.
51, 48, 45, 42
50, 47, 44, 41
CPUCLKST (3:0)
CPUCLKSC (3:0)
"Complementory" clocks of differential pair CPU outputs. These
are switched current outputs and external resistors are required for
voltage bias.
Invokes Spread Spectrum functionality on the Differential host
clocks, MRef/MRef_b clocks, 66MHz clocks, and 33MHz PCI
clocks. Active Low
52
SPREAD#
IN
3V reference to memory clock driver
(out of phase with 3Vmref)
54
55
3VMREF_B
3VMREF
OUT
OUT
3V reference to memory clock driver
Third party brands and names are the property of their respective owners.
2
ICS9250-22
Truth Table
SEL
133/100
FS0
FS1
CPU
MRef
3V66
PCI
48MHz
REF
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100MHz 50MHz
66MHz
N/A
33MHz
N/A
48MHz
N/A
14.318MHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Tristate
Tristate
Tristate
66MHz
N/A
Tristate
33MHz
N/A
Tristate
48MHz
N/A
Tristate
14.318MHz
N/A
133MHz 66MHz
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
TCLK/2 TCLK/4
TCLK
TCLK/6
TCLK
Group Offset Limits
Measurement Loads
(lumped)
Group
Offset
Measure Points
CPU to 3V66
CPU to PCI
No Requirement
1.5 - 3.5ns
3V66 leads
3V66 to PCI
30pF
1.5V
Third party brands and names are the property of their respective owners.
3
ICS9250-22
CPUCLK Buffer Configuration
Conditions
Configuration
Load
Min
Max
All combinations of M0,
M1 and Rr shown in
table below
Nominal test load for
given configuration
Vdd = nominal (3.30V)
-7% I nominal +7% I nominal
-12% I nominal +12% I nominal
Iout
Iout
All combinations of M0,
M1 and Rr shown in
table below
Nominal test load for
given configuration
Vdd = 3.30 ± 5%
CPUCLK Swing Select Functions
Reference R,
Iref=
Vdd/(3*Rr)
Board Target
Output
Current
Voh @ Z,
Iref=2.32mA
MULTSEL0
MULTSEL1
Trace/Term Z
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
60 ohms
50 ohms
Rr = 475 1%
Iref = 2.32mA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.71V @ 60
0.59V @ 50
0.85V /2 60
0.71V @ 50
0.56V @ 60
0.47V @ 50
0.99V @ 60
0.82V @ 50
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 475 1%
Iref = 2.32mA
Rr = 221 1%
Iref = 5mA
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
30 (DC equiv)
25 (DC equiv)
Ioh = 5*Iref
Ioh = 5*Iref
Ioh = 6*Iref
Ioh = 6*Iref
Ioh = 4*Iref
Ioh = 4*Iref
Ioh = 7*Iref
Ioh = 7*Iref
0.75V @ 30
0.62V @ 20
0.90V @ 30
0.75V @ 20
0.60 @ 20
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
0.5V @ 20
1.05V @ 30
0.84V @ 20
Rr = 221 1%
Iref = 5mA
Rr = 221 1%
Iref = 5mA
Third party brands and names are the property of their respective owners.
4
ICS9250-22
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
V
VIL
VSS-0.3
-5
A
µ
IIH
VIN = VDD
5
A
µ
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
-5
Input Low Current
IIL2
-200
Operating Supply
Current
Powerdown Current
IDD3.3OP
mA
mA
CL = 0 pF; Select @ 100 MHz
130
35
250
60
CL = 0 pF; Input address to VDD or GND
IDD3.3PD
Fi
Input Frequency
Pin Inductance
VDD = 3.3 V
14.318
MHz
nH
pF
Lpin
7
5
CIN
Logic Inputs
Input Capacitance1
COUT
CINX
Ttrans
Output pin capacitance
X1 & X2 pins
6
pF
27
45
3
pF
Transition time1
Settling time1
Clk Stabilization1
To 1st crossing of target frequency
ms
Ts
From 1st crossing to 1% target frequency
From VDD = 3.3 V to 1% target frequency
3
ms
TSTAB
3
ms
ns
ns
tPZH,tPZL Output enable delay (all outputs)
PHZ,tPLZ
1
1
10
10
Delay1
t
Output disable delay (all outputs)
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
5
ICS9250-22
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
2
TYP
714
714
MAX UNITS
1
Output Impedance
RDSP2B
VO = VDD*(0.5)
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
RDSN2B
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
Ω
VOH2B
V
VOL2B
0.4
-27
30
V
2
mA
mA
IOH2B
V OH@MIN = 1.0 V, V OH@MAX = 2.375 V
VOL @MIN = 1.2 V, VOL @MAX = 0.3 V
VOL = 20%, VOH = 80%
VOH = 80%, VOL = 20%
VT = 50%
-27
27
2
Output Low Current
IOL2B
1
Rise Time
Fall Time
Duty Cycle
tr2B
175
175
45
500
500
51
700
700
55
ps
ps
%
1
tf2B
1
dt2B
1
Skew
Jitter
tsk2B
VT = 50%
110
110
150
200
ps
ps
1
tjcyc-cyc
VT = 50%
1Guaranteed by design, not 100% tested in production.
2 IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - PCI
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
FO1
CONDITIONS
MIN
TYP
33
MAX UNITS
MHz
Output Frequency
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
55
Ω
V
1
VOH
2.4
1
VOL
0.55
-33
38
V
1
mA
mA
IOH
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
1
IOL
1
Rise Time
Fall Time
Duty Cycle
tr1
0.5
0.5
45
1.4
1.4
51
2
ns
ns
%
1
tf1
2
1
dt1
55
1
Skew
Jitter
tsk1
VT = 1.5 V
270
115
500
500
ps
ps
1
tjcyc-cyc
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
ICS9250-22
Electrical Characteristics - MREF/MREF_B
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
FO1
CONDITIONS
MIN
TYP
MAX UNITS
MHz
Output Frequency
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
33
55
Ω
V
1
VOH
2.4
1
VOL
0.55
-33
38
V
1
mA
mA
IOH
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
1
IOL
1
Rise Time
Fall Time
Duty Cycle
tr1
0.4
0.4
45
1.4
1.4
51
1.6
1.6
55
ns
ns
%
1
tf1
1
dt1
1
Skew
Jitter
tsk1
VT = 1.5 V
80
100
250
ps
ps
1
tjcyc-cyc
VT = 1.5 V
105
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
FO1
CONDITIONS
MIN
TYP
48
MAX UNITS
MHz
Output Frequency
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
60
Ω
V
1
VOH
2.4
1
VOL
0.4
-23
27
V
1
mA
mA
IOH
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
1
1
IOL
1
Rise Time
Fall Time
Duty Cycle
tr1
2
2
4
ns
ns
%
1
tf1
1
4
1
dt1
45
50
55
1
Skew
Jitter
tsk1
VT = 1.5 V
N/A
1000
ps
ps
1
tjcyc-cyc
VT = 1.5 V
205
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
ICS9250-22
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
FO1
CONDITIONS
MIN
TYP
33
MAX UNITS
MHz
Output Frequency
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
12
55
Ω
V
1
VOH
2.4
1
VOL
0.55
-33
38
V
1
mA
mA
IOH
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-33
30
1
IOL
1
Rise Time
Fall Time
Duty Cycle
tr1
0.5
0.5
45
1.3
1.3
51
2
ns
ns
%
1
tf1
2
1
dt1
55
1
Skew
Jitter
tsk1
VT = 1.5 V
85
80
250
300
ps
ps
1
tjcyc-cyc
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - 48MHz
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
FO1
CONDITIONS
MIN
TYP
48
MAX UNITS
MHz
Output Frequency
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
RDSP1
VO = VDD*(0.5)
IOH = -1 mA
IOL = 1 mA
20
60
Ω
V
1
VOH
2.4
1
VOL
0.4
-23
27
V
1
mA
mA
IOH
V OH@MIN = 1.0 V, V OH@MAX = 3.135 V
VOL @MIN = 1.95 V, VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
-29
29
1
1
IOL
1
Rise Time
Fall Time
Duty Cycle
tr1
2
2
4
ns
ns
%
1
tf1
1
4
1
dt1
45
54
55
1
Skew
Jitter
tsk1
VT = 1.5 V
N/A
350
ps
ps
1
tjcyc-cyc
VT = 1.5 V
120
1Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
8
ICS9250-22
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is
an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizer.
Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down
latency should be as short as possible but conforming to the sequence requirements shown below.
PD#
MREF
MREF_BAR
CPUCLKT
CPUCLKC
VCO
Crystal
Notes:
1. As shown, the outputs Stop Low on the next falling edge after PD# goes low.
2. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part.
3. The shaded sections on the VCO and the Crystal signals indicate an active clock.
Third party brands and names are the property of their respective owners.
9
ICS9250-22
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEE VARIATIONS
SEE VARIATIONS
D
E
E1
e
10.033
7.391
10.668
7.595
.395
.291
.420
.299
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.720
MAX
.730
56
18.288
18.542
JEDEC MO-118
6/1/00
DOC# 10-0034
REV B
Ordering Information
ICS9250yF-22-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
10
ICS9250-22
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
MIN
-
MAX
1.20
0.15
1.05
0.27
0.20
MIN
-
MAX
.047
.006
.041
.011
.008
A
A1
A2
b
0.05
0.80
0.17
0.09
.002
.032
.007
.0035
c
SEE VARIATIONS
8.10 BASIC
SEE VARIATIONS
0.319
D
E
E1
e
6.00
6.20
0.50 BASIC
0.75
.236
.244
0.020 BASIC
L
0.45
.018
.30
SEE VARIATIONS
SEE VARIATIONS
N
0°
-
8°
0°
-
8°
α
aaa
0.10
.004
VARIATIONS
D mm.
D (inch)
N
MIN
MAX
MIN
.547
MAX
6.10 mm. Body, 0.50 mm. pitch TSSOP
(0.020 mil)
56
13.90
14.10
.555
7/6/00 Rev B
(240 mil)
MO-153 JEDEC
Doc.# 10-0039
Ordering Information
ICS9250yG-22-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
Third party brands and names are the property of their respective owners.
11
information being relied upon by the customer is current and accurate.
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