ICS9248YF-131-T [ICSI]
Frequency Generator & Integrated Buffers for Celeron & PII/III??; 频率发生器和缓冲器集成的赛扬和PII / III ？
| 型号： | ICS9248YF-131-T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Frequency Generator & Integrated Buffers for Celeron & PII/III?? |
| 文件： | 总16页 (文件大小：499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated
Circuit
Systems, Incꢀ
ICS9248-131
Frequency Generator & Integrated Buffers for Celeron & PII/III™
RecommendedApplication:
ALI -Aladdin V - mobile style chipsets
Pin Configuration
OutputFeatures:
VDDF
*REF0/CPU2.5_3.3#
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDAGP
AGP0
AGP1
3-CPUs@2ꢀ5/3ꢀ3V, upto100MHzꢀ
3-AGPCLK@3ꢀ3V
13-SDRAM@3ꢀ3V
6-PCI@3ꢀ3V
1-48MHz,@3ꢀ3Vfixedꢀ
1-REF@3ꢀ3V,14ꢀ318MHzꢀ
X1
X2
VDDPCI
GND
CPUCLK0
CPUCLK1
VDDL
CPUCLK2
SDRAM12
GND
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GND
*PCICLK_F/FS1
*PCICLK0/FS2
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDA
BUFFERIN
GND
Features:
Support power management: CPU, PCI, AGP stop and
Power down Mode from I2C programmingꢀ
Spread spectrum for EMI controlꢀ
Uses external 14ꢀ318MHz crystal
FS pins for frequency select
*CPU_STOP#/SDRAM11
*PCI_STOP#/SDRAM10
VDDSDR
*AGP_STOP#/SDRAM9
*PD#/SDRAM8
GND
KeySpecifications:
CPUCPU:<250ps
AGPPCI:<550ps
CPU(early)-PCI:1-4ns, Center2-6ns
SDATA
SCLK
48MHz/FS0*
AGP_F/MODE*
48-Pin SSOP
* Internal Pull-up Resistor of
240K to 3ꢀ3V on indicated inputs
Block Diagram
Functionality
PLL2
48MHz
CPU, SDRAM
PCI
(MHz)
AGP
(MHz)
FS2 FS1 FS0
(MHz)
X1
X2
XTAL
OSC
REF
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
100
95.25
83.3
97
33.33
31.75
33.30
32.33
30.50
32.07
33.33
30.00
66.67
63.50
66.60
64.66
61.00
64.15
66.67
60.00
PLL1
Spread
Spectrum
CPU
DIVDER
Stop
Stop
CPUCLK (2:0)
3
5
91.5
96.22
66.67
60
PCI
DIVDER
PCICLK (4:0)
PCICLK_F
CPU2.5_3.3#
Control
Logic
SDATA
SCLK
FS (2:0)
Note:REF&IOAPIC=14ꢀ318MHz
AGP
DIVDER
Stop
AGP (1:0)
AGP_F
PD#
PCI_STOP#
CPU_STOP#
SDRAM_STOP#
AGP-STOP#
MODE
2
Config.
Reg.
Power Groups
Analog
Digital
VDDF
VDDA
VDDPCI
VDDSDR
VDDAGP
SDRAM (12:0)
BUFFERIN
13
Pentium is a trademark of Intel Corporation
I2C is a trademark of Philips Corporation
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
9248-131RevB7/17/00
information being relied upon by the customer is current and accurate.
ICS9248-131
Pin Descriptions
PIN NUMBER
1, 6, 14, 19,
30, 36, 48
PIN NAME
TYPE
DESCRIPTION
VDD
PWR
Power supply, nominal 3.3V
14.318 Mhz reference clock.
REF0
OUT
IN
2
Indicates whether VDDL is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V
CPU1. Latched input2
CPU2.5_3.3#1,2
3,9,16,22,27,
33,39,45
GND
X1
PWR
IN
Ground
Crystal input, has internal load cap (33pF) and feedback
resistor from X2
4
Crystal output, nominally 14.318MHz.
Has internal load cap (33pF)
5
X2
OUT
Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew
(CPU early) This is not affected by PCI_STOP#
Frequency select pin. Latched Input. Along with other FS pins determins the
CPU, SDRAM, PCI & AGP frewuencies.
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Frequency select pin. Latched Input
PCICLK_F
FS11, 2
OUT
IN
7
8
PCICLK0
FS21, 2
OUT
IN
13, 12, 11, 10
15
PCICLK(4:1)
BUFFERIN
OUT
IN
PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early)
Input pin for SDRAM buffers.
Halts CPUCLK clocks at logic 0 level,
when input low (in Mobile Mode, MODE=0)
SDRAM clock output
Halts PCICLK clocks at logic 0 level, when input low
(In mobile mode, MODE=0)
CPU_STOP#1
SDRAM 11
IN
17
18
OUT
IN
PCI_STOP#1
SDRAM 10
OUT
OUT
SDRAM clock output
40, 28, 29, 31, 32,
34, 35, 37, 38
SDRAM (12, 7:0)
SDRAM clock outputs.
This asynchronous input halts AGP clocks at logic "0" level when input low
(in Mobile Mode, MODE=0) Does not affect AGP0
SDRAM clock output
AGP_STOP#
SDRAM9
PD#
IN
OUT
IN
20
This asyncheronous Power Down input Stops the VCO, crystal & internal
clocks when active, Low. (In Mobile Mode, MODE=0)
SDRAM clock output
21
SDRAM8
SDATA
SCLK
OUT
I/O
IN
23
24
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
AGP_F
OUT
Advanced Graphic Port output, Not affected by AGP_STOP#
Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode.
Latched Input.
48MHz output clock for USB timing.
Frequency select pin. Latched Input. Along with other FS pins determins the
25
MODE1, 2
48MHz
FS01, 2
IN
OUT
IN
26
CPU, SDRAM, PCI & AGP frewuencies.
41, 43, 44
CPUCLK(2:0)
OUT
CPU clock outputs, powered by VDDL. Low if CPU_STOP#=Low
42
46, 47
VDDL
AGP (1:0)
PWR
OUT
Supply for CPU, either 2.5V or 3.3V nominal
Advanced Graphic Port outputs
Notes:
1: Internal Pull-up Resistor of 240K to 3ꢀ3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-resetꢀ Use 10Kohm resistor to
program logic Hi to VDD or GND for logic lowꢀ
2
ICS9248-131
General Description
The ICS9248-131 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrixꢀ Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitionsꢀ
Spread spectrum may be enabled through I2C programmingꢀ Spread spectrum typically reduces system EMI by 8dB to 10dBꢀ
This simplifies EMI qualification without resorting to board design iterations or costly shieldingꢀ The ICS9248-131 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variationsꢀ
Serial programming I2C interface allows changing functions, stop clock programming and frequency selectionꢀ The SDRAM12
output may be used as a feed back into an off chip PLLꢀ
Mode Pin - Power Management Input Control
MODE, Pin 25
(Latched Input)
Pin 17
Pin 18
Pin 20
Pin 21
CPU_STOP#
(INPUT)
SDRAM 11
(OUTPUT)
PCI_STOP#
(INPUT)
SDRAM 10
(OUTPUT)
AGP_STOP#
(INPUT)
SDRAM 9
(OUTPUT)
PD#
0
(INPUT)
SDRAM 8
(OUTPUT)
1
Power Management Functionality
AGP,
CPUCLK
Outputs
PCICLK_F,
REF, 48MHz
and SDRAM
PCICLK
(4:0)
Crystal
OSC
AGP
(1:0)
AGP_STOP# CPU_STOP# PCI_STOP#
VCO
1
1
1
0
0
1
1
1
1
1
0
1
Stopped Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped Low
Running
Running
Running Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Buffer Selected for
Input level
operation at:
(Latched Data)
1
0
2.5V VDD
3.3V VDD
3
ICS9248-131
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Bit
Description
PWD
Bit7 Bit2
Spread Spectrum Method
0,0
0,1
+/- 0.25% Center Spread Spectrum Modulation
+/- 0.15% Center Spread Spectrum Modulation
0 to -0.5 Down Spread Spectrum Modulation
+/- 0.375% Center Spread Spectrum Modulation
Bit 7,2
0,0
1,0
1,1
Bit6 Bit5 Bit4
111
CPU Clock
100
PCI
AGP
66.67
63.50
66.60
64.66
61.00
64.15
66.67
60.00
33.33
31.75
33.30
32.33
30.50
32.07
33.33
30.00
110
95.25
83.3
101
Note1
001
Bit 6:4
100
97
011
91.5
010
96.22
66.67
60
001
000
0 - Frequency is selected by hardware select, Latched inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Normal
Bit 3
Bit 1
Bit 0
0
0
0
1 - Spread Spectrum Enabled
0 - Running
1 - Tristate all outputs
Note 1ꢀ Default at Power-up will be for latched logic inputs to define frequencyꢀ Bits 4, 5, 6 are default to 001, and if bit
3 is written to a 1 to use Bits 6:4, then these should be defined to desired frequency at same write cycleꢀ
Note: PWD = Power-Up Default
Byte2:PCIActive/InactiveRegister
(1 = enable, 0 = disable)
Byte 1: CPU,Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin # PWD
Description
CPU2.5_3.3#
PCICLK_F (Act/Inact)
FS0#
PCICLK4 (Act/Inact)
PCICLK3 (Act/Inact)
PCICLK2 (Act/Inact)
PCICLK1 (Act/Inact)
PCICLK0(Act/Inact)
Bit
Pin #
-
-
-
40
-
41
43
44
PWD
Description
(Reserved)
FS2#
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
7
X
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
X
X
1
1
1
-
X
1
1
1
1
FS1#
13
12
11
10
8
SDRAM12 (Act/Inact)
(Reserved)
CPUCLK2 (Act/Inact)
CPUCLK1 (Act/Inact)
CPUCLK0 (Act/Inact)
1
1
1
Notes:
Notes:
1ꢀ Inactive means outputs are held LOW and are disabled
from switchingꢀ
1ꢀ Inactive means outputs are held LOW and are disabled
from switchingꢀ
I2C is a trademark of Philips Corporation
4
ICS9248-131
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
Bit
Pin #
28
29
31
32
34
35
37
38
PWD
Description
SDRAM7 (Act/Inact)
SDRAM6 (Act/Inact)
SDRAM5 (Act/Inact)
SDRAM4 (Act/Inact)
SDRAM3 (Act/Inact)
SDRAM2 (Act/Inact)
SDRAM1 (Act/Inact)
SDRAM0 (Act/Inact)
Bit
Pin #
25
-
-
-
PWD
Description
AGP_F (Active/Inactive)
(Reserved)
(Reserved)
(Reserved)
SDRAM11 (Act/Inact)
(Desktop Mode Only)
SDRAM10 (Act/Inact)
(Desktop Mode Only)
SDRAM9 (Act/Inact)
SDRAM8 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
1
Bit 3
Bit 2
17
18
1
1
Bit 1
Bit 0
20
21
1
1
Notes:
1ꢀ Inactive means outputs are held LOW and are disabled
from switchingꢀ
Notes:
1ꢀ Inactive means outputs are held LOW and are disabled
from switchingꢀ
Byte 6: Optional Register for Possible
Furture Requirements
Byte5:Peripheral Active/InactiveRegister
(1 = enable, 0 = disable)
Bit
Pin #
PWD
Description
(Reserved)
Bit
Pin #
-
-
-
47
-
-
46
2
PWD
1
1
1
1
1
X
1
Description
(Reserved)
(Reserved)
(Reserved)
AGP0 (Act/Inact)
(Reserved)
MODE
AGP1 (Act/Inact)
REF0 (Act/Inact)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
1
1
1
1
1
1
1
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
1
Notes:
Notes:
1ꢀ Byte 6 is reserved by Integrated Circuit Systems for futue
applicationsꢀ
1ꢀ Inactive means outputs are held LOW and are disabled
from switchingꢀ
5
ICS9248-131
Absolute Maximum Ratings
Supply Voltage ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 5ꢀ5V
Logic Inputs ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ GND 0ꢀ5 V to VDD +0ꢀ5 V
Ambient Operating Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 0°C to +70°C
Storage Temperature ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the deviceꢀ These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not impliedꢀ Exposure to absolute maximum rating conditions for extended periods
may affect product reliabilityꢀ
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD =VDDL= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX UNITS
VDD+0.3
V
V
VIL
VSS-0.3
0.8
5
IIH
VIN = VDD
uA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66 MHz
CL = 0 pF; Select @ 100 MHz
VDD = 3.3 V
-5
uA
IIL2
-200
uA
105
140
160
160
16
mA
mA
MHz
IDD3.3OP
Operating Supply Current
Input frequency
Fi
12
27
14.318
CIN
CINX
Logic Inputs
5
45
2
pF
pF
ms
ms
ms
ns
Input Capacitance1
Transition Time1
X1 & X2 pins
Ttrans
Ts
TSTAB
TCPU-PCI
TAGP-PCI
To 1st crossing of target Freq
From 1st corssing to 1% target Freq
From VDD = 3.3 V to 1% target Freq.
Vt=1.5 V; f=66 / 100 Mhz; CPU leads
Vt = 1.5V; AGP Leads ( Vdd+/-5% 25C)
Settling Time1
2
Clk Stabilization1
2
1
2
4
Skew1
300
550
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL=2.5V +/- 5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
8
MAX UNITS
CL = 0 pF; Select @ 66.8 MHz
15
IDDL2.5
Operating Supply Current
mA
20
CL = 0 pF; Select @ 100 MHz
15
2
TCPU-PCI1
TAGP-PCI1
Vt=1.5 V; f=66 / 100 Mhz; CPU leads
Vt = 1.5V; AGP Leads ( Vdd+/-5% 25C)
1
4
ns
ps
Skew1
300
550
6
ICS9248-131
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=VDDL=3.3V +/- 5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
13.5
TYP
30
MAX UNITS
1
Output Impedance
RDSP2B
VO=VDD*(0.5)
45
45
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN2B
VO=VDD*(0.5)
IOH = -28 mA
IOL = 27 mA
VOH = 2.0 V
VOL = 0.8 V
13.5
2.5
32
Ω
V
VOH2A
VOL2A
IOH2A
IOL2A
0.4
-23
V
mA
mA
33
50
1
tr2A
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.1
1.6
52
2
ns
ns
%
Fall Time1
Duty Cycle1
Skew window1
1
tf2A
2
1
dt2A
55
1
tsk2A
VT = 1.5 V
130
130
250
250
ps
ps
tjcyc-cyc2A1
Jitter, Cycle-to-cycle1
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
1Edge displacement of a period relative to a 10-clock-cycle rolling average period.
Electrical Characteristics - CPU
TA = 0 - 70C; VDD=3.3V, VDDL=2.5V, both +/- 5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
13.5
TYP
30
MAX UNITS
1
Output Impedance
RDSP2B
VO=VDD*(0.5)
45
45
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN2B
VO=VDD*(0.5)
IOH = -8 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
13.5
2
32
Ω
V
VOH2B
VOL2B
IOH2B
IOL2B
0.4
-16
V
mA
mA
19
45
1
tr2B
VOL = 0.4 V, VOH = 2.0 V
VOH = 2.0 V, VOL = 0.4 V
VT = 1.25 V
1
1.8
1.8
55
ns
ns
%
Fall Time1
Duty Cycle1
Skew window1
1
tf2B
1.3
50
1
dt2B
1
tsk2B
VT = 1.25 V
130
130
250
250
ps
ps
tjcyc-cyc2A1
Jitter, Cycle-to-cycle1
VT = 1.5 V
1Guaranteed by design, not 100% tested in production.
1Edge displacement of a period relative to a 10-clock-cycle rolling average period.
7
ICS9248-131
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = VDDL = 3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
24
MAX UNITS
1
Output Impedance
RDSP2B
VO=VDD*(0.5)
55
55
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN2B
VO=VDD*(0.5)
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
12
23
Ω
V
VOH1
VOL1
IOH1
IOL1
2.4
0.4
-40
V
mA
mA
41
45
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.7
1.5
50
2.3
2.0
55
ns
ns
%
Fall Time1
tf1
Duty Cycle1
Skew window1
Jitter, Cyc-to-Cyc
dt1
tsk1
tjcyc-cyc1
VT = 1.5 V
VT = 1.5 V
305
100
500
500
ps
ps
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD=VDDL=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
1
Output Impedance
RDSP2B
VO=VDD*(0.5)
12
24.19
23.08
55
55
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SD (0:1,3:12) Rise Time1
SD(0:1,3:12) Fall Time1
SD(0:1,3:12) Duty Cycle1
SD 2 Rise Time1
RDSN2B
VO=VDD*(0.5)
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
12
Ω
V
VOH1
VOL1
IOH1
IOL1
2.4
0.4
-40
V
mA
mA
41
50
50
tr1
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
1.5
54
2
2
ns
ns
%
ns
tf1
dt1
58
2.4
tr1
VOL = 0.4 V, VOH = 2.4 V
1.8
SD 2 Fall Time1
tf1
dt1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.9
54
4
2.4
58
6
ns
%
ns
SD 2 Duty Cycle1
Propagation Delay
Skew window1
Tprop
VT = 1.5 V
tsk1
VT = 1.5 V
350
500
ps
1Guaranteed by design, not 100% tested in production.
8
ICS9248-131
Electrical Characteristics - AGP
TA = 0 - 70C; VDD=VDDL=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
12
TYP
24.19
23.08
MAX UNITS
1
Output Impedance
RDSP2B
VO=VDD*(0.5)
55
55
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN2B
VO=VDD*(0.5)
IOH = -28 mA
IOL = 23 mA
VOH = 2.0 V
VOL = 0.8 V
12
Ω
V
VOH1
VOL1
IOH1
IOL1
2.4
0.4
-40
V
mA
mA
41
45
tr1
VOL = 0.4 V, VOH = 2.4 V
1.3
2
ns
Fall Time1
Duty Cycle1
tf1
dt1
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1.4
48
2
ns
%
ps
ps
ps
55
Skew window1
tsk1
VT = 1.5 V
100
120
500
250
250
850
tjcyc-cyc1
tjcyc-cyc1
Jitter Cyc-Cyc, AGP(1:2)
VT = 1.5 V
VT = 1.5 V
Jitter Cyc-Cyc, AGP_F
1Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF, 48MHz
TA = 0 - 70C; VDD = VDDL = 3.3V +/-5%; CL = 10 - 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
20
TYP
47
MAX UNITS
1
Output Impedance
RDSP2B
VO=VDD*(0.5)
60
60
Ω
1
Output Impedance
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time1
RDSN2B
VO=VDD*(0.5)
IOH = -16 Ma
IOL = 9 mA
20
44
Ω
V
VOH5
VOL5
IOH5
IOL5
2.4
0.4
-22
V
VOH = 2.0 V
VOL = 0.8 V
mA
mA
16
45
1
tr5
VOL = 0.4 V, VOH = 2.4 V
2.3
2.3
50
4.0
4.0
55
1
ns
ns
%
ns
Fall Time1
Duty Cycle1
1
tf5
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
1
dt5
1
VT = 1.5 V
REF Jitter, Cyl-to-Cyl
0.7
tj1s5
1Guaranteed by design, not 100% tested in production.
9
ICS9248-131
Shared Pin Operation -
Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is usedꢀ With no jumper is installed
the pin will be pulled highꢀ With the jumper in place the pin
will be pulled lowꢀ If programmability is not necessary, than
only a single resistor is necessaryꢀThe programming resistors
should be located close to the series termination resistor to
minimize the current loop areaꢀ It is more important to locate
the series termination resistor close to the driver than the
programming resistorꢀ
The I/O pins designated by (input/output) on the serve as
dual signal functions to the deviceꢀ During initial power-up,
they act as input pinsꢀ The logic level (voltage) that is present
on these pins at this time is read and stored into a 5-bit
internal data latchꢀ At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output functionꢀ In
this mode the pins produce the specified buffered clocks to
external loadsꢀ
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potentialꢀ A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating periodꢀ
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
10
ICS9248-131
General I2C serial interface information
The information in this section assumes familiarity with I2C programmingꢀ
For more information, contact ICS for an I2C programming application noteꢀ
How to Write:
Controller (host) sends a start bitꢀ
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
How to Read:
Controller (host) will send start bitꢀ
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
ICS clock will acknowledge each byte one at a timeꢀ
Controller (host) sends a Stop bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
How to Read:
Start Bit
Controller (Host)
ICS (Slave/Receiver)
Address
Start Bit
D2(H)
Address
D3(H)
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Dummy Command Code
ACK
Byte Count
Dummy Byte Count
Byte 0
ACK
ACK
ACK
ACK
ACK
ACK
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
ACK
Stop Bit
Stop Bit
Notes:
1ꢀ
The ICS clock generator is a slave/receiver, I2C componentꢀ It can read back the data stored in the latches for verificationꢀ
Read-BackwillsupportIntelPIIX4"Block-Read"protocolꢀ
2ꢀ
3ꢀ
4ꢀ
5ꢀ
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3ꢀ3V logic levelsꢀ
The data byte format is 8 bit bytesꢀ
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controllerꢀ The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferredꢀ The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytesꢀ The data is loaded until a Stop sequence is issuedꢀ
6ꢀ
At power-on, all registers are set to a default condition, as shownꢀ
11
ICS9248-131
AGP_STOP# Timing Diagram
AGP_STOP# is an asychronous input to the clock synthesizerꢀ It is used to turn off the AGP clocksꢀ for low power operationꢀ
AGP_STOP# is synchronized by the ICS9248-131ꢀ The AGPCLKs will always be stopped in a low state and start in such a
manner that guarantees the high pulse width is a full pulseꢀAGPCLK on latency is less thanAGPCLK andAGPCLK off latency
is less than 4AGPCLKsꢀ This function is available only with MODE pin latched lowꢀ
Notes:
1ꢀ All timing is referenced to the internal CPUCLKꢀ
2ꢀ AGP_STOP# is an asynchronous input and metastable conditions may existꢀ
This signal is synchronized to the CPUCLKs inside the ICS9248-131ꢀ
3ꢀ All other clocks continue to run undisturbedꢀ
4ꢀ PD# and PCI_STOP# are shown in a high (true) stateꢀ
5ꢀ Only applies if MODE pin latched 0 at power upꢀ
12
ICS9248-131
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizerꢀ It is used to turn off the CPU clocks for low power operationꢀ
CPU_STOP# is synchronized by the ICS9248-131ꢀ The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100
CPU clocksꢀAll other clocks will continue to run while the CPU clocks are disabledꢀ The CPU clocks will always be stopped in
a low state and start in such a manner that guarantees the high pulse width is a full pulseꢀ CPU clock on latency is less than 4
CPU clocks and CPU clock off latency is less than 4 CPU clocksꢀ
INTERNAL
CPUCLK
PCICLK
CPU_STOP#
PCI_STOP# (High)
CPUCLK,
AGP
SDRAM
Notes:
1ꢀ All timing is referenced to the internal CPU clockꢀ
2ꢀ CPU_STOP# is an asynchronous input and metastable conditions may existꢀ This signal is synchronized
to the CPU clocks inside the ICS9248-131ꢀ
3ꢀ All other clocks continue to run undisturbedꢀ (including SDRAM outputs)ꢀ
13
ICS9248-131
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-131ꢀ It is used to turn off the PCICLK clocks for low power operationꢀ
PCI_STOP# is synchronized by the ICS9248-131 internallyꢀTheminimumthatthePCICLK clocksareenabled(PCI_STOP#
high pulse) is at least 10 PCICLK clocksꢀ PCICLK clocks are stopped in a low state and started with a full high pulse width
guaranteedꢀ PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clockꢀ
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 deviceꢀ)
2ꢀ PCI_STOP# is an asynchronous input, and metastable conditions may existꢀ This signal is required to be synchronized
inside the ICS9248 deviceꢀ
3ꢀ All other clocks continue to run undisturbedꢀ
4ꢀ CPU_STOP# is shown in a high (true) stateꢀ
14
ICS9248-131
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the partꢀ PD# is
an asynchronous active low inputꢀ This signal needs to be synchronized internal to the device prior to powering down the clock
synthesizerꢀ
Internal clocks are not running after the device is put in power downꢀ When PD# is active low all clocks need to be driven to a
low value and held prior to turning off the VCOs and crystalꢀ The power up latency needs to be less than 3 mSꢀ The power down
latency should be as short as possible but conforming to the sequence requirements shown belowꢀ PCI_STOP# and CPU_STOP#
are considered to be don't cares during the power down operationsꢀ The REF and 48MHz clocks are expected to be stopped in
the LOW state as soon as possibleꢀ Due to the state of the internal logic, stopping and holding the REF clock outputs in the
LOW state may require more than one clock cycle to completeꢀ
PD#
CPUCLK
AGP
PCICLK
VCO
Crystal
Notes:
1ꢀ All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-131 device)ꢀ
2ꢀ As shown, the outputs Stop Low on the next falling edge after PD# goes lowꢀ
3ꢀ PD# is an asynchronous input and metastable conditions may existꢀ This signal is synchronized inside this partꢀ
4ꢀ The shaded sections on the VCO and the Crystal signals indicate an active clockꢀ
5ꢀ Diagrams shown with respect to 133MHzꢀ Similar operation when CPU is 100MHzꢀ
15
ICS9248-131
SYMBOL
In Millimeters
In Inc hes
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
2.794
0.406
0.343
0.254
MIN
.095
.008
.008
.005
MAX
.110
.016
.0135
.010
A
A1
b
2.413
0.203
0.203
0.127
c
SEE VARIATIONS
SEE VARIATIONS
D
E
10.033
7.391
10.668
7.595
.395
.291
.420
.299
E1
e
0.635 BASIC
0.025 BASIC
h
0.381
0.508
0.635
1.016
.015
.020
.025
.040
L
SEE VARIATIONS
SEE VARIATIONS
N
0°
8°
0°
8°
α
VARIATIONS
N
D mm.
D (inch)
MIN
MAX
MIN
MAX
9.652
28
34
48
56
64
9.398
11.303
15.748
18.288
20.828
.370
.445
.620
.720
.820
.380
.455
.630
.730
.830
11.557
16.002
18.542
21.082
J E DE C MO- 118
6/ 1/ 00
DOC# 10-0034
REVB
Ordering Information
ICS9248yF-131-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
16
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