843031AGILFT [IDT]
Clock Generator, 350MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8;
| 型号： | 843031AGILFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 350MHz, PDSO8, 4.40 X 3 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-8 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总14页 (文件大小：236K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
FemtoClock Crystal-to-3.3V LVPECL
ICS843031I
Clock Generator
DATA SHEET
GENERAL DESCRIPTION
FEATURES
The ICS843031I is a 1 Gigabit Ethernet Clock Generator. The • One differential 3.3V LVPECL output
ICS843031I can synthesize 1 Gigabit Ethernet, SONET, or Serial
• Crystal oscillator interface designed for 18pF parallel resonant
crystals
ATA reference clock frequencies with the appropriate choice of
crystal and output divider. The ICS843031I has excellent phase
jitter performance and is packaged in a small 8-pin TSSOP, making
it ideal for use in systems with limited board space.
• Output frequency range: 290MHz - 350MHz
• VCO frequency range: 580MHz - 700MHz
• RMS phase jitter @312.5MHz (1.875MHz - 20MHz):
0.475ps (typical)
RMS phase jitter @318.75MHz (1.875MHz - 20MHz):
0.475ps (typical)
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
FREQUENCY TABLE
Inputs
Crystal Frequency (MHz)
25.92
Output Frequency
M/N Ratio (Multiplier)
(MHz)
12
12
12
311.04
312.5
26.04166
26.5625
318.75
BLOCK DIAGRAM
PIN ASSIGNMENT
VCC
XTAL_OUT
XTAL_IN
VEE
Q0
1
2
3
4
8
7
6
5
nQ0
VCC
XTAL_IN
PWR_DN
nQ0
Q0
Phase
VCO
OSC
÷2
Detector
XTAL-OUT
ICS843031I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
÷24
(fixed)
G Package
Top View
PWR_DN
ICS843031AGI REVISION A NOVEMBER 3, 2011
1
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 6
VCC
Power
Input
Power supply pin.
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
2, 3
4
VEE
Power
Input
Negative supply pin.
Output state control input. High impedance when LOW (oscillator
stops). LVCMOS/LVTTL interface levels.
5
PWR_DN
nQ0, Q0
Pullup
7, 8
Output
Differential clock outputs. LVPECL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characterristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
RPULLUP
51
kΩ
ICS843031AGI REVISION A NOVEMBER 3, 2011
2
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ 101.7°C/W (0 mps)
JA
Storage Temperature, T
-65°C to 150°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
VCC Power Supply Voltage
Test Conditions
Minimum
Typical
Maximum Units
3.135
3.3
3.465
105
<1
V
PWR_DN = 1
PWR_DN = 0
mA
mA
IEE
Power Supply Current
TABLE 3B. LVCMOS/LVTTLDC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VCC + 0.3
V
V
Input Low Voltage
-0.3
0.8
5
Input High Current PWR_DN
Input Low Current PWR_DN
VCC = VIN = 3.465V
μA
μA
IIL
VCC = 3.465V, VIN = 0V
-150
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 1.4
VCC - 2.0
0.6
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
ICS843031AGI REVISION A NOVEMBER 3, 2011
3
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
12
40
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
fOUT
Output Frequency
290
350
MHz
ps
312.5MHz, Integration Range:
1.875MHz to 20MHz
318.75MHz, Integration Range:
1.875MHz to 20MHz
0.475
0.475
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
200
46
600
54
ps
%
NOTE 1: Please refer to the Phase Noise Plot.
ICS843031AGI REVISION A NOVEMBER 3, 2011
4
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 312.5MHZ
0
-10
-20
-30
1 Gigabit Ethernet Filter
312.5MHz
-40
-50
RMS Phase Jitter (Random)
-60
1.875Mhz to 20MHz = 0.475ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding 1
Gigabit Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 318.75MHZ
0
-10
-20
1 Gigabit Ethernet Filter
-30
-40
-50
318.75MHz
RMS Phase Jitter (Random)
-60
-70
-80
1.875Mhz to 20MHz = 0.475ps (typical)
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding 1
Gigabit Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
ICS843031AGI REVISION A NOVEMBER 3, 2011
5
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
SCOPE
VCC
Qx
LVPECL
Phase Noise Mask
nQx
VEE
Offset Frequency
f1
f2
-1.3V ± 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0
80%
80%
tR
Q0
VSWING
20%
tPW
tPERIOD
Clock
Outputs
20%
tF
tPW
odc =
x 100%
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
ICS843031AGI REVISION A NOVEMBER 3, 2011
6
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
CRYSTAL INPUT INTERFACE
The ICS843031I has been characterized with 18pF parallel 18pF parallel resonant crystal and were chosen to minimize
the ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 1 below were determined using a 26.04167MHz,
XTAL_OUT
XTAL_IN
C1
12p
X1
18pF Parallel Crystal
C2
12p
Figure 1. CRYSTAL INPUt INTERFACE
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termi-
nation for LVPECL outputs. The two different layouts men-
tioned are recommended only as guidelines.
designed to drive 50Ω transmission lines.Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 2A and
2B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 2A. LVPECL OUTPUT TERMINATION
ICS843031AGI REVISION A NOVEMBER 3, 2011
FIGURE 2B. LVPECL OUTPUT TERMINATION
©2011 Integrated Device Technology, Inc.
7
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843031I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843031I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_TYP = 3.465V * 105mA = 363.83mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 363.8mW + 30mW = 393.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.394W * 90.5°C/W = 120.65°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION
θJA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
ICS843031AGI REVISION A NOVEMBER 3, 2011
8
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
- 0.9V
CC_MAX
OUT
OH_MAX
)
= 0.9V
OH_MAX
(V
- V
CC_MAX
For logic low, V = V
= V
- 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
- (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
- (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
ICS843031AGI REVISION A NOVEMBER 3, 2011
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©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
89.8°C/W
TRANSISTOR COUNT
The transistor count for ICS843031I is: 2360
ICS843031AGI REVISION A NOVEMBER 3, 2011
10
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
ICS843031AGI REVISION A NOVEMBER 3, 2011
11
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
Shipping
Packaging
Marking
Package
Temperature
843031AGI
843031AGIT
843031AGILF
843031AGILFT
031AI
031AI
8 lead TSSOP
8 lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
2500 tape & reel
tube
031AIL
031AIL
8 lead "Lead-Free" TSSOP
8 lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any
patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change
any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
ICS843031AGI REVISION A NOVEMBER 3, 2011
12
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
REVISION HISTORY SHEET
Rev
Table
T9
Page
Description of Change
Date
1
12
Features Section - deleted duplicate phase jitter bullet.
Ordering Information Table - deleted ICS prefix from part order number.
Added LF marking.
A
11/3/2011
Updated header/footer with IDT logo.
ICS843031AGI REVISION A NOVEMBER 3, 2011
13
©2011 Integrated Device Technology, Inc.
ICS843031I Data Sheet
FEMTOCLOCK® CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
www.IDT.com
6024 Silver Creek Valley Road
San Jose, CA 95138
Sales
Technical Support
netcom@idt.com
+480-763-2056
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion.All information
in this document, including descriptions of product features and performace, is subject to change without notice. Performance specifications and the operating parameters of the described products are
determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any
kind, whether express or implied, including, but not limited to, the suitablity of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property
rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users.
Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Techology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or
their respective third party owners.
Copyright 2011.All rights reserved.
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