8V49NS0312_17_技术文档

®

FemtoClock NG Clock Generator

8V49NS0312

Datasheet

with 4 Dividers

Description

The 8V49NS0312 is a Clock Generator with four output dividers:

three integer and one that is either integer or fractional. When used

with an external crystal, the 8V49NS0312 generates

Features

▪ Eleven differential LVPECL, LVDS outputs with programmable

voltage swings

▪ One LVCMOS output

high-performance timing geared towards the communications and

datacom markets, especially for applications that demand extremely

low phase noise, such as 10, 40, and 100GE.

— Input reference maybe bypassed to this output

▪ The clock input operates in full differential mode (LVDS, LVPECL)

or single-ended LVCMOS mode

The 8V49NS0312 provides versatile frequency configurations and

output formats and is optimized to deliver excellent phase noise

performance. The device delivers an optimum combination of high

clock frequency and low phase noise performance, combined with

high power supply noise rejection.

▪ Driven from a crystal or differential clock input

▪ 2.4-2.5GHz PLL frequency range supports Ethernet, SONET and

CPRI frequency plans

▪ Four Integer output dividers with a range of output divide ratios

(see Table 7)

The 8V49NS0312 supports two types of output levels: LVPECL or

LVDS on eleven of its outputs. In addition, there is a single LVCMOS

output that has the option of providing a generated clock or acting as

a reference bypass output.

▪ One Fractional Output divider can generate any desired output

frequency

▪ Support of output power-down

▪

Excellent clock output phase noise

The device can be configured to deliver specific output

configurations under pin control only or additional configurations

through an I²C serial interface.

Offset

Output Frequency

Single-side Band Phase Noise

100kHz

156.25MHz

-143dBc/Hz

▪ Phase Noise RMS, 156.25MHz, 12kHz to 20MHz integration

It is offered in a lead-free (RoHS6) 64-pin VFQFN package.

range: 110fs (maximum)

▪ Select configurations may be controlled via the use of control

input pins without need for serial port access

▪ LVCMOS compatible I²C serial interface gives access to

additional configurations either alone or in combination with the

control input pins

▪ Single 3.3V supply voltage

▪ Lead-free (RoHS 6) 64-pin VFQFN packaging

▪ -40°C to 85°C ambient operating temperature

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November 14, 2017

8V49NS0312 Datasheet

Block Diagram

Figure 1: 8V49NS0312 Block Diagram

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November 14, 2017

8V49NS0312 Datasheet

Pin Assignment

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

V_CCOB

QB0

nQB0

QB1

nQB1

QB2

nQB2

QB3

nQB3

V_CCOB

ND[0]

ND[1]

V_CCOD

QD1

V_CCOA

QA0

nQA0

QA1

nQA1

QA2

nQA2

QA3

nQA3

V_CCOA

V_CCOC

QC0

nQC0

QC1

3

4

5

6

7

8

8V49NS0312

9

10

11

12

13

14

15

16

nQC1

V_CCOC

QD0

nQD0

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64-pin, 9mm x 9mm VFQFN Package

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November 14, 2017

8V49NS0312 Datasheet

Pin Description and Pin Characteristic Tables

Table 1: Pin Descriptions^a

Number

Name

Type

Description

1

V_CCOB

Power

Output

Power

Power Supply Voltage for Output Bank B (3.3V).

2

3

QB0

nQB0

QB1

Differential device clock output pair. LVPECL or LVDS with configurable amplitude.

4

5

nQB1

QB2

6

7

nQB2

QB3

8

9

nQB3

V_CCOB

10

Power Supply Voltage for Output Bank B (3.3V).

Pullup /

Pulldown

11

12

ND[0]

ND[1]

Input

Control Inputs for Output Bank D. 3-level signals. Refer to Table 12.

Pullup /

Pulldown

Control Inputs for Output Bank D. 3-level signals. Refer to Table 12.

13

14

15

16

V_CCOD

QD1

Power

Output

Power Supply Voltage for Output Bank D (3.3V).

Single-ended output clock. LVCMOS output levels.

QD0

Differential device clock output pair. LVPECL or LVDS with configurable amplitude.

nQD0

Pullup /

Pulldown

17

18

19

NB[0]

NB[1]

NC[0]

Input

Control Inputs for Output Bank B. 3-level signals. Refer to Table 10.

Control Inputs for Output Bank C. 3-level signals. Refer to Table 11.

Pullup /

Pulldown

Pullup /

Pulldown

Pullup /

Pulldown

20

21

22

NC[1]

V_{CCA_IN1}

NA[1]

Input

Power

Input

Control Inputs for Output Bank C. 3-level signals. Refer to Table 11.

Analog Power Supply Voltage for PLL (3.3V).

Pullup /

Pulldown

Control Inputs for Output Bank A. 3-level signals. Refer to Table 9.

Internal VCO bias decoupling capacitor. Use a 4.7µF capacitor between the

CAP_BIASterminal and V_EE.

23

24

25

CAP_BIAS

V_{CCA_IN2}

CR

Analog

Power

Analog

Analog Power Supply Voltage for VCO (3.3V).

Internal VCO regulator decoupling capacitor. Use a 1µF capacitor between the CR

and the V_CCAterminals.

Internal VCO regulator decoupling capacitor. Use a 4.7µF capacitor between the

CAP_REGterminal and V_EE.

26

CAP_REG

Analog

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8V49NS0312 Datasheet

Table 1: Pin Descriptions^aCont.

Number

Name

Type

Description

27

LFFR

Analog

Output

Ground return path pin for the PLL loop filter.

Loop filter/charge pump output for the FemtoClock NG PLL. Connect to the external

loop filter.

28

LFF

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

V_CCA

nc

Power

-

Analog Power Supply Voltage for VCO (3.3V).

No connect. Do not use.

-

V_{CC_CP}

ICP

Power

Analog

Power

Output

Power

Output

Power

Analog Power Supply Voltage for PLL charge pump (3.3V).

Charge pump current input for PLL. Connect to LFF pin (28).

Power Supply Voltage for Output Bank C (3.3V).

V_CCOC

nQC1

QC1

Differential device clock output pair. LVPECL or LVDS with configurable amplitude.

nQC0

QC0

V_CCOC

V_CCOA

nQA3

QA3

Power Supply Voltage for Output Bank C (3.3V).

Power Supply Voltage for Output Bank A (3.3V).

Differential device clock output pair. LVPECL or LVDS with configurable amplitude.

nQA2

QA2

nQA1

QA1

nQA0

QA0

V_CCOA

Power Supply Voltage for Output Bank A (3.3V).

Selects Input Reference source. LVCMOS interface levels.

49

REF_SEL

Input

Pulldown 0 = Crystal input on pins OSCI, OSCO (default)

1 = Reference clock input on pins CLK, nCLK

50

51

52

53

V_{CC_CK}

nCLK

CLK

Power

Input

Power Supply Voltage for input CLK, nCLK (3.3V).

Pullup/

Inverting differential clock input. Internal resistor bias to V_{CC_CK.}

Pulldown

Pulldown Non-inverting differential clock input.

Pullup /

Pulldown

FIN[1]

Control Inputs for Input Reference Frequencies. 3-level signals. Refer to Table 5.

Pullup /

Pulldown

54

55

FIN[0]

Input

Control Inputs for Input Reference Frequencies. 3-level signals. Refer to Table 5.

Crystal oscillator circuit decoupling capacitor. Use a 4.7µF capacitor between the

CAP_XTALand the V_EEterminals.

CAP_XTAL

Analog

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8V49NS0312 Datasheet

Table 1: Pin Descriptions^aCont.

Number

Name

Type

Description

56

OSCO

Output

Input

Crystal oscillator interface.

57

58

OSCI

Crystal oscillator interface.

V_{CCA_XT}

Power

Analog Power Supply Voltage for the Crystal Oscillator (3.3V).

Pullup /

Pulldown

59

NA[0]

Input

Control Inputs for Output Bank A. 3-level signals. Refer to Table 9.

60

61

62

63

RES

SDATA

SCLK

Analog

I/O

Connect a 2.8 k (1%) resistor to V_EEfor output current calibration.

I²C data Input/Output: LVCMOS interface levels. Open Drain Pin.

I²C clock input. LVCMOS interface levels.

Pullup

Input

Power

V_{CC_SP}

Power Supply Voltage for the I²C port (3.3V).

Lock status output. LVCMOS interface levels.

Logic Low = PLL not locked

64

LOCK

Output

Logic High = PLL locked

ePad

V_EE

Power

Negative supply. Exposed pad must be connected to ground

a. Pulldown and Pullup refer to internal input resistors. See Table 2, Input Characteristics, for typical values.

Table 2: Input Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C_IN

Input Capacitance^a

3.5

pF

R_PULLDOWN

R_PULLUP

Input Pulldown Resistor

Input Pullup Resistor

51

k

a. This specification does not apply to OSCI and OSCO pins.

Table 3: Output Characteristics

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

LOCK

QD1

20



Output

Impedance

R_OUT

V_CC^a= 3.3V ± 5%

30



a. V_CCdenotes V_{CC_SP,}V_CCOD.

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8V49NS0312 Datasheet

Principles of Operation

The 8V49NS0312 can be locked to either an input reference clock or a 10MHz to 50MHz fundamental-mode crystal and generate a wide range

of synchronized output clocks. Lock status may be monitored via the LOCK pin.

It could be used for example in either the transmit or receive path of Synchronous Ethernet or SONET/SDH equipment.

The 8V49NS0312 accepts a differential or single-ended input clock ranging from 5MHz up to 1GHz. It generates up to twelve output clocks

with up to four different output frequencies, ranging from 10.91MHz up to 2.5GHz.

The device outputs are divided into 4 output banks. Each bank supports conversion of the input frequency to a different output frequency: one

independent or integer-related output frequency on Bank D (QD[0:1]) and three more integer-related frequencies on Bank A (QA[0:3]), Bank B

(QB[0:3]) and Bank C (QC[0:1]). All outputs within a bank will have the same frequency.

The device is programmable through an I²C serial interface or control input pins.

Pin versus Register Control

The 8V49NS0312 can be configured by the use of input control pins and/or over an I²C serial port. The pins / registers used to control each

function are shown in Table 4. At power-up, control of each function is via the control input pins. Access over the serial port can change each

function individually to be controlled by registers. This allows for any mixture of register or pin control. However any of the indicated functions

can only be controlled by register or by pin at any given time, not by both. Use of register control will allow access to a wider range of

configuration options, but values are lost on power-down.

Table 4: Control of Specific Functions

Function

Control Select Bit

Control Input Pins

Register Fields Affected

Prescaler & PLL

Feedback Divider

FIN_CTL

FIN[1:0]

PS[5:0], FDP M[8:0]

NA_DIV, PD_A, EN_A,

PD_QAx, STY_QAx,

AMP_QAx[1:0]

Bank A

Divider & Output Type

NA_CTL

NB_CTL

NC_CTL

NA[1:0]

NB[1:0]

NC[1:0]

NB_DIV, PD_B, EN_B,

PD_QBx, STY_QBx,

AMP_QBx[1:0]

Bank B

Divider & Output Type

NC_DIV, PD_C, EN_C,

PD_QCx, STY_QCx,

AMP_QCx[1:0]

Bank C

Divider & Output Type

ND[5:0], ND_FINT[3:0],

ND_FRAC[23:0],

ND_DIVF[1:0], ND_SRC[1:0],

PD_D, EN_D, PD_QDx,

STY_QD0, AMP_QD0[1:0]

Bank D

Divider & Output Type

ND_CTL

ND[1:0]

Changes to the control input pins while the part is active are allowed, but can not be guaranteed to be glitch-free. It is recommended that any

such changes be performed by disabling the outputs using the I²C-accessible registers, then re-enabling once changes are completed. Also,

the output dividers, which are synchronized on power-up will not be re-synchronized without an explicit access to the INIT_CLK register bit

over the I²C interface.

Any change to the output dividers performed over the I²C interface must be followed by an assertion of the INIT_CLK register bit to force the

loading of the new divider values, as well as to synchronize the output dividers.

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November 14, 2017

8V49NS0312 Datasheet

Input Clock Selection (REF_SEL)

The 8V49NS0312 needs to be provided with an input reference frequency either from its crystal input pins (OSCI, OSCO) or its reference clock

input pins (CLK, nCLK). The REF_SEL input pin controls which source is used.

The crystal input on the 8V49NS0312 is capable of being driven by a parallel-resonant, fundamental mode crystal with a frequency of 10MHz

to 50MHz.

The crystal input also supports being driven by a single-ended crystal oscillator or reference clock, but only a frequency from 10MHz to 50MHz

may be used on these pins.

The reference clock input accepts clocks with frequencies ranging from 5MHz up to 1GHz. Each input can accept LVPECL, LVDS, LVHSTL,

HCSL or LVCMOS inputs using 2.5V or 3.3V logic levels as shown in the Applications Information section of this datasheet.

Prescaler and PLL Configuration

When the input frequency (f_IN), whether generated by a crystal or clock input is known, and the desired PLL operating frequency has been

determined, several constraints need to be met:

▪ The Phase / Frequency Detector operating frequency (f_PFD) must be within the specified limits shown in Table 28. This is controlled by

selecting an appropriate doubler (FDP) and prescaler (PS) value. If multiple values are possible, a higher f_PFDwill provide better phase

noise performance.

▪ The VCO operating frequency (f_VCO) must be within the specified limits shown in Table 28. This is controlled by selecting an appropriate

PLL feedback Divider (M) value. Note that it may be necessary to chose a different prescaler value if the limits can not be met by the

available values of M. It may also be necessary to select an appropriate input frequency value.

Several preset configurations may be selected directly from the FIN[1:0] control input pins. These configurations are based on a particular

input frequency f_INand a particular f_VCO(see Table 5). These selections apply whether the input frequency is provided from the crystal or

reference clock inputs

Table 5: Input Selection Control

FIN[1]

High

FIN[0]

f_IN(MHz)

38.88

38.4

f_VCO(MHz)

2488.32

2457.6

2500

High

Middle^a

Low

High

31.25

312.5

125

Middle

Low

High

2500

Middle

Low

2500

156.25

100

2500

High

2500

Low

Middle

Low

25

2500

Low

50

2500

a. A ‘middle’ voltage level is defined in Table 22. Leaving the input pin open will also

generate this level via a weak internal resistor network.

Alternatively the user may directly access the registers for M, FDP & PS over the serial interface for a wider range of options. See Table 6 for

some examples.

Inputs do not support transmission of spread-spectrum clocking sources. Since this family is intended for high-performance applications, it will

assume input reference sources to have stabilities of +100ppm or better.

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8V49NS0312 Datasheet

Table 6: PLL Frequency Control Examples

PLL Operating Frequency

(MHz)

f_IN(MHz)

25

PS

1

2

4

1

FDP

2

f_PFD(MHz)

50

M

50

32

25

20

16

25

20

16

25

20

16

64

32

2500

39.0625

50

2

78.125

100

2

2500

100

1

100

2500

125

1

125

2500

156.25

200

1

156.25

100

2500

1

2500

250

1

125

2500

312.5

400

1

156.25

100

2500

1

2500

500

1

125

2500

625

1

156.25

38.88

77.76

76.8

2500

19.44

38.88

38.4

2

2488.32

2457.6

2

PLL Loop Bandwidth

The 8V49NS0312 uses one external capacitor of fixed value to support its loop bandwidth. A fixed loop bandwidth of approximately 200kHz is

provided.

Output Divider Frequency Sources

Output dividers associated with Banks A, B & C take their input frequency directly from the PLL.

Bank D also has the option to bypass the input frequency (after mux) directly to the output.

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November 14, 2017

8V49NS0312 Datasheet

Integer Output Dividers (Banks A, B, C, and D)

The 8V49NS0312 supports four integer output dividers: one per output bank. Each integer output divider block independently supports one of

several divide ratios as shown in their respective register descriptions (Table 15, Table 16, Table 17 or Table 18). Select divide ratios can be

chosen directly from the control input pins for that particular output bank. The remaining ratios can only be selected via the serial interface.

Bank D may choose whether to use the integer divider or a separate fractional divider to generate the output.

Some example output frequencies are shown in Table 7 for the minimum f_VCO(2400MHz), the maximum f_VCO(2500MHz) and two other

common VCO frequencies. With appropriate input frequencies and configuration selections, any f_VCOand f_OUTbetween the minimum and

maximum can be generated.

Table 7: Integer Output Divider Control Examples

f_OUT(MHz)

Divide Ratio

f_VCO= 2400MHz

2400

1200

600

f_VCO= 2457.6MHz

2457.6

1228.8

614.4

f_VCO= 2488.32MHz

2488.32

1244.16

622.08

497.664

414.72

311.04

276.48

248.832

207.36

155.52

138.24

124.416

99.53

f_VCO= 2500MHz

2500

1

2

1250

4

625

5

480

491.52

409.6

500

6

400

416.667

318.75

277.78

250

8

300

307.2

9

266.667

240

273.07

245.76

204.8

10

12

16

18

20

25

32

36

40

50

64

72

80

100

128

160

200

220

200

208.333

156.25

138.889

125

150

153.6

133.333

120

136.533

122.88

98.3

96

100

75

76.8

77.76

78.125

69.444

62.5

66.667

60

68.267

61.44

69.12

62.208

49.766

38.88

48

49.152

38.4

50

37.5

33.333

30

39.063

34.722

31.25

25

34.133

30.72

34.56

31.104

24.883

19.44

24

24.576

19.2

18.75

15

19.531

15.625

11.36

15.36

15.552

12.44

12

12.29

10.91

11.17

11.31

11.36

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November 14, 2017

8V49NS0312 Datasheet

Fractional Output Divider (Bank D)

For the fractional output divider in Bank D, the output divide ratio is given by:

f_VCO

f_OUT= ------------------------------------------------------------------------------

FRAC

2²⁴





2  FINT + ----------------  FDIV





Where,

▪ FINT = Integer Part: 5, 6, ...(2⁴-1) - given by ND_FINT[3:0]

▪ FRAC = Fractional Part: 0, 1, 2, ...(2²⁴-1)- given by ND_FRAC[23:0]

▪ FDIV = post-divider: 1, 2 or 4- given by ND_DIVF[1:0]

This provides a frequency range of 20MHz to 312.5MHz.

Output Drivers

Each of the four output banks are provided with pin or register-controlled output drivers. Differential outputs may be individually selected as

LVDS, LVPECL or POWER-DOWN. When powered down, both outputs of the differential output pair will drive a logic-high level, and the

single-ended QD1output will be in Hi-Z state.

The differential outputs may individually choose one of several different output voltage swings: 350mV, 500mV or 750mV, measured

single-ended.

Note that under pin-control, all differential outputs within an output bank will assume the same configuration. Pin-control does not allow

configuration of individual outputs within a bank.

Pin Control of the Output Frequencies and Protocols

See Table 8, Table 9, Table 10, Table 11 and Table 12, for pin-control settings. All of the output frequencies assume f_VCO= 2500MHz. With

different f_VCOconfigurations, the pins may still be used to select the indicated divide ratios for each bank, but the f_OUTwill be different.

Note that the control pins do not affect the internal register values, but act directly on the output structures. So register values will not change

to match the control input pin selections.

Each output bank may be powered-up / down and enabled / disabled by register bits. In the disabled state, an output will drive a logic low level.

The default state is all outputs enabled. Pin-control does not require register access to enable the outputs. Additionally, individual outputs

within a bank may be powered up / down.

Table 8: Definition of Output Disabled / Power-down

a

b

OUTPUT CONDITION

Q_MN

nQ_MN

QD1

LOW

Hi-Z

DISABLED (register-control only)

LOW

HIGH

POWER-DOWN (pin-control or register-control)

a. Q_MNrefers to output pins QA[0:3], QB[0:3], QC[0:1] and QD0.

b. nQ_MNrefers to output pins nQA[0:3], nQB[0:3], nQC[0:1] and nQD0.

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8V49NS0312 Datasheet

Table 9: Bank A Divider/ Driver Pin-Control

Table 11: Bank C Divider/ Driver Pin-Control

(3-level control signals)

Divide

Ratio

f_OUT

(MHz)

Divide

Ratio

f_OUT

(MHz)

NA[1]

Low

NA[0]

Low

Output Type

LVPECL^a

LVPECL

POWER-DOWN^b

LVDS^c

NC[1]

Low

NC[0]

Output Type

LVPECL^a

LVPECL

POWER-DOWN^b

LVDS^c

16

156.25

125

100

25

Low

Middle

High

8

312.5

156.25

125

25

Low

Middle

High

20

Low

16

Low

25

Low

20

Middle

High

Low

100

-

Middle

High

Low

100

Middle

High

-

Middle

High

-

16

156.25

125

100

50

20

25

125

100

50

Low

LVDS

20

Low

LVDS

High

Middle

High

LVDS

25

High

Middle

High

LVDS

50

High

LVDS

50

High

LVDS

100

25

a. Under pin control, all outputs of the bank are LVPECL using 750mV output swing.

b. No active receivers should be connected to QA outputs.

a. Under pin control, all outputs of the bank are LVPECL using 750mV output swing.

b. No active receivers should be connected to QC outputs.

c. Under pin control, all outputs of the bank are LVDS using 350mV output swing.

Table 12: Bank D Divider/ Driver Pin-Control

Table 10: Bank B Divider/ Driver Pin-Control

(3-level control signals)

QD1

Output Divide

Divide

Ratio

f_OUT

(MHz)

QD0

Output Type

f_OUT

(MHz)

NB[1]

Low

NB[0]

Low

Output Type

LVPECL^a

LVPECL

ND[1] ND[0]

Type

Hi-Z

Ratio

16

20

156.25

125

Low

Middle

High

LVDS^a

LVDS

25

100

Low

Middle

High

50

Low

LVPECL

25

100

Low

18.75^b133.333

Middle

Low

LVPECL

100

25

Middle

Low

37.5^b

66.667

-

POWER-DOWN

Middle Middle POWER-DOWN^c

-

Middle

-

b

Middle High POWER-DOWN^cLVCMOS

75

100

20

1

33.333

25

Middle

High

Low

LVDS^c

LVDS

16

20

25

50

156.25

125

High

High Middle

High High

Low

LVDS

Hi-Z

125

High

Middle

High

100

d

LVCMOS

f_IN

High

50

a. Under pin control, all outputs of the bank are LVDS using 350mV output swing.

b. Generated from Fractional divider.

c. No active receivers should be connected to QD0 output.

d. This bypasses the input frequency directly to the output.

a. Under pin control, all outputs of the bank are LVPECL using 750mV output swing.

b. No active receivers should be connected to QB outputs.

c. Under pin control, all outputs of the bank are LVDS using 350mV output swing.

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November 14, 2017

8V49NS0312 Datasheet

Device Start-up and Reset Behavior

The 8V49NS0312 has an internal power-on reset (POR) circuit.The POR circuit will remain active for a maximum of 175msec after device

power-up.

While in the reset state (POR active), the device will operate as follows:

▪ All registers will return to & be held in their default states as indicated in the applicable register description.

▪ All internal state machines will be in their reset conditions.

▪ The serial interface will not respond to read or write cycles.

▪ All clock outputs will be enabled.

▪ Lock status will be cleared.

Upon the internal POR circuit expiring, the device will exit reset and begin self-configuration.

Self-configuration will consist of loading appropriate default values into each register as indicated by the control input pins and the defaults

indicated in the register descriptions.

Once the full configuration has been loaded, the device will respond to accesses on the serial port and will attempt to lock the PLL to the input

frequency and begin operation. Once the PLL is locked, all the outputs derived from it will be synchronized.

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November 14, 2017

8V49NS0312 Datasheet

Serial Control Port Description

Serial Control Port Configuration Description

The device has a serial control port capable of responding as a slave in an I²C compatible configuration at a base address of 1101100b, to

allow access to any of the internal registers for device programming or examination of internal status.

All registers are configured to have default values. See the specifics for each register for details. Default values for registers will be set after

reset by the configuration pins.

Any changes to the configuration pins will result in the appropriate register(s) being changed to reflect the new pin-controlled setup. Any such

change while the part is operating may result in glitches on output clocks, even if those particular clocks are not being reconfigured.

2

I C Mode Operation

The I²C interface is designed to fully support v1.2 of the I²C Specification for Normal and Fast mode operation. The device acts as a slave

device on the I²C bus at 100kHz or 400kHz using a fixed base address of 1101100b. The interface accepts byte-oriented block write and block

read operations. One address byte specifies the register address of the byte position of the first register to write or read. Data bytes (registers)

are accessed in sequential order from the lowest to the highest byte (most significant bit first). Read and write block transfers can be stopped

after any complete byte transfer. During a write operation, data will not be moved into the registers until the STOP bit is received, at which

point, all data received in the block write will be written simultaneously.

For full electrical I²C compliance, it is recommended to use external pull-up resistors for SDATA and SCLK. The internal pull-up resistors have

a size of 51k typical.

Current Read

S

Dev Addr + R

A

Data X

A

Data X +1

A

Data n

Data X

A

P

Sequential Read

S

Dev Addr + W

Offset Addr X

A

Sr

Dev Addr + R

A

Data X +1

A

Data n

A

P

Sequential Write

S

Dev Addr + W

Data X

A

Data X +1

A

Data n

A

P

NOTE:

S = start

from master to slave

from slave to master

Data X refers to the data at Offset Addr X,

Sr = repeated start

A = acknowledge

A = non-acknowledge

P = stop

Data X+1 refers to the data at Offset Addr +1, etc.

Figure 2: I²C Slave Read and Write Cycle Sequencing

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8V49NS0312 Datasheet

Register Description

Table 13: Register Blocks

Register Ranges Offset (Hex)

Register Block Description

Prescaler & PLL Control Registers

Reserved^a

00 - 08

09 - 0F

10 - 17

Bank A Control Registers

Bank B Control Registers

Bank C Control Registers

Bank D Control Registers

Reserved

18 - 1F

20 - 27

28 - 31

32 - 37

38 - 3C

Reserved

3D - 40

Device Control Registers

Reserved

41 - 4B

4C - 4F

Reserved

50 - FF

Reserved

a. Reserved registers should not be written to and have indeterminate read values.

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8V49NS0312 Datasheet

Table 14: Prescaler & PLL Control Register Bit Field Locations and Descriptions

Prescaler & PLL Control Register Block Field Locations

Address (Hex)

D7

D6

D5

D4

D3

D2

D1

D0

00

01

02

03

04

05

06

07

08

Rsvd

PS[5:0]

Rsvd

FDP

Rsvd

FIN_CTL

OSC_LOW

Rsvd

M[8]

M[7:0]

Rsvd

CP[4:0]

Prescaler & PLL Control Register Block Field Descriptions

Field Type Default Value Description

Prescaler - scales input frequency by the value:

00h = Reserved

Bit Field Name

PS[5:0]

R/W

000000b

01h - 7Fh = divide by the value used (e.g. 04 = divide-by-4)

Input frequency doubler:

0 = disabled

FDP

FIN_CTL

OSC_LOW

M[8:0]

1b

1 = enabled

Prescaler and PLL Configuration Control:

0b

0 = PS[5:0], FDP and M settings determined by FIN[1:0] control pins

1 = PS[5:0], FDP and M settings determined by register settings over I²C

Crystal oscillator gain control selection:

0b

0 = normal gain for crystal frequencies of 25MHz and up

1 = low gain for crystal frequencies less than 25MHz

PLL Feedback divider ratio:

019h

000h - 003h = Reserved (do not use)

004h - 1FFh = divide f_VCOby the value

PLL Charge Pump Current Control:

ICP = 200μA x (CP[4:0] + 1).

Max. charge pump current is 6.4 mA. Default setting is 5.2mA: ((25+1) x 200μA).

CP[4:0]

Rsvd

R/W

11001b

-

Reserved. Always write 0 to this bit location. Read values are not defined.

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8V49NS0312 Datasheet

Table 15: Bank A Control Register Bit Field Locations and Descriptions

Bank A Control Register Block Field Locations

Address (Hex)

D7

D6

D5

D4

D3

D2

D1

D0

10

11

12

13

14

15

16

17

Rsvd

NA[5:0]

Rsvd

PD_A

NA_CTL

PD_QA0

PD_QA1

PD_QA2

PD_QA3

Rsvd

STY_QA0

STY_QA1

STY_QA2

STY_QA3

AMP_QA0[1:0]

AMP_QA1[1:0]

AMP_QA2[1:0]

AMP_QA3[1:0]

Bank A Control Register Block Field Descriptions

Field Type Default Value Description

Divider ratio for Bank A:

Bit Field Name

Any changes made to this register will not take effect until the INIT_CLK register bit is

toggled.

00 0000b = Reserved

00 0001b = ÷1

00 0010b = ÷2

00 0011b = ÷3

00 0100b = ÷4

00 0101b = ÷5

00 0110b = ÷6

00 0111b = ÷8

00 1000b = ÷9

00 1001b = ÷10

00 1010b = ÷12

00 1011b = ÷14

00 1100b = ÷15

00 1101b = ÷16

00 1110b = ÷18

00 1111b = ÷20

01 0000b = ÷21

01 0001b = ÷22

01 0010b = ÷24

01 0011b = ÷25

01 0100b = ÷27

01 0101b = ÷28

01 0110b = ÷30

01 0111b = ÷32

01 1000b = ÷33

01 1001b = ÷35

01 1010b = ÷36

01 1011b = ÷40

01 1100b = ÷42

01 1101b = ÷44

01 1110b = ÷45

01 1111b = ÷48

10 0000b = ÷50

10 0001b = ÷54

10 0010b = ÷55

10 0011b = ÷56

10 0100b = ÷60

10 0101b = ÷64

10 0110b = ÷66

10 0111b = ÷70

10 1000b = ÷72

10 1001b = ÷80

10 1010b = ÷84

10 1011b = ÷88

10 1100b = ÷90

10 1101b = ÷96

10 1110b = ÷100

10 1111b = ÷108

11 0000b = ÷110

11 0001b = ÷112

11 0010b = ÷120

11 0011b = ÷128

11 0100b = ÷132

11 0101b = ÷140

11 0110b = ÷144

11 0111b = ÷160

11 1000b = ÷176

11 1001b = ÷180

11 1010b = ÷200

11 1011b = ÷220

11 1100b = Reserved

11 1101b = Reserved

11 1110b = Reserved

11 1111b = Reserved

NA[5:0]

R/W

0Dh

Power-down Bank A:

0 = Bank A & all QA outputs powered and operate normally

1 = Bank A & all QA outputs powered-down - no active receivers should be connected

to QA outputs. When powering-down the output bank, it is recommended to also write

a ‘1’ to the PD_QAx registers.

PD_A

R/W

0b

Bank A Configuration Control:

0 = NA[5:0], PD_A, EN_A, STY_Ax and AMP_Ax[1:0] settings determined by NA[1:0]

NA_CTL

PD_QAx

R/W

0b

control pins

1 = NA[5:0], PD_A, EN_A, STY_Ax and AMP_Ax[1:0] settings determined by register

settings over I²C

Power-down Output QAx:

0 = QAx output powered and operates normally

1 = QAx output powered-down - no active receivers should be connected to the QAx

output

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8V49NS0312 Datasheet

Bank A Control Register Block Field Descriptions

Field Type Default Value Description

Bit Field Name

Output Style for Output QAx:

0 = QAx is LVDS

STY_QAx

R/W

0b

1 = QAx is LVPECL

Output Amplitude for Output QAx (measured single-ended):

00 = 350mV

01 = 500mV

10 = 750mV

11 = Reserved

AMP_QAx[1:0]

Rsvd

R/W

00b

-

Reserved. Always write 0 to this bit location. Read values are not defined.

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8V49NS0312 Datasheet

Table 16: Bank B Control Register Bit Field Locations and Descriptions

Bank B Control Register Block Field Locations

Address (Hex)

D7

D6

D5

D4

D3

D2

D1

D0

18

19

1A

1B

1C

1D

1E

1F

Rsvd

NB[5:0]

Rsvd

PD_B

NB_CTL

PD_QB0

PD_QB1

PD_QB2

PD_QB3

Rsvd

STY_QB0

STY_QB1

STY_QB2

STY_QB3

AMP_QB0[1:0]

AMP_QB1[1:0]

AMP_QB2[1:0]

AMP_QB3[1:0]

Bank B Control Register Block Field Descriptions

Field Type Default Value Description

Divider ratio for Bank B:

Bit Field Name

Any changes made to this register will not take effect until the INIT_CLK register bit is

toggled.

00 0000b = Reserved

00 0001b = ÷1

00 0010b = ÷2

00 0011b = ÷3

00 0100b = ÷4

00 0101b = ÷5

00 0110b = ÷6

00 0111b = ÷8

00 1000b = ÷9

00 1001b = ÷10

00 1010b = ÷12

00 1011b = ÷14

00 1100b = ÷15

00 1101b = ÷16

00 1110b = ÷18

00 1111b = ÷20

01 0000b = ÷21

01 0001b = ÷22

01 0010b = ÷24

01 0011b = ÷25

01 0100b = ÷27

01 0101b = ÷28

01 0110b = ÷30

01 0111b = ÷32

01 1000b = ÷33

01 1001b = ÷35

01 1010b = ÷36

01 1011b = ÷40

01 1100b = ÷42

01 1101b = ÷44

01 1110b = ÷45

01 1111b = ÷48

10 0000b = ÷50

10 0001b = ÷54

10 0010b = ÷55

10 0011b = ÷56

10 0100b = ÷60

10 0101b = ÷64

10 0110b = ÷66

10 0111b = ÷70

10 1000b = ÷72

10 1001b = ÷80

10 1010b = ÷84

10 1011b = ÷88

10 1100b = ÷90

10 1101b = ÷96

10 1110b = ÷100

10 1111b = ÷108

11 0000b = ÷110

11 0001b = ÷112

11 0010b = ÷120

11 0011b = ÷128

11 0100b = ÷132

11 0101b = ÷140

11 0110b = ÷144

11 0111b = ÷160

11 1000b = ÷176

11 1001b = ÷180

11 1010b = ÷200

11 1011b = ÷220

11 1100b = Reserved

11 1101b = Reserved

11 1110b = Reserved

11 1111b = Reserved

NB[5:0]

R/W

0Dh

Power-down Bank B:

0 = Bank B & all QB outputs powered and operate normally

1 = Bank B & all QB outputs powered-down - no active receivers should be connected

to QB outputs

PD_B

R/W

0b

Bank A Configuration Control:

0 = NB[5:0], PD_B, EN_B, STY_Bx and AMP_Bx[1:0] settings determined by NB[1:0]

control pins

NB_CTL

1 = NB[5:0], PD_B, EN_B, STY_Bx and AMP_Bx[1:0] settings determined by register

settings over I²C

Power-down Output QBx:

0 = QBx output powered and operates normally

PD_QBx

R/W

0b

1 = QBx output powered-down - no active receivers should be connected to the QBx

output. When powering-down the output bank, it is recommended to also write a ‘1’ to

the PD_QBx registers.

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8V49NS0312 Datasheet

Bank B Control Register Block Field Descriptions

Field Type Default Value Description

Bit Field Name

Output Style for Output QBx:

0 = QBx is LVDS

STY_QBx

R/W

0b

1 = QBx is LVPECL

Output Amplitude for Output QBx (measured single-ended):

00 = 350mV

01 = 500mV

10 = 750mV

11 = Reserved

AMP_QBx[1:0]

Rsvd

R/W

00b

-

Reserved. Always write 0 to this bit location. Read values are not defined.

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8V49NS0312 Datasheet

Table 17: Bank C Control Register Bit Field Locations and Descriptions

Bank C Control Register Block Field Locations

Address (Hex)

D7

D6

D5

D4

D3

D2

D1

D0

20

21

22

23

24

25

26

27

Rsvd

NC[5:0]

Rsvd

PD_C

NC_CTL

PD_QC0

PD_QC1

Rsvd

STY_QC0

STY_QC1

AMP_QC0[1:0]

AMP_QC1[1:0]

Rsvd

Bank C Control Register Block Field Descriptions

Field Type Default Value Description

Divider ratio for Bank C:

Bit Field Name

Any changes made to this register will not take effect until the INIT_CLK register bit is

toggled.

00 0000b = Reserved

00 0001b = ÷1

00 0010b = ÷2

00 0011b = ÷3

00 0100b = ÷4

00 0101b = ÷5

00 0110b = ÷6

00 0111b = ÷8

00 1000b = ÷9

00 1001b = ÷10

00 1010b = ÷12

00 1011b = ÷14

00 1100b = ÷15

00 1101b = ÷16

00 1110b = ÷18

00 1111b = ÷20

01 0000b = ÷21

01 0001b = ÷22

01 0010b = ÷24

01 0011b = ÷25

01 0100b = ÷27

01 0101b = ÷28

01 0110b = ÷30

01 0111b = ÷32

01 1000b = ÷33

01 1001b = ÷35

01 1010b = ÷36

01 1011b = ÷40

01 1100b = ÷42

01 1101b = ÷44

01 1110b = ÷45

01 1111b = ÷48

10 0000b = ÷50

10 0001b = ÷54

10 0010b = ÷55

10 0011b = ÷56

10 0100b = ÷60

10 0101b = ÷64

10 0110b = ÷66

10 0111b = ÷70

10 1000b = ÷72

10 1001b = ÷80

10 1010b = ÷84

10 1011b = ÷88

10 1100b = ÷90

10 1101b = ÷96

10 1110b = ÷100

10 1111b = ÷108

11 0000b = ÷110

11 0001b = ÷112

11 0010b = ÷120

11 0011b = ÷128

11 0100b = ÷132

11 0101b = ÷140

11 0110b = ÷144

11 0111b = ÷160

11 1000b = ÷176

11 1001b = ÷180

11 1010b = ÷200

11 1011b = ÷220

11 1100b = Reserved

11 1101b = Reserved

11 1110b = Reserved

11 1111b = Reserved

NC[5:0]

R/W

0Dh

Power-down Bank C:

0 = Bank C & all QC outputs powered and operate normally

1 = Bank C & all QC outputs powered-down - no active receivers should be connected

to QC outputs

PD_C

R/W

0b

Bank C Configuration Control:

0 = NC[5:0], PD_C, EN_C, STY_Cx and AMP_Cx[1:0] settings determined by NC[1:0]

control pins

NC_CTL

1 = NC[5:0], PD_C, EN_C, STY_Cx and AMP_Cx[1:0] settings determined by register

settings over I²C

Power-down Output QCx:

0 = QCx output powered and operates normally

PD_QCx

R/W

0b

1 = QCx output powered-down - no active receivers should be connected to the QCx

output. When powering-down the output bank, it is recommended to also write a ‘1’ to

the PD_QCx registers.

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8V49NS0312 Datasheet

Bank C Control Register Block Field Descriptions

Field Type Default Value Description

Bit Field Name

Output Style for Output QCx:

0 = QCx is LVDS

STY_QCx

R/W

0b

1 = QCx is LVPECL

Output Amplitude for Output QCx (measured single-ended):

00 = 350mV

01 = 500mV

10 = 750mV

11 = Reserved

AMP_QCx[1:0]

Rsvd

R/W

00b

-

Reserved. Always write 0 to this bit location. Read values are not defined.

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8V49NS0312 Datasheet

Table 18: Bank D Control Register Bit Field Locations and Descriptions

Bank D Control Register Block Field Locations

Address (Hex)

D7

D6

D5

D4

D3

D2

D1

D0

28

29

2A

2B

2C

2D

2E

2F

30

31

ND_FRAC[7:0]

ND_FRAC[15:8]

ND_FRAC[23:16]

Rsvd

ND_FINT[3:0]

Rsvd

ND[5:0]

ND_DIVF[1:0]

ND_DIV

ND_SRC

ND_CTL

PD_D

Rsvd

PD_QD0

PD_QD1

Rsvd

STY_QD0

AMP_QD0[1:0]

Rsvd

Bank D Control Register Block Field Descriptions

Field Type Default Value Description

Bit Field Name

Fractional portion of divider ratio for fractional divider for Bank D:

Fraction used in divide ratio = ND_FRAC[23:0] / 2²⁴

ND_FRAC[23:0]

R/W

600000h

Integer portion of divider ratio for fractional divider for Bank D:

0h - 4h= Reserved

ND_FINT[3:0]

R/W

1001b

5h - Fh = divide by the value used (e.g. 5 = divide-by-5)

Divider ratio for Bank D:

Any changes made to this register will not take effect until the INIT_CLK register bit is

toggled.

00 0000b = Reserved

00 0001b = ÷ 1

00 0010b = ÷ 2

00 0011b = ÷ 3

00 0100b = ÷ 4

00 0101b = ÷ 5

00 0110b = ÷ 6

00 0111b = ÷ 8

00 1000b = ÷ 9

00 1001b = ÷ 10

00 1010b = ÷ 12

00 1011b = ÷ 14

00 1100b = ÷ 15

00 1101b = ÷ 16

00 1110b = ÷ 18

00 1111b = ÷ 20

01 0000b = ÷ 21

01 0001b = ÷ 22

01 0010b = ÷ 24

01 0011b = ÷ 25

01 0100b = ÷ 27

01 0101b = ÷ 28

01 0110b = ÷ 30

01 0111b = ÷ 32

01 1000b = ÷ 33

01 1001b = ÷ 35

01 1010b = ÷ 36

01 1011b = ÷ 40

01 1100b = ÷ 42

01 1101b = ÷ 44

01 1110b = ÷ 45

01 1111b = ÷ 48

10 0000b = ÷ 50

10 0001b = ÷ 54

10 0010b = ÷ 55

10 0011b = ÷ 56

10 0100b = ÷ 60

10 0101b = ÷ 64

10 0110b = ÷ 66

10 0111b = ÷ 70

10 1000b = ÷ 72

10 1001b = ÷ 80

10 1010b = ÷ 84

10 1011b = ÷ 88

10 1100b = ÷ 90

10 1101b = ÷ 96

10 1110b = ÷ 100

10 1111b = ÷ 108

11 0000b = ÷ 110

11 0001b = ÷ 112

11 0010b = ÷ 120

11 0011b = ÷ 128

11 0100b = ÷ 132

11 0101b = ÷ 140

11 0110b = ÷ 144

11 0111b = ÷ 160

11 1000b = ÷ 176

11 1001b = ÷ 180

11 1010b = ÷ 200

11 1011b = ÷ 220

11 1100b = Reserved

11 1101b = Reserved

11 1110b = Reserved

11 1111b = Reserved

ND[5:0]

R/W

0Dh

NOTE: QD1 CMOS output should be powered-off or disabled for output frequencies

greater than the maximum listed for it in Table 28.

Post-divider ratio for fractional divider for Bank D:

00 = ÷1

ND_DIVF[1:0]

R/W

00b

01 = ÷2

10 = ÷4

11 = Reserved

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8V49NS0312 Datasheet

Bank D Control Register Block Field Descriptions

Field Type Default Value Description

Bit Field Name

Control which divider is used to provide output frequency for Bank D:

0 = Integer divider D (ND configures this)

1 = Fractional mode (ND_FINT, ND_FRAC and ND_DIVF configure this)

ND_DIV

R/W

0b

Output Source Selection for Bank D:

0 = Bank D is driven from the integer or fractional divider as selected by ND_SRC

1 = Bank D is driven from the input reference (after the mux) with f_IN

ND_SRC

PD_D

Power-down Bank D:

0 = Bank D & all QD outputs powered and operate normally

1 = Bank D & all QD outputs powered-down - no active receivers should be connected

to QD0 output. QD1 output is in High-Impedance.

R/W

0b

Bank D Configuration Control:

0 = ND[5:0], ND_FRAC[23:0], ND_FINT[3:0], ND_DIVF[1:0], ND_DIV, ND_SRC,

PD_D, EN_D, STY_D0 and AMP_D0[1:0] settings determined by ND[1:0] control pins

1 = ND[5:0], ND_FRAC[23:0], ND_FINT[3:0], ND_DIVF[1:0], ND_DIV, ND_SRC,

PD_D, EN_D, STY_D0 and AMP_D0[1:0] settings determined by register settings

over I²C

ND_CTL

Power-down Output QDx:

0 = QD[0:1] outputs powered and operate normally

PD_QDx

R/W

0b

1 = QD0 output powered-down - no active receivers should be connected to the QD0

output, QD1 output is in High-Impedance. When powering-down the output bank, it is

recommended to also write a ‘1’ to the PD_QDx registers.

Output Style for Output QD0:

0 = QD0 is LVDS

STY_QD0

1 = QD0 is LVPECL

Output Amplitude for Output QD0 (measured single-ended):

00 = 350mV

01 = 500mV

10 = 750mV

11 = Reserved

AMP_QD0[1:0]

Rsvd

R/W

00b

-

Reserved. Always write 0 to this bit location. Read values are not defined.

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8V49NS0312 Datasheet

Table 19: Device Control Register Bit Field Locations and Descriptions

Device Control Register Block Field Locations

Address (Hex)

D7

D6

D5

D4

D3

D2

D1

D0

3D

3E

3F

40

INIT_CLK

RELOCK

PB_CAL

Rsvd

EN_A

Rsvd

EN_B

EN_C

EN_D

Device Control Register Block Field Descriptions

Field Type Default Value Description

Bit Field Name

INIT_CLK

Writing a ‘1’ to this bit location will cause output dividers to be synchronized. Must be

done every time a divider value is changed if output divider synchronization is desired.

This bit will auto-clear after output divider synchronization is completed.

W/O^a

0b

RELOCK

Writing a ‘1’ to this bit location will cause the PLL to re-lock. This bit will auto-clear.

Precision Bias Calibration:

Setting this bit to 1 will start the calibration of an internal precision bias current source.

The bias current is used as reference for outputs configured as LVDS and for as

reference for the charge pump currents. This bit will auto-clear after the calibration is

completed.

PB_CAL

W/O^a

0b

Output Enable control for Bank A:

EN_A

EN_B

EN_C

R/W

1b

0 = Bank A outputs QA[0:3] disabled to logic-low state (QAx = 0, nQAx = 1)

1 = Bank A outputs QA[0:3] enabled

Output Enable control for Bank B:

0 = Bank B outputs QB[0:3] disabled to logic-low state (QBx = 0, nQBx = 1)

1 = Bank B outputs QB[0:3] enabled

Output Enable control for Bank C:

0 = Bank C outputs QC[0:1] disabled to logic-low state (QCx = 0, nQCx = 1)

1 = Bank C outputs QC[0:1] enabled

Output Enable control for Bank D:

0 = Bank D outputs QD[0:1] disabled to logic-low state (QD0 = 0, nQD0 = 1, QD1 = 0)

Note that if Bank D is powered down via the PD_D bit or the QD1 output is powered

down by the PD_QD1 bit, then QD1 will be in High-Impedance regardless of the state

of this bit.

EN_D

Rsvd

R/W

1b

-

1 = Bank D outputs QD[0:1] enabled

Reserved. Always write 0 to this bit location. Read values are not defined.

a. These bits are read as ‘0’. When a ‘1’ is written to them, it will have the indicated effect and then self-clear back to ‘0’.

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8V49NS0312 Datasheet

Absolute Maximum Ratings

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress

specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or

AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

Table 20: Absolute Maximum Ratings

Item

Rating

Supply Voltage, V_CC

3.6V

Inputs, V_I

OSCI

Other Inputs

-0.5V to 3.6V

Outputs, V_O(LVCMOS)

-0.5V to 3.6V

Outputs, I_O(LVPECL)

Continuous Current

Surge Current

50mA

100mA

Outputs, I_O(LVDS)

Continuous Current

Surge Current

50mA

100mA

Maximum Junction Temperature, t_JMAX

Storage Temperature, T_STG

125C

-65C to 150C

26

November 14, 2017

8V49NS0312 Datasheet

DC Electrical Characteristics

Table 21: Power Supply DC Characteristics, V_{CC_x}^a= V_CCOX^b= 3.3V±5%, T_A= -40°C to +85°C, V_EE= 0V,

Symbol

Parameter

Test Conditions

Minimum

Typical Maximum Units

V_{CC_X}

Core Supply Voltage

3.135

3.3

73

3.465

100

169

167

226

217

205

103

124

161

10

V

c

V_{CCA_X}

Analog Supply Voltage

Output Supply Voltage

3.135

V

V_CCOX

V

LVPECL

All Outputs Enabled & Terminated^e

All Outputs Enabled & Terminated^f

mA

Core

Supply Current

d

I_{CC_X}

LVDS

73

LVPECL

LVDS

All Outputs Enabled & Terminated^e

141

189

183

172

84

Analog

Supply Current

g

I_{CCA_X}

All Outputs Enabled & Terminated^f

350mV, Outputs Enabled & Terminated^e

500mV, Outputs Enabled & Terminated^e

750mV, Outputs Enabled & Terminated^e

350mV, Outputs Enabled & Terminated^f

500mV, Outputs Enabled & Terminated^f

750mV, Outputs Enabled & Terminated^f

350mV, Outputs Disabled & Unterminated

500mV, Outputs Disabled & Unterminated

750mV, Outputs Disabled & Unterminated

350mV, Outputs Disabled & Unterminated

500mV, Outputs Disabled & Unterminated

750mV, Outputs Disabled & Unterminated

LVPECL

LVDS

101

130

8

Bank A Output

Supply Current

h

I_CCOA

LVPECL

LVDS

10

12

15

26

32

36

43

51

62

27

November 14, 2017

8V49NS0312 Datasheet

Table 21: Power Supply DC Characteristics, V_{CC_x}^a= V_CCOX^b= 3.3V±5%, T_A= -40°C to +85°C, V_EE= 0V, Cont.

Symbol

Parameter

Test Conditions

Minimum

Typical Maximum Units

350mV, Outputs Enabled & Terminated^e

196

188

177

86

103

132

9

234

224

211

105

126

163

11

mA

LVPECL

LVDS

500mV, Outputs Enabled & Terminated^e

750mV, Outputs Enabled & Terminated^e

350mV, Outputs Enabled & Terminated^f

500mV, Outputs Enabled & Terminated^f

750mV, Outputs Enabled & Terminated^f

350mV, Outputs Disabled & Unterminated

500mV, Outputs Disabled & Unterminated

750mV, Outputs Disabled & Unterminated

350mV, Outputs Disabled & Unterminated

500mV, Outputs Disabled & Unterminated

750mV, Outputs Disabled & Unterminated

350mV, Outputs Enabled & Terminated^e

500mV, Outputs Enabled & Terminated^e

750mV, Outputs Enabled & Terminated^e

350mV, Outputs Enabled & Terminated^f

500mV, Outputs Enabled & Terminated^f

750mV, Outputs Enabled & Terminated^f

350mV, Outputs Disabled & Unterminated

500mV, Outputs Disabled & Unterminated

750mV, Outputs Disabled & Unterminated

350mV, Outputs Disabled & Unterminated

500mV, Outputs Disabled & Unterminated

750mV, Outputs Disabled & Unterminated

Bank B Output

Supply Current

h

I_CCOB

LVPECL

LVDS

10

13

27

36

52

109

106

100

55

64

78

1

13

16

33

44

62

131

127

120

67

78

95

2

LVPECL

LVDS

Bank C Output

Supply Current

h

I_CCOC

LVPECL

LVDS

1

2

1

2

1

2

1

2

1

2

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November 14, 2017

8V49NS0312 Datasheet

Table 21: Power Supply DC Characteristics, V_{CC_x}^a= V_CCOX^b= 3.3V±5%, T_A= -40°C to +85°C, V_EE= 0V, Cont.

Symbol

Parameter

Test Conditions

Minimum

Typical Maximum Units

350mV, Outputs Enabled & Terminated^e

91

89

86

57

62

70

3

114

112

109

69

75

85

5

mA

LVPECL

LVDS

500mV, Outputs Enabled & Terminated^e

750mV, Outputs Enabled & Terminated^e

350mV, Outputs Enabled & Terminated^f

500mV, Outputs Enabled & Terminated^f

750mV, Outputs Enabled & Terminated^f

350mV, Outputs Disabled & Unterminated

500mV, Outputs Disabled & Unterminated

750mV, Outputs Disabled & Unterminated

350mV, Outputs Disabled & Unterminated

500mV, Outputs Disabled & Unterminated

750mV, Outputs Disabled & Unterminated

350mV, Outputs Enabled & Terminated^e

500mV, Outputs Enabled & Terminated^e

750mV, Outputs Enabled & Terminated^e

350mV, Outputs Disabled & Unterminated

500mV, Outputs Disabled & Unterminated

750mV, Outputs Disabled & Unterminated

Bank D Output

Supply Current

h

I_CCOD

LVPECL

LVDS

3

5

3

5

3

5

3

5

3

5

385

394

407

233

236

241

470

481

497

277

280

286

LVPECL

Power Supply

Current

for V_EE

h

I_EE

a. V_{CC_x}denotes V_{CC_CP,}V_{CC_CK,}V_{CC_SP.}

b. V_CCOXdenotes V_CCOA,V_CCOB,V_CCOC,V_CCOD.

c. V_{CCA_X}denotes V_{CCA_IN1,}V_{CCA_IN2,}V_CCA,V_{CCA_XT.}

d. I_{CC_X}denotes I_{CC_CP, CC_CK, CC_SP.}

I

e. Differential outputs terminated 50 to V_CCOX- 2V. QD1 output terminated 50to V_CCOD/2.

f. Differential outputs terminated 100 across Q and nQ. QD1 output terminated 50to V_CCOD/2.

g. I_{CCA_X}denotes I_{CCA_IN1, CCA_IN2, CCA, CCA_XT.}

I

h. Internal maximum dynamic switching current is included.

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November 14, 2017

8V49NS0312 Datasheet

Table 22: LVCMOS DC Characteristics for 3-level Pins, V_{CC_X}^a= V_CCOX^b= 3.3V±5%, T_A= -40°C to +85°C,

_EE= 0V

V

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

c

V_IH

Input High Voltage

0.7 * V_CC

3.465

V

FIN[1:0],

NA[1:0], NB[1:0],

NC[1:0], ND[1:0]

c

V_IM

V_IL

I_IH

Input Middle Voltage

Input Low Voltage

Input High Current

0.4 * V_CC

0.6 * V_CC

V

c

-0.3

0.3 * V_CC

FIN[1:0],

NA[1:0], NB[1:0],

NC[1:0], ND[1:0]

V_CC^c= V_IN= 3.465V

150

µA

FIN[1:0],

NA[1:0], NB[1:0],

NC[1:0], ND[1:0]

I_IM

Input Middle Current

Input Low Current

V_IN= V_CC^c/ 2

±1

µA

FIN[1:0],

NA[1:0], NB[1:0],

NC[1:0], ND[1:0]

I_IL

V_CC^c= 3.465V, V_IN= 0V

-150

a. V_{CC_X}denotes V_{CC_CP,}V_{CC_CK,}V_{CC_SP.}

b. V_CCOXdenotes V_CCOA,V_CCOB,V_CCOC,V_CCOD.

c. V_CCdenotes V_{CCA_IN1,}V_{CC_CK.}

Table 23: LVCMOS DC Characteristics for 2-level Pins, V_{CC_X}^a= V_CCOX^b= 3.3V±5%, T_A= -40°C to +85°C,

_EE= 0V

V

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

c

V_IH

Input High Voltage

0.7 * V_CC

3.465

V

c

REF_SEL

-0.3

0.3 * V_CC

V

V_IL

I_IH

I_IL

Input Low Voltage

Input High Current

Input Low Current

c

SDATA, SCLK

SCLK, SDATA

REF_SEL

0.15 * V_CC

V_CC^c= V_IN= 3.465V

V_CC^c= 3.465V, V_IN= 0V

I_OH= -4mA

5

µA

V

150

SCLK, SDATA

REF_SEL

-150

-5

V_OH

V_OL

Output High Voltage

Output Low Voltage

LOCK

2.2

SDATA, LOCK

I_OL= 4mA

0.45

V

a. V_{CC_X}denotes V_{CC_CP,}V_{CC_CK,}V_{CC_SP.}

b. V_CCOXdenotes V_CCOA,V_CCOB,V_CCOC,V_CCOD.

c. V_CCdenotes V_{CC_CK.}

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November 14, 2017

8V49NS0312 Datasheet

Table 24: Differential Input DC Characteristics, V_{CC_X}^a= V_CCOX^b= 3.3V±5%, T_A= -40°C to +85°C, V_EE= 0V

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input

CLK_IN,

nCLK_IN

I_IH

V_CC^c= V_IN= 3.465V

150

µA

High Current

CLK_IN

V_CC^c= 3.465V, V_IN= 0V

-5

µA

Input

I_IL

Low Current

nCLK_IN

-150

Peak-to-Peak

Voltage^{d, e}

CLK_IN,

nCLK_IN

V_PP

0.2

1.4

V

Common Mode

Input Voltage^{d, e}

CLK_IN,

nCLK_IN

V_CMR

V_EE+ 1.1

V_CC^c– 0.3

a. V_{CC_X}denotes V_{CC_CP,}V_{CC_CK,}V_{CC_SP.}

b. V_CCOXdenotes V_CCOA,V_CCOB,V_CCOC,V_CCOD.

c. V_CCdenotes V_{CC_CK.}

d. Common mode voltage is defined as the cross point.

e. Input voltage cannot be less than V_EE- 300mV or more than V_CC.

Table 25: LVPECL Output DC Characteristics (Qmn^a), V_{CC_X}^b= V_CCOX^c= 3.3V±5%, T_A= -40°C to +85°C,

_EE= 0V

V

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

350mV Amplitude setting

V_CCOX– 1.1

V_CCOX– 0.8

V_OH

Output High Voltage^d

500mV Amplitude setting

750mV Amplitude setting

350mV Amplitude setting

500mV Amplitude setting

750mV Amplitude setting

350mV Amplitude setting

500mV Amplitude setting

750mV Amplitude setting

V_CCOX– 1.1

V_CCOX– 1.5

V_CCOX– 1.6

V_CCOX– 1.8

280

V_CCOX– 0.8

V_CCOX– 1.1

V_CCOX– 1.3

V_CCOX– 1.5

420

V

V_OL

Output Low Voltage^d

V

350

500

700

Single-ended Peak-to-Peak

Output Voltage Swing

V_SWING

430

570

mV

630

770

a. In this table, Qmn denotes the differential outputs QA[0:3], QB[0:3], QC[0:1] or QD0. Note that QD1 is not included because it is not differential.

b. V_{CC_X}denotes V_{CC_CP,}V_{CC_CK,}V_{CC_SP.}

c. V_CCOXdenotes V_CCOA,V_CCOB,V_CCOC,V_CCOD.

d. Outputs terminated with 50 to V_CCOX– 2V.

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November 14, 2017

8V49NS0312 Datasheet

Table 26: LVDS Output DC Characteristics (Qmn^a), V_{CC_X}^b= V_CCOX^c= 3.3V±5%, T_A= -40°C to +85°C, V_EE= 0V

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

350mV Amplitude setting

0.27

0.32

0.37

V_OD

V_OD

V_OS

Differential Output Voltage

500mV Amplitude setting

750mV Amplitude setting

0.39

0.62

0.46

0.69

0.53

0.76

50

V

V_ODMagnitude Change

Offset Voltage^{d, e, f}

mV

V

350mV Amplitude setting

500mV Amplitude setting

750mV Amplitude setting

1.9

1.8

1.7

2.3

2.2

2.1

2.7

2.6

2.5

50

V_OS

V_OSMagnitude Change

mV

a. In this table, Qmn denotes the differential outputs QA[0:3], QB[0:3], QC[0:1] or QD0. Note that QD1 is not included because it is not differential.

b. V_{CC_X}denotes V_{CC_CP,}V_{CC_CK,}V_{CC_SP.}

c. V_CCOXdenotes V_CCOA,V_CCOB,V_CCOC,V_CCOD.

d. No external DC pulldown resistor.

e. Loading condition is with 100 across the differential output.

f. Offset voltage (V_OS) changes with supply voltage V_CCOX.

Table 27: Crystal Characteristics

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Mode of Oscillation

Frequency

Fundamental

10

50

60

30

MHz



C_L= 12pF

C_L= 18pF

Equivalent Series Resistance (ESR)

15

12



Load Capacitance (C_L)

pF

Maximum Crystal Drive Level

Frequency Stability (total)

200

W

ppm

-100

100

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November 14, 2017

8V49NS0312 Datasheet

AC Electrical Characteristics

Table 28: AC Characteristics,^aV_{CC_X}^b= V_CCOX^c= 3.3V+5%, T_A= -40°C to +85°C, V_EE= 0V

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

f_VCOVCO Frequency

2400

2500

MHz

Phase / Frequency Detector

Frequency

f_PFD

5

200

MHz

QA[0:3]

nQA[0:3]

QB[0:3]

nQB[0:3]

QC[0:1]

10.91

2500

nQC[0:1]

Output

Frequency

f_OUT

Integer Divider Selected

Fractional Divider Selected

Integer Divider Selected

Fractional Divider Selected

10.91

20

2500

138

250

138

45

MHz

QD0, nQD0

10.91

20

QD1

Bank A

Bank Skew^{d, e, f}Bank B

Bank C

Same Frequency and Output Type

Only valid for skew between outputs in

the same bank

tsk(b)

45

ps

20

QA[0:3]

nQA[0:3]

QB[0:3]

nQB[0:3]

QC[0:1]

nQC[0:1]

30% to 70%

30

60

110

Output

Rise/Fall Time

t_R/ t_F

ps

QD0, nQD0

QD1

30% to 70%

30

220

45

90

375

50

200

600

55

QA[0:3]

nQA[0:3]

QB[0:3]

nQB[0:3]

F_OUT 1250MHz

%

F_OUT> 1250MHz

40

50

60

QC[0:1]

Output

odc

Duty Cycle^g

nQC[0:1],

QD0, nQD0

F_OUT< 156.25MHz

45

40

50

40

55

60

%

QD1

F_OUT 156.25MHz

t_LOCK

PLL Lock Time^h

100

ms

a. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with main-

tained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.

b. V_{CC_X}denotes V_{CC_CP,}V_{CC_CK,}V_{CC_SP.}

c. V_CCOXdenotes V_CCOA,V_CCOB,V_CCOC,V_CCOD.

d. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crosspoints

e. This parameter is defined in accordance with JEDEC Standard 65.

.

f. This parameter is guaranteed by characterization. Not tested in production

g. Duty Cycle of bypassed signals (input reference clock or crystal input) is not adjusted by the device.

h. PLL Lock Time is defined as time from input clock availability to frequency locked output. The following loop filter component values may be used: R_Z= 221Ω, C_Z= 4.7μF

C_P= 30pf. Refer to Applications Information.

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November 14, 2017

8V49NS0312 Datasheet

Table 29: Qmn^aand QD1 Phase Noise and Jitter Characteristics, V_{CC_X}^b= V_CCOX^c= 3.3V+5%,

g

,

h i

,

T_A= -40°C to +85°C^{d e f}

,

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

RMS Phase

Jitter Random

Qmn =

Integration Range: 12kHz – 20MHz

87

110

fs

156.25MHz^k

RMS Phase

Jitter Random

Qmn = 125MHz

Qmn = 100MHz

Qmn = 25MHz

Integration Range: 12kHz – 20MHz

Integration Range: 12kHz – 5MHz

84

94

fs

RMS Phase

Jitter Random

RMS Phase

Jitter Random

126

QD0 =

RMS Phase

Jitter Random

tjit(Ø)^j

133.33MHz

Integration Range: 12kHz – 20MHz

180

170

fs

(fractional)^l

RMS Phase

Jitter Random

QD1= 125MHz

QAn = 125MHz

QBn = 100MHz

QCn = 25MHz

Integration Range: 12kHz – 20MHz

Integration Range: 12kHz – 5MHz

85

88

fs

RMS Phase

137

Jitter Random^m

QD0 =

133.33MHz

(fractional)

Integration Range: 12kHz – 20MHz

170

fs

Single-Side Band Noise Power,

10Hz from Carrier

_N(10)ⁿ

Qmn = 156.25MHz

-75.1

-109.6

-128.9

-137.6

-143.0

-157.5

dBc/Hz

Single-Side Band Noise Power,

100Hz from Carrier

_N(100)ⁿ

_N(1k)ⁿ

Single-Side Band Noise Power,

1kHz from Carrier

Single-Side Band Noise Power,

10kHz from Carrier

_N(10k)ⁿ

_N(100k)ⁿ

_N(1M)ⁿ

Single-Side Band Noise Power,

100kHz from Carrier

Single-Side Band Noise Power,

1MHz from Carrier

Single-Side Band Noise Power,

10MHz from Carrier

_N(10M)ⁿ

_N()ⁿ

Qmn = 156.25MHz

-163.1

dBc/Hz

Noise Floor (30MHz from Carrier)

a. In this table, Qmn denotes the differential outputs QA[0:3], QB[0:3], QC[0:1] or QD0. Note that QD1 is not included because it is not differential.

b. V_{CC_X}denotes V_{CC_CP,}V_{CC_CK,}V_{CC_SP.}

c. V_CCOXdenotes V_CCOA,V_CCOB,V_CCOC,V_CCOD.

d. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is mounted in a test socket with main-

tained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium has been reached under these conditions.

e. All outputs enabled and configured for the same output frequency unless otherwise noted.

f. Characterized using a 50MHz, C_L= 18pF crystal, unless otherwise noted.

g. Measured on Qmn configured as ÷16 and ÷20.

h. V_CCArequires a voltage regulator. Voltage supplied to V_CCAshould be derived from a regulator with a typical power supply rejection ratio of 80dB at 1kHz and ultra low

noise generation with a typical value of 3nV/Hz at 10kHz and 7nV/Hz at 1kHz.

i. Characterized with 750mV output voltage swing configuration for all differential outputs.

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November 14, 2017

8V49NS0312 Datasheet

j. The following loop filter component values were used: R_Z= 221, C_Z= 4.7µF, CP = 30pF. PLL Charge Pump Current Control set at 5.2mA.

k. Characterized using a 31.25MHz, C_L= 18pF crystal, (FOX P/N FX277LF-31.25-1).

l. QAx = 156.25MHz, QBx = 156.25MHz, QCx = 156.25MHz.

m. QAx = 156.25MHz, QBx = 100MHz, QCx = 25MHz, QD0 = 133.33MHz (fractional).

n. Measured using a 50MHz, 12pF crystal as input reference. The following loop filter components were used: R_Z= 150, C_Z= 0.1µF, CP = 200pF.

PLL Charge Pump Current Control set at 6.4mA.

Typical Phase Noise at 156.25MHz^a

Offset Frequency (Hz)

a: Measured using a 50MHz, 12pF crystal as input reference. The following loop filter components were used: R_Z= 150, C_Z= 0.1µF, CP = 200pF.

PLL Charge Pump Current Control set at 6.4mA.

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November 14, 2017

8V49NS0312 Datasheet

Typical Phase Noise at 125MHz^a

Offset Frequency (Hz)

a. Measured using a 50MHz, 12pF crystal as input reference. The following loop filter components were used: R_Z= 150, C_Z= 0.1µF, CP = 200pF.

PLL Charge Pump Current Control set at 6.4mA.

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November 14, 2017

8V49NS0312 Datasheet

Applications Information

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pull-up and/or pull-down resistors; additional resistance is not required but can be added for additional protection.

A 1k resistor can be used.

Outputs:

LVPECL Outputs

All unused LVPECL outputs should be left floating. It is recommended that there is no trace attached.

LVDS Outputs

All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating there should be no trace attached.

LVCMOS Outputs

QD1 output can be left floating if unused. There should be no trace attached.

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November 14, 2017

8V49NS0312 Datasheet

Overdriving the XTAL Interface

The OSCI input can be overdriven by an LVCMOS driver or by one side of a differential driver through an AC coupling capacitor. The OSCO

pin can be left floating. The amplitude of the input signal should be between 500mV and 1.8V and the slew rate should not be less than

0.2V/nS. For 3.3V LVCMOS inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent signal

interference with the power rail and to reduce internal noise. Figure 3 shows an example of the interface diagram for a high speed 3.3V

LVCMOS driver. This configuration requires that the sum of the output impedance of the driver (Ro) and the series resistance (Rs) equals the

transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of

two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50 applications, R1 and R2 can be 100. This

can also be accomplished by removing R1 and changing R2 to 50. The values of the resistors can be increased to reduce the loading for a

slower and weaker LVCMOS driver. Figure 4 shows an example of the interface diagram for an LVPECL driver. This is a standard LVPECL

termination with one side of the driver feeding the OSCI input. It is recommended that all components in the schematics be placed in the

layout. Though some components might not be used, they can be utilized for debugging purposes. The datasheet specifications are

characterized and guaranteed by using a quartz crystal as the input.

OSCO

OSCI

VCC

R1

100

C1

Zo = 50Ω

Ro

RS

0.1μF

Zo = Ro + Rs

LVCMOS_Driver

R2

100

Figure 3: General Diagram for LVCMOS Driver to XTAL Input Interface

OSCO

C2

Zo = 50Ω

OSCI

0.1μF

Zo = 50Ω

R1

50

R2

50

LVPECL_Driver

R3

50

Figure 4: General Diagram for LVPECL Driver to XTAL Input Interface

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November 14, 2017

8V49NS0312 Datasheet

Wiring the Differential Input to Accept Single-Ended Levels

Figure 5 shows how a differential input can be wired to accept single ended levels. The reference voltage V₁= V_CC/2 is generated by the bias

resistors R1 and R2. The bypass capacitor (C1) is used to help filter noise on the DC bias. This bias circuit should be located as close to the

input pin as possible. The ratio of R1 and R2 might need to be adjusted to position the V₁in the center of the input voltage swing. For example,

if the input clock swing is 2.5V and V_CC= 3.3V, R1 and R2 value should be adjusted to set V₁at 1.25V. The values below are for when both the

single ended swing and V_CCare at the same voltage. This configuration requires that the sum of the output impedance of the driver (Ro) and

the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the input will attenuate the signal in

half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission line impedance. For most 50

applications, R3 and R4 can be 100. The values of the resistors can be increased to reduce the loading for slower and weaker LVCMOS

driver.

When using single-ended signaling, the noise rejection benefits of differential signaling are reduced. Even though the differential input can

handle full rail LVCMOS signaling, it is recommended that the amplitude be reduced. The datasheet specifies a lower differential amplitude,

however this only applies to differential signals. For single-ended applications, the swing can be larger, however V_ILcannot be less than -0.3V

and V_IHcannot be more than V_CC+ 0.3V. Suggested edge rate faster than 1V/ns. Though some of the recommended components might not

be used, the pads should be placed in the layout. They can be utilized for debugging purposes. The datasheet specifications are characterized

and guaranteed by using a differential signal.

Figure 5: Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

39

November 14, 2017

8V49NS0312 Datasheet

3.3V Differential Clock Input Interface

CLK/nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other differential signals. Both V_SWINGand V_OHmust meet the V_PPand V_CMRinput

requirements. Figure 6 to Figure 10 show interface examples for the CLK/nCLK input driven by the most common driver types. The input

interfaces suggested here are examples only.

Please consult with the vendor of the driver component to confirm the driver termination requirements. For example, in Figure 6, the input

termination applies for IDT open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination

recommendation.

3.3V

1.8V

Zo = 50Ω

CLK

Zo = 50Ω

nCLK

Differential

Input

LVHSTL

R1

50Ω

R2

50Ω

IDT

LVHSTL Driver

Figure 6: CLK/nCLK Input Driven by an

IDT Open Emitter LVHSTL Driver

Figure 9: CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 7: CLK/nCLK Input Driven by a

3.3V LVPECL Driver

Figure 10: CLK/nCLK Input Driven by a

3.3V LVDS Driver

3.3V

*R3

CLK

nCLK

Differential

Input

*R4

HCSL

Figure 8: CLK/nCLK Input Driven by a

3.3V HCSL Driver

40

November 14, 2017

8V49NS0312 Datasheet

LVDS Driver Termination

For a general LVDS interface, the recommended value for the termination impedance (Z_T) is between 90 and 132. The actual value should

be selected to match the differential impedance (Z₀) of your transmission line. A typical point-to-point LVDS design uses a 100 parallel

resistor at the receiver and a 100 differential transmission-line environment. In order to avoid any transmission-line reflection issues, the

components should be surface mounted and must be placed as close to the receiver as possible. IDT offers a full line of LVDS compliant

devices with two types of output structures: current source and voltage source. The standard termination schematic as shown in Figure 11 can

be used with either type of output structure. Figure 12, which can also be used with both output types, is an optional termination with center tap

capacitance to help filter common mode noise. The capacitor value should be approximately 50pF. If using a non-standard termination, it is

recommended to contact IDT and confirm if the output structure is current source or voltage source type. In addition, since these outputs are

LVDS compatible, the input receiver’s amplitude and common-mode input range should be verified for compatibility with the output.

Refer to Figure 13, Figure 14 and Figure 15 for additional details on the recommended termination schemes.

Figure 11: Standard LVDS Termination

Figure 12: Optional LVDS Termination

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November 14, 2017

8V49NS0312 Datasheet

3.3V

Z0 = 50Ω

Input high

impedance

100Ω

Z0 = 50Ω

8Vꢀ9N30ꢁꢂ2

Receiver

Figure 13: DC Termination for LVDS Outputs

Figure 14: AC Termination for LVDS Outputs

3.3V

0.1μF

Z0 = 50Ω

0.1μF

Z0 = 50Ω

Internal 50Ω

terminations

8Vꢀ9N3ꢃꢁꢂ2

Receiver

Figure 15: AC Termination for LVDS outputs used with an Input Clock Receiver with Internal 50 Terminations

and DC Bias.

42

November 14, 2017

8V49NS0312 Datasheet

Termination for 3.3V LVPECL Outputs

The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended

only as guidelines.The differential outputs generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to

ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance

techniques should be used to maximize

operating frequency and minimize signal distortion. Figure 16 and Figure 17 show two different layouts which are recommended only as

guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility

across all printed circuit and clock component process variations.

3.3V

R3

R4

125

3.3V

Z_o= 50

+

_

Input

Z_o= 50

R1

84

R2

84

Figure 16: 3.3V LVPECL Output Termination

Figure 17: 3.3V LVPECL Output Termination

43

November 14, 2017

8V49NS0312 Datasheet

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the

Printed Circuit Board (PCB) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package,

as shown in Figure 18. The solderable area on the PCB, as defined by the solder mask, should be at least the same size/shape as the exposed

pad/slug area on the package to maximize the thermal/electrical performance. Sufficient clearance should be designed on the PCB between

the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat transfer and electrical grounding from the package to the board through a solder

joint, thermal vias are necessary to effectively conduct from the surface of the PCB to the ground plane(s). The land pattern must be

connected to ground through these vias. The vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are application specific

and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis

and/or testing are recommended to determine the minimum number needed. Maximum thermal and electrical performance is achieved when

an array of vias is incorporated in the land pattern. It is recommended to use as many vias connected to ground as possible. It is also

recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is desirable to avoid any

solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal

land. Precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. Note: These

recommendations are to be used as a guideline only. For further information, please refer to the Application Note on the Surface Mount

Assembly of Amkor’s Thermally/ Electrically Enhance Leadframe Base Package, Amkor Technology.

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

Figure 18: P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

44

November 14, 2017

8V49NS0312 Datasheet

Schematic Layout

Figure 19 shows an example 8V49NS0312 application schematic operating the device at V_CC= 3.3V. This example focuses on functional

connections and is not configuration specific. Refer to the pin description and functional tables in the datasheet to ensure that the logic control

inputs are properly set for the application.

To demonstrate the range of output stage configurations possible, the application schematic assumes that the 8V49NS0312 is programmed

over I²C. For alternative DC coupled LVPECL options please see IDT Application Note, AN-828; for AC coupling options use IDT Application

Note, AN-844.

For a 12pF parallel resonant crystal, tuning capacitors C145 and C146 are recommended for frequency accuracy. Depending on the parasitic

of the printed circuit board layout, these values might require a slight adjustment to optimize the frequency accuracy. Crystals with other load

capacitance specifications can be used. This will require adjusting C145 and C146. For this device, the crystal tuning capacitors are required

for proper operation.

Crystal layout is very important to minimize capacitive coupling between the crystal pads and leads and other metal in the circuit board.

Capacitive coupling to other conductors has two adverse effects; it reduces the oscillator frequency leaving less tuning margin and noise

coupling from power planes and logic transitions on signal traces can pull the phase of the crystal resonance, inducing jitter. Routing I²C under

the crystal is a very common layout error, based on the assumption that it is a low frequency signal and will not affect the crystal oscillation. In

fact, I²C transition times are short enough to capacitively couple into the crystal-oscillator loop if they are routed close enough to the crystal

traces.

In layout, all capacitive coupling to the crystal from any signal trace is to be minimized, that is to the OSCI and OSCO pins, traces to the crystal

pads, the crystal pads and the tuning capacitors. Using a crystal on the top layer as an example, void all signal and power layers under the

crystal connections between the top layer and the ground plane used by the 8V49NS0312. Then calculate the parasitic capacity to the ground

and determine if it is large enough to preclude tuning the oscillator. If the coupling is excessive, particularly if the first layer under the crystal is

a ground plane, a layout option is to void the ground plane and all deeper layers until the next ground plane is reached. The ground connection

of the tuning capacitors should first be made between the capacitors on the top layer, then a single ground via is dropped to connect the tuning

cap ground to the ground plane as close to the 8V49NS0312 as possible as shown in the schematic.

As with any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power

supply isolation is required. The 8V49NS0312 provides separate power supplies to isolate any high switching noise from coupling into the

internal PLL.

In order to achieve the best possible filtering, it is recommended that the placement of the filter components be on the device side of the PCB

as close to the power pins as possible. The ferrite bead and the 0.1uF capacitor in each power pin filter should always be placed on the device

side of the board. The other components can be on the opposite side of the PCB if space on the top side is limited. Pull up and pull down

resistors to set configuration pins can all be placed on the PCB side opposite the device side to free up device side area if necessary.

Power supply filter recommendations are a general guideline to be used for reducing external noise from coupling into the devices. Depending

on the application, the filter may need to be adjusted to get a lower cutoff frequency to adequately attenuate low-frequency noise. Additionally,

good general design practices for power plane voltage stability suggest adding bulk capacitance in the local area of all devices.

For additional layout recommendations and guidelines, contact clocks@idt.com.

45

November 14, 2017

8V49NS0312 Datasheet

Figure 19: 8V49NS0312 Application Schematic

46

November 14, 2017

8V49NS0312 Datasheet

Power Dissipation and Thermal Considerations

The 8V49NS0312 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. Since this device is

highly programmable with a broad range of features and functionality, the power consumption will vary as each of these features and functions

is enabled.

The 8V49NS0312 device was designed and characterized to operate within the ambient industrial temperature range of -40°C to +85°C. The

ambient temperature represents the temperature around the device, not the junction temperature. When using the device in extreme cases,

such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable

junction temperature. Extreme care must be taken to avoid exceeding 125°C junction temperature.

The power calculation examples below were generated using a maximum ambient temperature and supply voltage. For many applications, the

power consumption will be much lower. Please contact IDT technical support for any concerns on calculating the power dissipation for your

own specific configuration.

Example 1. LVPECL, 750mV Output Swing

This section provides information on power dissipation and junction temperature when the device differential outputs are configured for

LVPECL level, 750mV output swing. Equations and example calculations are also provided.

Table 30: Power Calculations Configuration #1

Output

QA0

QA1

QA2

QA3

QB0

QB1

QB2

QB3

QC0

QC1

QD0

QD1

Output Style

LVPECL

LVCMOS

Output Swing

750mV

N/A

1a. Power Dissipation.

The total power dissipation is the sum of the core power plus the power dissipated due to output loading.

The following is the power dissipation for V_CC= 3.465V, which gives worst case results.

▪ Power(core)_MAX= V_{CC_MAX}* I_{EE_MAX}= 3.465V * 497mA = 1722.1mW

▪ Power(LVPECL outputs)_MAX= 34.2mW/Loaded Output pair. Refer to Section 1c.

If all outputs are loaded, the total power is 11 * 34.2mW = 376.2mW

▪ Power (LVCMOS output)_MAX(Power dissipation due to loading 50 to V_CCO/ 2)

Output Current: I_OUT= V_{CCOD_MAX}/ [2 * (50 + R_OUT)] = 3.465V / [2 * (50 + 30)] = 21.66mA

Power Dissipation on the R_OUT: Power (R_OUT) = R_OUT* (I_OUT)²= 30 * (21.66mA)²= 14.07mW

▪ Total Power_MAX= Power(core) + Power (LVPECL outputs) + Power (LVCMOS output)

= 1722.1mW + 376.2mW +14.07mW = 2112.37mW = 2.112W

47

November 14, 2017

8V49NS0312 Datasheet

1b. Junction Temperature.

Junction temperature, T_J, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, T_J, to 125°C ensures that the

bond wire and bond pad temperature remains below 125°C.

The equation for T_Jis as follows: T_J= T_A+ P_D* _JA:

T_J= Junction Temperature

T_A= Ambient Temperature

P_D= Power Dissipation (W) in desired operating configuration



_JA= Junction-to-Ambient Thermal Resistance

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance must be used. Assuming no air flow and a

multi-layer board, the appropriate value is 15.6°C/W per Table 32.

Therefore, assuming T_A= 85°C and all outputs switching, T_Jwill be:

85°C + 2.112W * 15.6°C/W = 117.95°C. This is below the limit of 125°C.

This calculation is only an example. T_Jwill obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

1c. Power Dissipation due to output loading.

The purpose of this section is to calculate the power dissipation for the LVPECL output pair.

LVPECL output driver circuit and termination are shown in Figure 20.

V_CCO

Q1

V_OUT

RL

50Ω

V_CCO- 2V

Figure 20: LVPECL Driver Circuit and Termination

To calculate worst case power dissipation at the output(s), use the following equations which assume a 50 load, and a termination voltage of

V

_CCOX- 2V. These are typical calculations.

▪ For logic high, V_OUT= V_{OH_MAX}= V_{CCOX_MAX}- 0.8V

(V_{CCOX_MAX}- V_{OH_MAX}) = 0.8V

▪ For logic low, V_OUT= V_{OL_MAX}= V_{CCOX_MAX}- 1.5V

(V_{CCOX_MAX}- V_{OL_MAX}) = 1.5V

Pd_H is the power dissipation when the output drives high.

48

November 14, 2017

8V49NS0312 Datasheet

Pd_L is the power dissipation when the output drives low.

Pd_H = [(V^OH_MAX– (VCCOX_MAX – 2V))/RL] * (VCCOX_MAX – VOH_MAX) = [(2V – (VCCOX_MAX – VOH_MAX))/RL] * (VCCOX_MAX– VOH_MAX) =

[(2V – 0.8V)/50] * 0.8V = 19.2mW

Pd_L = [(V^OL_MAX– (VCCOX_MAX – 2V))/RL] * (VCCOX_MAX – VOL_MAX) = [(2V – (VCCOX_MAX – VOL_MAX))/RL] * (VCCOX_MAX – VOL_MAX) =

[(2V – 1.5V)/50] * 1.5V = 15mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 34.2mW

Example 2. LVDS, 350mV Output Swing

This section provides information on power dissipation and junction temperature when the device differential outputs are configured for LVDS

levels, 350mV output swing. Equations and example calculations are also provided.

Table 31: Power Calculations Configuration #2

Output

QA0

QA1

QA2

QA3

QB0

QB1

QB2

QB3

QC0

QC1

QD0

QD1

Output Style

LVDS

Output Swing

350mV

N/A

LVDS

LVCMOS

2a. Power Dissipation.

The total power dissipation is the sum of the core power plus the power dissipation due to output loading.

The following is the power dissipation for V_CCX= V_{CCA_X}= V_CCOX= 3.3V + 5% = 3.465V, which gives worst case results.

▪ Power_MAX= V_{CCX_MAX}* I_{CCX_MAX}+ V_{CCA_X_MAX}* I_{CCA_X_MAX}+ V_{CCOX_MAX}* I_{CCOX_MAX}

= 3.465V * 100mA + 3.465V * 167mA + 3.465V (103mA + 105mA + 67mA + 69mA)

= 346.5mW + 578.66mW + 1191.96mW = 2117.12mW = 2.117W

49

November 14, 2017

8V49NS0312 Datasheet

2b. Junction Temperature.

Junction temperature, T_J, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The

maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, T_J, to 125°C ensures that the

bond wire and bond pad temperature remains below 125°C.

The equation for T_Jis as follows: T_J= T_A+ P_D* _JA:

T_J= Junction Temperature

T_A= Ambient Temperature

P_D= Power Dissipation (W) in desired operating configuration



_JA= Junction-to-Ambient Thermal Resistance

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance must be used. Assuming no air flow and a

multi-layer board, the appropriate value is 15.6°C/W per Table 32.

Therefore, assuming T_A= 85°C and all outputs switching, T_Jwill be:

85°C + 2.117W * 15.6°C/W = 118.03°C. This is below the limit of 125°C.

This calculation is only an example. T_Jwill obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Reliability Information

Table 32: Thermal Resistance Table for 64-pin VFQFN Package

Symbol

Thermal Parameter

Junction-to-Ambient

Junction-to-Case

Condition

Value

15.6

15.3

0.6

Unit

°C/W

a

_JA

No air flow

_JC

_JB

Junction-to-Board

a. Theta J_A(_JA) values calculated using an 8-layer PCB (114.3mm x 101.6mm), with 2oz. (70µm) copper plating on all 8 layers, with ePad

connected to 4 ground planes.

Transistor Count

The transistor count for the 8V49NS0312 is: 143,063

50

November 14, 2017

8V49NS0312 Datasheet

Package Outline Drawings

51

November 14, 2017

8V49NS0312 Datasheet

Package Outline Drawings (Cont.)

52

November 14, 2017

8V49NS0312 Datasheet

Ordering Information

Part/Order Number

Marking

Package

Shipping Packaging

Temperature

8V49NS0312NLGI

IDT8V49NS0312NLGI

64-pin VFQFN, Lead-Free

Tray

-40°C to +85°C

8V49NS0312NLGI8

64-pin VFQFN, Lead-Free

Tape & Reel

-40°C to +85°C

Revision History

Revision Date

Description of Change

November 14, 2017

▪ Updated the QD fractional output divider’s maximum frequency to 138MHz to meet period jitter compliance

(see Table 28)

▪ Updated the Package Outline Drawings; however, no mechanical changes

▪ Completed other minor changes

September 2, 2016

August 1, 2016

page 32, Table 27 Crystal Characteristics - added additional spec to Equivalent Series Resistance row.

page 50, Power Dissipation due to output loading. - typographical error

replaced “-” with “=”: For logic low, V_OUT= V_{OL_MAX}= V_{CCOX_MAX}- 1.5V, (V_{CCOX_MAX}- V_{OL_MAX}) = 1.5V.

July 11, 2016

Initial release.

Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 USA

www.IDT.com

Sales

Tech Support

www.IDT.com/go/support

1-800-345-7015 or 408-284-8200

Fax: 408-284-2775

www.IDT.com/go/sales

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time, without

notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed

in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any

particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual

property rights of IDT or any third parties.

IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably

expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of

53

November 2017


型号：	8V49NS0312_17
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	NG Clock Generator with 4 Dividers
文件：	总53页 (文件大小：1330K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

8V49NS0312_17 [IDT]

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