ICS842S104_技术文档

Crystal-to-HSTL 100MHz / 200MHz

PCI Express™ Clock Synthesizer

ICS842S104

DATA SHEET

General Description

Features

The ICS842S104 is a PLL-based clock generator specifically

designed for PCI Express™ Clock Generation 2 applications. This

device generates either a 200MHz or 100MHz differential HSTL

clock from an input reference of 25MHz. The input reference may be

derived from an external source or by the addition of a 25MHz

crystal to the on-chip crystal oscillator. An external reference is

applied to the XTAL_IN pin with the XTAL_OUT pin left floating.The

device offers spread spectrum clock output for reduced EMI

applications. An I²C bus interface is used to enable or disable spread

spectrum operation as well as select either a down spread value of

-0.35% or -0.5%.The ICS842S104 is available in a lead-free 24-Lead

package.

• Four differential HSTL output pairs

• Crystal oscillator interface: 25MHz

• Output frequency: 100MHz or 200MHz

• RMS phase jitter @ 200MHz (12kHz – 20MHz): 1.27ps (typical)

• Cycle-to-cycle jitter: 25ps (maximum)

• I²C support with readback capabilities up to 400kHz

• Spread Spectrum for electromagnetic interference (EMI) reduction

• 3.3V core/1.5V to 2.0V output operating supply

• 0°C to 70°C ambient operating temperature

• Available lead-free (RoHS 6) package

• PCI Express Gen2 Jitter Compliant

HiPerClockS™

Block Diagram

Pin Assignment

SRCC4

SRCT4

SRCT3

SRCC3

V_SS

24

23

1

2

XTAL_IN ^25MHz

4

Divider

Network

SRCT[1:4]

SRCC[1:4]

OSC

PLL

4

3

4

22

21

VDDO

SDATA

XTAL_OUT

V_DDO

SRCT2

SRCC2

SRCT1

5

6

7

20

19

18

17

SCLK

XTAL_OUT

XTAL_IN

Pullup

SDATA

I²C

SCLK

Logic

8

9

10

11

12

SRCC1

V_SS

V

DD

SS

16

15

14

13

V_DD

V_SS

nc

VDDA

VSS

nc

ICS842S104

24-Lead TSSOP

4.4mm x 7.8mm x 0.925mm package body

G Package

Top View

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Table 1. Pin Descriptions

Number

Name

Type

Output

Description

1, 2

SRCT3, SRCC3

Differential output pair. HSTL interface levels.

3, 9,

11, 13, 16

V_SS

Power

Power supply ground.

4, 22

5, 6

V_DDO

SRCT2, SRCC2

SRCT1, SRCC1

V_DD

Power

Output

Power

Unused

Power

Input

Output power supply pins.

Differential output pair. HSTL interface levels.

Core supply pins.

7, 8

10, 17

12, 15

14

nc

No connect.

V_DDA

Analog supply for PLL.

18, 19

XTAL_IN, XTAL_OUT

Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.

I²C compatible SCLK. This pin has an internal pullup resistor.

LVCMOS/LVTTL interface levels.

I²C compatible SDATA. This pin has an internal pullup resistor.

LVCMOS/LVTTL interface levels.

20

SCLK

Input

Pullup

21

SDATA

I/O

23, 24

SRCT4, SRCC4

Output

Differential output pair. HSTL interface levels.

NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Symbol

C_IN

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

pF

Input Capacitance

Input Pullup Resistor

2

R_PULLUP

51

kΩ

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer, a

two-signal I²C serial interface is provided. Through the Serial Data

Interface, various device functions, such as individual clock output

buffers, can be individually enabled or disabled. The registers

associated with the serial interface initialize to their default setting

upon power-up, and therefore, use of this interface is optional. Clock

device register changes are normally made upon system

initialization, if any are required.

Data Protocol

The clock driver serial protocol accepts byte write, byte read, block

write and block read operations from the controller. For block

write/read operation, the bytes must be accessed in sequential order

from lowest to highest byte (most significant bit first) with the ability to

stop after any complete byte has been transferred. For byte write and

byte read operations, the system controller can access individually

indexed bytes. The offset of the indexed byte is encoded in the

command code, as described in Table 3A.

The block write and block read protocol is outlined in Table 3B, while

Table 3C outlines the corresponding byte write and byte read

protocol. The slave receiver address is 11010010 (D2h).

Table 3A.Command Code Definition

Bit

7

Description

0 = Block read or block write operation, 1 = Byte read or byte write operation.

Chip select address, set to “00” to access device.

6:5

4:0

Byte offset for byte read or byte write operation. For block read or block write operations, these bits must be “00000”.

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Table 3B. Block Read and Block Write Protocol

Bit

1

Description = Block Write

Start

Bit

1

Description = Block Read

Start

2:8

Slave address - 7 bits

Write

2:8

9

Slave address - 7 bits

Write

9

10

Acknowledge from slave

Command Code - 8 bits

Acknowledge from slave

Byte Count - 8 bits

Acknowledge from slave

Data byte 1 - 8 bits

Acknowledge from slave

Data byte 2 - 8 bits

Acknowledge from slave

Data Byte/Slave Acknowledges

Data Byte N - 8 bits

Acknowledge from slave

Stop

10

Acknowledge from slave

Command Code - 8 bits

Acknowledge from slave

Repeat start

11:18

19

11:18

19

20:27

28

20

21:27

28

Slave address - 7 bits

Read = 1

29:36

37

29

Acknowledge from slave

Byte Count from slave - 8 bits

Acknowledge

38:45

46

30:37

38

39:46

47

Data Byte 1 from slave - 8 bits

Acknowledge

48:55

56

Data Byte 2 from slave - 8 bits

Acknowledge

Data Bytes from Slave/Acknowledge

Data Byte N from slave - 8 bits

Not Acknowledge

Table 3C. Byte Read and Byte Write Protocol

Bit

1

Description = Byte Write

Start

Bit

1

Description = Byte Read

Start

2:8

9

Slave address - 7 bits

Write

2:8

9

Slave address - 7 bits

Write

10

Acknowledge from slave

Command Code - 8 bits

Acknowledge from slave

Data Byte - 8 bits

Acknowledge from slave

Stop

10

Acknowledge from slave

Command Code - 8 bits

Acknowledge from slave

Repeat start

11:18

19

11:18

19

20:27

28

20

21:27

28

Slave address - 7 bits

Read

29

Acknowledge from slave

Data from slave - 8 bits

Not Acknowledge

Stop

30:37

38

39

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Control Registers

Table 3D. Byte 0: Control Register 0

Table 3G. Byte 3:Control Register 3

Bit

@Pup

Name

Description

Bit

7

@Pup

Name

Description

Reserved

7

0

Reserved

1

0

1

0

1

Reserved

SRC[T/C]4 Output Enable

0 = Disable (Hi-Z)

1 = Enable

6

5

4

3

1

SRC[T/C]4

SRC[T/C]3

SRC[T/C]2

SRC[T/C]1

5

4

SRC[T/C]3 Output Enable

0 = Disable (Hi-Z)

1 = Enable

3

2

SRC[T/C]2 Output Enable

0 = Disable (Hi-Z)

1 = Enable

1

0

SRC[T/C]1 Output Enable

0 = Disable (Hi-Z)

1 = Enable

Table 3H. Byte 4: Control Register 4

Bit

7

@Pup

Name

Description

Reserved

2

1

0

1

0

Reserved

0

1

Reserved

6

5

4

Table 3E. Byte 1: Control Register 1

3

Bit

7

@Pup

Name

Description

Reserved

2

0

Reserved

1

6

0

5

4

Table 3I. Byte 5: Control Register 5

3

Bit

7

@Pup

Name

Description

Reserved

2

0

Reserved

1

6

0

5

4

Table 3F. Byte 2: Control Register 2

3

Bit

@Pup

Name

Description

2

Spread Spectrum Selection

0 = -0.35%, 1 = -0.5%

1

7

1

SRCT/C

0

6

5

4

3

1

0

1

Reserved

SRC Spread Spectrum

Enable

0 = Spread Off,

1 = Spread On

2

0

SRC

1

0

1

Reserved

FOUTCTL

Reserved

Output Frequency Control

0 = 100MHz

1 = 200MHz

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Table 3J. Byte 6: Control Register 6

Table 3K. Byte 7: Control Register 7

Bit

@Pup

Name

Description

Bit

7

@Pup

Name

Description

REF/N or Hi-Z Select

0 = Hi-Z, 1 = REF/N

0

1

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

7

0

TEST_SEL

6

TEST Clock

5

Mode Entry Control

0 = Normal Operation,

1 = REF/N or Hi-Z Mode

6

0

TEST_MODE

4

3

5

4

3

2

1

0

1

0

1

Reserved

2

Vendor ID Bit 2

1

Vendor ID Bit 1

0

Vendor ID Bit 0

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond

those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect product reliability.

Item

Rating

Supply Voltage, V_DD

4.6V

Inputs, V_I

XTAL_IN

0V to V_DD

Other Inputs

-0.5V to V_DD+ 0.5V

Outputs, I_O

Continuous Current

Surge Current

50mA

100mA

Package Thermal Impedance, θ_JA

77.5°C/W (0 mps)

-65°C to 150°C

Storage Temperature, T_STG

DC Electrical Characteristics

Table 4A. Power Supply DC Characteristics, V_DD= 3.3V 5%, V_DDO= 1.5V to 2.0V, T_A= 0°C to 70°C

Symbol Parameter

Test Conditions

Minimum

3.135

Typical

3.3

Maximum

3.465

V_DD

2.0

Units

V

V_DD

V_DDA

V_DDO

I_DD

Positive Supply Voltage

Analog Supply Voltage

Output Supply Voltage

Power Supply Current

Analog Supply Current

Output Supply Current

V_DD– 0.21

1.5

3.3

V

106

mA

I_DDA

I_DDO

21

7

Table 4B. LVCMOS/LVTTL DC Characteristics, V_DD= 3.3V 5%, T_A= 0°C to 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

V_DD+ 0.3

0.8

Units

V

V_IH

V_IL

I_IH

Input High Voltage

2

Input Low Voltage

Input High Current

Input Low Current

-0.3

V

SDATA, SCLK

V_DD= V_IN= 3.465V

10

µA

I_IL

V_DD= 3.465V, V_IN= 0V

-150

Table 4C. HSTL DC Characteristics, V_DD= 3.3V 5%, V_DDO= 1.5V to 2.0V, T_A= 0°C to 70°C

Symbol Parameter

Test Conditions

Minimum

Typical

Maximum

Units

V_OH

V_OL

Output High Voltage; NOTE 1

0.9

0

1.2

0.4

V

Output Low Voltage; NOTE 1

Output Crossover Voltage;

NOTE 2

V_OX

40% x (V_OH- V_OL) + V_OL

0.6

65% x (V_OH- V_OL) + V_OL

1.1

%

V

Peak-to-Peak Output Voltage

Swing

V_SWING

NOTE 1: Outputs terminated with 50Ω to GND.

NOTE 2: Defined with respect to output voltage swing at a given condition.

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Table 5. Crystal Characteristics

Parameter

Test Conditions

Minimum

Typical

Fundamental

25

Maximum

Units

Mode of Oscillation

Frequency

MHz

Ω

Equivalent Series Resistance (ESR)

Shunt Capacitance

50

7

pF

NOTE: Characterized using an 18pF parallel resonant crystal.

AC Electrical Characteristics

Table 6. AC Characteristics, V_DD= 3.3V 5%, T_A= 0°C to 70°C

Symbol

Parameter

Test Conditions

FOUTCTL = 0

FOUTCTL = 1

Minimum

Typical

100

Maximum

Units

MHz

f_MAX

Output Frequency

Reference frequency

200

fref

25

ƒ= 200MHz,

25MHz crystal input

t_{REFCLK_HF_RMS}Phase Jitter RMS; NOTE 1, 2

0.95

ps

High Band: 1.5MHz - Nyquist

(clock frequency/2)

ƒ= 200MHz,

25MHz crystal input

t_{REFCLK_LF_RMS}Phase Jitter RMS; NOTE 1

0.31

1.27

ps

Low Band: 10kHz - 1.5MHz

tsk(o)

Output Skew; NOTE 2, 3

50

ps

200MHz, Integration Range:

12kHz – 20MHz

tjit(Ø)

Phase Jitter, RMS (Random)

tjit(cc)

t_L

Cycle-to-Cycle Jitter

PLL Lock Time

PLL Mode

25

60

52

ps

ms

%

odc

Output Duty Cycle

48

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and

reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps rms for t_{REFCLK_HF_RMS}(High

Band) and 3.0 ps RMS for t_{REFCLK_LF_RMS}(Low Band). See IDT Application Note PCI Express Reference Clock Requirements and also the

PCI Express Application section of this datasheet which show each individual transfer function and the overall composite transfer function.

NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.

NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Typical Phase Noise at 200MHz

Offset Frequency (Hz)

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Parameter Measurement Information

3.3V 5%

1.5V to 2.0V

3.3V 5%

Phase Noise Plot

V

DD

SCOPE

Qx

Phase Noise Mask

V

DDO

V

DDA

HSTL

Offset Frequency

f₁

f₂

nQx

GND

0V

RMS Jitter = Area Under the Masked Phase Noise Plot

3.3V HSTL Output Load AC Test Circuit

RMS Phase Jitter

SRCC(1:4)

SRCT(1:4)

SRCC(1:4)

SRCT(1:4)

t_PW

t_PERIOD

➤

tcycle n

tcycle n+1

➤

t_PW

tjit(cc) = tcycle n – tcycle n+1

|

odc =

x 100%

1000 Cycles

t_PERIOD

Cycle-to-Cycle Jitter

Output Duty Cycle/Pulse Width/Period

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Application Information

Power Supply Filtering Technique

As in any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter performance,

power supply isolation is required. The ICS842S104 provides

separate power supplies to isolate any high switching noise from the

outputs to the internal PLL. V_DD,V_DDAand V_DDOshould be

individually connected to the power supply plane through vias, and

0.01µF bypass capacitors should be used for each pin. Figure 1

illustrates this for a generic V_DDpin and also shows that V_DDA

requires that an additional 10Ω resistor along with a 10µF bypass

capacitor be connected to the V_DDApin.

3.3V

V_CC

.01µF

10Ω

V_CCA

.01µF

10µF

Figure 1. Power Supply Filtering

Recommendations for Unused Input and Output Pins

Inputs:

Outputs:

LVCMOS Control Pins

HSTL Outputs

All control pins have internal pullups; additional resistance is not

required but can be added for additional protection. A 1kΩ resistor

can be used.

All unused HSTL outputs can be left floating. We recommend that

there is no trace attached. Both sides of the differential output pair

should either be left floating or terminated.

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Crystal Input Interface

The ICS842S104 has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in Figure

2 below were determined using a 25MHz, 18pF parallel resonant

crystal and were chosen to minimize the ppm error. The optimum C1

and C2 values can be slightly adjusted for different board layouts.

XTAL_IN

C1

18pF

X1

18pF Parallel Crystal

XTAL_OUT

C2

18pF

Figure 2. Crystal Input Interface

Overdriving the XTAL Interface

The XTAL_IN input can accept a single-ended LVCMOS signal

through an AC coupling capacitor. A general interface diagram is

shown in Figure 3A. The XTAL_OUT pin can be left floating. The

maximum amplitude of the input signal should not exceed 2V and the

input edge rate can be as slow as 10ns. This configuration requires

that the output impedance of the driver (Ro) plus the series

resistance (Rs) equals the transmission line impedance. In addition,

matched termination at the crystal input will attenuate the signal in

half. This can be done in one of two ways. First, R1 and R2 in parallel

should equal the transmission line impedance. For most 50Ω

applications, R1 and R2 can be 100Ω. This can also be

accomplished by removing R1 and making R2 50Ω. By overdriving

the crystal oscillator, the device will be functional, but note, the device

performance is guaranteed by using a quartz crystal.

3.3V

R1

100

C1

Ro

~ 7 Ohm

Zo = 50 Ohm

XTAL_I N

RS

43

0.1uF

R2

Driver_LVCMOS

100

XTAL_OU T

Crystal Input Interf ace

Figure 3A. General Diagram for LVCMOS Driver to XTAL Input Interface

VCC=3.3V

C1

Zo = 50 Ohm

XTAL_IN

0.1uF

R1

Zo = 50 Ohm

50

XTAL_OUT

LVPECL

Cry stal Input Interface

R2

50

R3

50

Figure 3B. General Diagram for LVPECL Driver to XTAL Input Interface

ICS842S104CG REVISION A MARCH 17, 2010 12

ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Termination for HSTL Outputs

VDDO

VDD

Zo = 50

+

-

Zo = 50

HSTL

R1

R2

50

ICS HiPerClockS

HSTL Driver

Figure 4. HSTL Output Termination

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Schematic Example

Figure 5 shows an example of ICS842S104 application schematic. In

this example, the device is operated at V_DD= 3.3V and V_DDO= 1.8V.

Both input options are shown. The device can either be driven using

a quartz crystal or a 3.3V LVCMOS signal. The C1 and C2 = 18pF

are recommended for frequency accuracy. For different board

layouts, the C1 and C2 may be slightly adjusted for optimizing

fequency accuracy. The LVHSTL output driver termination examples

are shown in this schematic. The decoupling capacitor should be

located as close as possible to the power pin.

Logic Control Input Examples

Zo = 50 Ohm

SRCT1

Set Logic

Input to

'1'

Set Logic

Input to

'0'

VDD

SRCC1

+

VDD

VDDO

RU1

1K

RU2

Not Install

Zo = 50 Ohm

-

To Logic

Input

To Logic

Input

pins

R1

50

R2

50

RD1

RD2

1K

U1

Not Install

VDD=3.3V

VDDO=1.8V

Zo = 50 Ohm

SRCT4

SRCC4

VDD

VDDA

C3

+

-

R3

10

VDD

C4

VDDO

10uF

0.01u

Zo = 50 Ohm

25MHz

C2

X1

18pF

VDD

18pF

R4

50

R5

50

C1

18pF

R6

SP

R7

SP

VDD

VDDO

(U1-10)

(U1-17)

(U1-4) _VDDO(U1-22)

J1

VDD

R8

0

SDA

5

4

3

2

1

C5

0.1uF

C6

C7

C8

R9

0

0.1uF

SCL

Figure 5. ICS842S104 Schematic Example

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

PCI Express Application Note

PCI Express jitter analysis methodology models the system response

to reference clock jitter. The below block diagram shows the most

frequently used Common Clock Architecture in which a copy of the

reference clock is provided to both ends of the PCI Express Link.

In the jitter analysis, the Tx and Rx serdes PLLs are modeled as well

as the phase interpolator in the receiver. These transfer functions are

called H1, H2, and H3 respectively. The overall system transfer

function at the receiver is:

For PCI Express Gen 1, one transfer function is defined and the

evaluation is performed over the entire spectrum: DC to Nyquist (e.g

for a 100MHz reference clock: 0Hz to 50MHz) and the jitter result is

reported in peak-peak. For PCI Express Gen 2, two transfer functions

are defined with 2 evaluation ranges and the final jitter number is

reported in rms. The two evaluation ranges for PCI Express Gen 2

are 10kHz - 1.5MHz (Low Band) and 1.5MHz - Nyquist (High Band).

The below plots show the individual transfer functions as well as the

overall transfer function Ht. The respective -3 dB pole frequencies for

each transfer function are labeled as F1 for transfer function H1, F2

for H2, and F3 for H3. For a more thorough overview of PCI Express

jitter analysis methodology, please refer to IDT Application Note PCI

Express Reference Clock Requirements.

t(s) = H3(s) × [H1(s) – H2(s

The jitter spectrum seen by the receiver is the result of applying this

system transfer function to the clock spectrum X(s) and is:

s) = X(s) × H3(s) × [H1(s) – H2(

In order to generate time domain jitter numbers, an inverse Fourier

Transform is performed on X(s)*H3(s) * [H1(s) - H2(s)].

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Magnitude of Transfer Functions - PCIe Gen 1

0

-10

-20

-30

-40

-50

F1: 2.2e+007 F2: 1.5e+006

F3: 1.5e+006

H1

H2

H3

Ht=(H1-H2)*H3

-60

10³

10⁴

10⁵

10⁶

10⁷

Frequency (Hz)

PCIe Gen 1 Magnitude of Transfer Function

Magnitude of Transfer Functions - PCIe Gen 2B

Magnitude of Transfer Functions - PCIe Gen 2A

0

F1: 1.6e+007 F2: 8.0e+006

F3: 1.0e+006

F1: 1.6e+007 F2: 5.0e+006

F3: 1.0e+006

-10

-20

-30

-20

-30

-40

H1

H2

H3

-50

-60

H2

H3

-50

-60

Ht=(H1-H2)*H3

10³

10⁴

10⁵

10⁶

10⁷

10³

10⁴

10⁵

10⁶

10⁷

Frequency (Hz)

PCIe Gen 2A Magnitude of Transfer Function

PCIe Gen 2B Magnitude of Transfer Function

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Power Considerations

This section provides information on power dissipation and junction temperature for the ICS842S104.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the ICS842S104 is the sum of the core power plus the power dissipated in the load(s).

The following is the power dissipation for V_DD= 3.3V + 5% = 3.465V, which gives worst case results.

NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

•

The maximum current at 70°C is as follows:

I_{DD_MAX}= 101.7mA

I_{DDA_MAX}= 19.4mA

•

Power (core)_MAX= V_{DD_MAX}* (I_{DD_MAX}+ I_{DDA_MAX}) = 3.465V * (101.7mA + 19.4mA) = 419.6mW

Power (outputs)_MAX= 32mW/Loaded Output pair

If all outputs are loaded, the total power is 4 * 32mW = 128mW

Total Power__MAX(3.465V, with all outputs switching) = 419.6mW + 128mW = 547.6mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The

maximum recommended junction temperature for HiPerClockS devices is 125°C. Limiting the internal transistor junction temperature, Tj, to

125°C ensures that the bond wire and bond pad temperature remains below 125°C.

The equation for Tj is as follows: Tj = θ_JA* Pd_total + T_A

Tj = Junction Temperature

θ_JA= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

T_A= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ_JAmust be used. Assuming no air flow and

a multi-layer board, the appropriate value is 77.5°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.548W * 77.5°C/W = 112.5°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of

board (multi-layer).

Table 7. Thermal Resistance θ_JAfor 24 Lead TSSOP, Forced Convection

θ_JAby Velocity

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

77.5°C/W

73.2°C/W

71.0°C/W

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

3. Calculations and Equations.

The purpose of this section is to calculate the power dissipation for the HSTL output pair.

HSTL output driver circuit and termination are shown in Figure 6.

V_DDO

Q1

V_OUT

RL

50Ω

Figure 6. HSTL Driver Circuit and Termination

To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.

Pd_H is power dissipation when the output drives high.

Pd_L is the power dissipation when the output drives low.

Pd_H = (V_{OH_MAX}/R_L) * (V_{DD_MAX}- V_{OH_MAX}

Pd_L = (V_{OL_MAX}/R_L)* (V_{DD_MAX}- V_{OL_MAX}

)

Pd_H = (1.2V/50Ω) * (2.0V - 1.2V) = 19.2mW

Pd_L = (0.4V/50Ω) * (2.0V - 0.4V) = 12.8mW

Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW

ICS842S104CG REVISION A MARCH 17, 2010

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ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Reliability Information

Table 8. θ_JAvs. Air Flow Table for a 24 Lead TSSOP

θ_JAvs. Air Flow

Meters per Second

0

1

2.5

Multi-Layer PCB, JEDEC Standard Test Boards

77.5°C/W

73.2°C/W

71.0°C/W

Transistor Count

The transistor count for ICS842S104 is: 11,891

Package Outline and Package Dimensions

Package Outline - G Suffix for 24 Lead TSSOP

Table 9. Package Dimensions

All Dimensions in Millimeters

Symbol

Minimum

Maximum

N

A

24

1.20

0.15

1.05

0.30

0.20

7.90

A1

A2

b

0.05

0.80

0.19

0.09

7.70

c

D

E

6.40 Basic

E1

e

4.30

4.50

0.65 Basic

L

0.45

0°

0.75

8°

α

aaa

0.10

Reference Document: JEDEC Publication 95, MO-153

ICS842S104CG REVISION A MARCH 17, 2010

19

ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

Ordering Information

Table 10. Ordering Information

Part/Order Number

842S104CGLF

842S104CGLFT

Marking

ICS842S104CGL

Package

“Lead-Free” 24 Lead TSSOP

Shipping Packaging

Tube

2500 Tape & Reel

Temperature

0°C to 70°C

NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal

commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not

recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product

for use in life support devices or critical medical instruments.

ICS842S104CG REVISION A MARCH 17, 2010

20

ICS842S104 Data Sheet

CRYSTAL-TO- HSTL 100MHZ / 200MHZ PCI EXPRESS™ CLOCK SYNTHESIZER

6024 Silver Creek Valley Road Sales

Technical Support

800-345-7015 (inside USA)

netcom@idt.com

San Jose, California 95138

+408-284-8200 (outside USA) +480-763-2056

Fax: 408-284-2775

www.IDT.com/go/contactIDT

DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document,

including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not

guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the

suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any

license under intellectual property rights of IDT or any third parties.

IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT

product in such a manner does so at their own risk, absent an express, written agreement by IDT.

Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third

party owners.


型号：	ICS842S104
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Crystal-to-HSTL 100MHz / 200MHz PCI Express™ Clock Synthesizer 水晶到100MHz的HSTL / 200MHz的PCI Express的™时钟合成器 PC 时钟
文件：	总21页 (文件大小：921K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS842S104 [IDT]

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