MPC948FAR2 [IDT]
Low Skew Clock Driver, 948 Series, 12 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32;
| 型号： | MPC948FAR2 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew Clock Driver, 948 Series, 12 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32 PC 驱动 输入元件 输出元件 逻辑集成电路 |
| 文件： | 总4页 (文件大小：262K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC948/D
Freescale Semiconductor, Inc.
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The MPC948 is a 1:12 low voltage clock distribution chip. The device
features the capability to select either a differential LVPECL or a LVTTL
compatible input. The 12 outputs are LVCMOS or LVTTL compatible and
feature the drive strength to drive 50Ω series terminated transmission
lines. With output–to–output skews of 350ps, the MPC948 is ideal as a
clock distribution chip for the most demanding of synchronous systems.
For a similar product targeted at a lower price/performance point, please
consult the MPC947 data sheet.
LOW VOLTAGE
1:12 CLOCK
DISTRIBUTION CHIP
• Clock Distribution for PowerPC 620 L2 Cache
• LVPECL or LVCMOS/LVTTL Clock Input
• 350ps Maximum Output–to–Output Skew
• Drives Up to 24 Independent Clock Lines
• Maximum Output Frequency of 150MHz
• Synchronous Output Enable
• Tristatable Outputs
• 32–Lead LQFP Packaging
• 3.3V VCC Supply Voltage
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
With an output impedance of approximately 7Ω, in both the HIGH and
LOW logic states, the output buffers of the MPC948 are ideal for driving
series terminated transmission lines. More specifically, each of the 12
MPC948 outputs can drive two series terminated 50Ω transmission lines.
With this capability, the MPC948 has an effective fanout of 1:24 in ap-
plications where each line drives a single load. With this level of fanout,
the MPC948 provides enough copies of low skew clocks for high perfor-
mance synchronous systems, including use as a clock distribution chip
for the L2 cache of a PowerPC 620 based system.
6
The differential LVPECL inputs of the MPC948 allow the device to interface directly with a LVPECL fanout buffer like the
MC100LVE111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH
on the TTL_CLK_Sel pin will select the TTL level clock input.
All of the control inputs are LVCMOS/LVTTL compatible. The MPC948 provides a synchronous output enable control to allow
for starting and stopping of the output clocks. A logic high on the Sync_OE pin will enable all of the outputs. Because this control
is synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. In addition, for board level test,
the outputs can be tristated via the tristate control pin. A logic LOW applied to the Tristate input will force all of the outputs into
high impedance. Note that all of the MPC948 inputs have internal pullup resistors.
The MPC948 is fully 3.3V compatible. The 32–lead LQFP package was chosen to optimize performance, board space and
cost of the device. The 32–lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
PowerPC is a trademark of International Business Machines Corporation.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
615
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC948
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Figure 1. Logic Diagram
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FUNCTION TABLES
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TTL_CLK_Sel
Input
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0
1
PECL_CLK
TTL_CLK
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Sync_OE
Outputs
MPC948
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0
1
Disabled
Enabled
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Tristate
Outputs
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6
0
1
Tristate
Enabled
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Figure 2. 32–Lead Pinout (Top View)
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Figure 3. Sync_OE Timing Diagram
616
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC948
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
–0.3
–0.3
Max
Unit
V
V
V
Supply Voltage
Input Voltage
Input Current
4.6
CC
I
V
+ 0.3
V
DD
I
IN
20
mA
°C
T
Stor
Storage Temperature Range
–40
125
*
Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V 0.3V)
Symbol
Characteristic
Input HIGH Voltage
Min
Typ
Max
Unit
Condition
V
V
PECL_CLK
Other
2.135
2.0
2.42
3.60
V
Single Ended Spec
IH
Input LOW Voltage
PECL_CLK
Other
1.49
1.825
0.8
V
Single Ended Spec
IL
V
V
V
V
I
Peak–to–Peak Input Voltage
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
PECL_CLK
PECL_CLK
300
1000
mV
V
PP
V
– 2.0
V
– 0.6
Note 1.
CMR
OH
OL
CC
CC
2.5
V
I
I
= –20mA (Note 2.)
= 20mA (Note 2.)
OH
0.4
V
OL
100
4
µA
pF
pF
mA
Note 3.
IN
C
C
Input Capacitance
IN
pd
Power Dissipation Capacitance
25
22
Per Output
I
Maximum Quiescent Supply Current
30
CC
1. V
is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “HIGH” input is within
CMR
the V
range and the input swing lies within the V specification.
CMR
PP
2. The MPC948 can drive 50Ω transmission lines on the incident edge. Each output can drive one 50Ω parallel terminated transmission line to
the termination voltage of V = V /2. Alternately, the device drives up to two 50Ω series terminated transmission lines.
TT
CC
6
3. Inputs have pull–up resistors which affect input current, PECL_CLK has a pull–down resistor.
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V 0.3V, Assumes 50% input duty cycle)
Symbol
Characteristic
Maximum Input Frequency
Propagation Delay
Min
Typ
Max
Unit
MHz
ns
Condition
Note 4.
F
150
max
t
PECL_CLK to Q
TTL_CLK to Q
4.0
4.4
8.0
8.9
Note 4.
pd
t
t
Output–to–Output Skew
Part–to–Part Skew
350
ps
ns
Note 4.
sk(o)
PECL_CLK to Q
TTL_CLK to Q
1.5
2.0
Notes 4., 5.
sk(pr)
t
t
t
Output Pulse Width
t
/2 –
800
t
/2 +
800
ps
ns
ns
Notes 4., 6.
Measured at V /2
pwo
s
CYCLE
CYCLE
CC
Setup Time
Hold Time
Sync_OE to PECL_CLK
Sync_OE to TTL_CLK
1.0
0.0
Notes 4., 7.
Notes 4., 7.
PECL_CLK to Sync_OE
TTL_CLK to Sync_OE
0.0
1.0
h
t
t
,t
Output Enable Time
Output Disable Time
Output Rise/Fall Time
3
3
11
11
ns
ns
ns
PZL PZH
,t
PLZ PHZ
t , t
r
0.20
1.0
0.8V to 2.0V
f
4. Driving 50Ω transmission lines.
5. Part–to–part skew at a given temperature and voltage.
6. Assumes 50% input duty cycle.
7. Setup and Hold times are relative to the falling edge of the input clock.
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
617
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
MPC948
APPLICATIONS INFORMATION
Driving Transmission Lines
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
The MPC948 clock driver was designed to drive high speed
signals in a terminated transmission line environment. To pro-
vide the optimum flexibility to the user the output drivers were
designed to exhibit the lowest impedance possible. With an
output impedance of approximately 10Ω the drivers can drive
either parallel or series terminated transmission lines. For
more information on transmission lines the reader is referred to
application note AN1091 in the Timing Solutions data book
(DL207/D).
At the load end the voltage will double, due to the near unity
reflection coefficient, to 2.8V. It will then increment towards the
quiescent 3.0V in steps separated by one round trip delay (in
this case 4.0ns).
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ꢜ
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a point–to–
point scheme either series terminated or parallel terminated
transmission lines can be used. The parallel technique termi-
nates the signal at the end of the line with a 50Ω resistance to
VCC/2. This technique draws a fairly high level of DC current
and thus only a single terminated line can be driven by each
output of the MPC948 clock driver. For the series terminated
case however there is no DC current draw, thus the outputs
can drive multiple series terminated lines. Figure 4 illustrates
an output driving a single series terminated line vs two series
terminated lines in parallel. When taken to its extreme the fan-
out of the MPC948 clock driver is effectively doubled due to its
capability to drive multiple lines.
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Figure 5. Single versus Dual Waveforms
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ꢌΩ
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ꢘ Ω
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 6 should be used. In this case the series terminating
resistors are reduced such that when the parallel combination
is added to the output buffer impedance the line impedance is
perfectly matched.
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6
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ꢦꢥ ꢧꢧ ꢊꢨ
ꢪ
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ꢩ
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ꢠ
ꢌΩ
ꢌΩ
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ꢨ
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ꢩ
ꢩ
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ꢘ Ω
ꢘ Ω
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ꢢΩ
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ꢤꢏ ꢃꢞ ꢟ ꢝ
ꢕ
ꢉ ꢥꢀꢏ ꢥꢀ
ꢦ ꢥꢧꢧꢊ ꢨ
ꢪ
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ꢩ
ꢩ
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ꢌΩ
ꢌΩ
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ꢩ
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ꢘ
ꢡΩ
ꢡΩ
Figure 4. Single versus Dual Transmission Lines
The waveform plots of Figure 5 show the simulation results
ꢢΩ
of an output driving a single line vs two lines. In both cases the
drive capability of the MPC948 output buffers is more than suf-
ficient to drive 50Ω transmission lines on the incident edge.
Note from the delay measurements in the simulations a delta
of only 43ps exists between the two differently loaded outputs.
This suggests that the dual line driving need not be used exclu-
sively to maintain the tight output–to–output skew of the
MPC948. The output waveform in Figure 5 shows a step in the
waveform, this step is caused by the impedance mismatch
7Ω + 36Ω ꢀ 36Ω = 50Ω ꢀ 50Ω
25Ω = 25Ω
Figure 6. Optimized Dual Line Termination
SPICE level output buffer models are available for engi-
seen looking into the driver. The parallel combination of the neers who want to simulate their specific interconnect
43Ω series resistor plus the output impedance does not match schemes. In addition IV characteristics are in the process of
the parallel combination of the line impedances. The voltage being generated to support the other board level simulators in
wave launched down the two lines will equal:
general use.
618
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
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