CYPD3184A1-24LQXQ [INFINEON]
PG-VQFN-24 tray packing secondary side controller with PD controller and synchronous rectifier with optocoupler-feedback for USB PD charger and adapters;型号: | CYPD3184A1-24LQXQ |
厂家: | Infineon |
描述: | PG-VQFN-24 tray packing secondary side controller with PD controller and synchronous rectifier with optocoupler-feedback for USB PD charger and adapters 光电二极管 |
文件: | 总28页 (文件大小:403K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EZ-PD™ PAG1S - CYPD3184
USB PD power adapter SR controller
General description
EZ-PD™ PAG1S is an integrated synchronous rectifier (SR) controller and charging port controller. EZ-PD™ PAG1S
is designed to fit into a traditional primary-controlled flyback system with secondary-side sensing and regulation.
EZ-PD™ PAG1S is targeted towards power adapters, it fits well into high-efficiency AC-DC flyback designs for USB
Power Delivery, Qualcomm Quick Charge, and other standard charging protocols. EZ-PD™ PAG1S also supports
USB Power Delivery (USB PD) programmable power supply (PPS) mode.
Applications
• USB PD 3.0 PPS power adapter
• Quick Charge 4.0 power adapter
• Power adapters supporting both USB PD and legacy charging
Features
• Integrates secondary-side regulation, synchronous rectifier (SR), and charging port controller
• Optimized efficiency across line and load range
• Supports both critical conduction mode (CrCM) and valley switching mode
• Switching frequency range of 20 kHz to 150 kHz
• Supports constant voltage (CV) and constant current (CC) modes of operation.
• Configurable overvoltage protection (OVP), undervoltage protection (UVP), overcurrent protection (OCP), short
circuit protection (SCP), and over-temperature protection (OTP)
• Supports USB PD2.0, PD 3.0 with PPS, QC4+, QC 4.0, QC 3.0, QC 2.0, Samsung AFC, Apple charging, and BC v1.2
charging protocols
• Integrates low-side current sense amplifier (LSCSA), 2x VBUS discharge FETs, and a NFET gate driver to drive
the load switch
• Protects against accidental VBUS to CC short; ESD protection on CC, VBUS, and DP/DM lines
• 24-QFN package with –40°C to +105°C extended industrial temperature range
Functional block diagram
SR_CPN
VDDD
VCCD
VBUS_C
SR_CPP
SR_GDRV
V
VBUS_IN
VBUS_CTRL
OV, UV
OV, UV
SR Sense
Slew Rate
Controlled NFET
Gate Driver
SR_VSS
SR_SEN
VBUS_IN
Discharge
SR Gate Driver
and Doubler
VBUS_C
Discharge
LDO
Zero Crossing
Detect (ZCD)
Negative Sense
HV
Regulator
CC1
CC2
BMC
PHY
Protocol Engine
DP_GPIO5
DM_GPIO4
CC
Charger
Detect
VBUS_IN
ADC
CV
Reference
Reference
Error
Amplifier
(CV)
Error
Amplifier
(CC)
LSCSA
FB
XRES
GPIOs
POR/RESET
IDACs
SCP
CSN
EA_OUT
CC_COMP_GPIO2
VSS
GPIO3
CSP
GPIO0
GPIO1
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Table of contents
Table of contents
General description ...........................................................................................................................1
Applications......................................................................................................................................1
Features ...........................................................................................................................................1
Functional block diagram...................................................................................................................1
Table of contents...............................................................................................................................2
1 Pinout............................................................................................................................................3
1.1 Pin description ........................................................................................................................................................5
2 Application overview ......................................................................................................................9
2.1 USB Power Delivery power adapter.......................................................................................................................9
3 Functional description ..................................................................................................................10
3.1 Start-up behavior..................................................................................................................................................10
3.2 Fault protection ....................................................................................................................................................10
3.3 Power modes ........................................................................................................................................................10
4 Electrical specifications.................................................................................................................11
4.1 Absolute maximum ratings ..................................................................................................................................11
4.2 Device-level specifications ...................................................................................................................................12
4.3 Functional block specifications ...........................................................................................................................13
4.4 I/O specifications ..................................................................................................................................................19
4.5 System resources specifications..........................................................................................................................20
5 Ordering information ....................................................................................................................21
5.1 Ordering code definitions.....................................................................................................................................21
6 Packaging ....................................................................................................................................22
7 Acronyms.....................................................................................................................................24
8 Document conventions..................................................................................................................26
8.1 Units of measure ...................................................................................................................................................26
Revision history ..............................................................................................................................27
Datasheet
2 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Pinout
1
Pinout
1
2
3
4
5
6
18
17
16
15
14
13
SR_GDRV
SR_VSS
SR_SEN
XRES
VBUS_C
DP_GPIO5
DM_GPIO4
VSS
EPAD
CC1
GPIO0
GPIO1
CC2
Figure 1
24-pin QFN pin map
Datasheet
3 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Pinout
Table 1
EZ-PD™ PAG1S pin description
Pin name
Pin number
Description
1
2
3
4
SR_GDRV
SR_VSS
SR_SEN
XRES
Synchronous-rectifier NFET gate driver
Synchronous-rectifier NFET ground terminal
Synchronous-rectifier NFET drain terminal
External reset input
5
GPIO0
GPIO P0.0
6
GPIO1
GPIO P0.1
7
8
9
CC_COMP_GPIO2
EA_OUT
FB
Pin for constant current mode compensation capacitor/GPIO P0.2
Error amplifier output
Error amplifier feedback
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CSN
CSP
GPIO3
CC2
CC1
VSS
Low-side current sense amplifier negative input
Low-side current sense amplifier positive input
GPIO P0.3
Power Delivery communication channel 2
Power Delivery communication channel 1
Ground
USB D-/SWD_DATA/GPIO P0.4
USB D+/SWD_CLK/GPIO P0.5
USB Type-C VBUS monitor input
Load switch NFET gate control
Power source input
1.8-V core voltage LDO output
3.0 V–5.5 V internal LDO Output
SR doubler capacitor negative pin
SR doubler capacitor positive pin
EPAD for ground
DM_GPIO4
DP_GPIO5
VBUS_C
VBUS_CTRL
VBUS_IN
VCCD
VDDD
SR_CPN
SR_CPP
EPAD
Datasheet
4 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Pinout
1.1
Pin description
SR_GDRV, SR_VSS, SR_SEN, SR_CPP, SR_CPN.
EZ-PD™ PAG1S senses the voltage across the SR NFET and appropriately controls the gate driver to achieve
optimum efficiency. The gate driver (SR_GDRV) can be driven to internal VDDD or twice of VDDD to achieve better
RDS-On of the external NFET. The Gate Driver can be driven to twice of VDDD using an internal doubler circuit,
with the doubler capacitor connected across SR_CPP and SR_CPN pins. The source terminal of the SR FET shall
be connected to SR_VSS pin.
EZ-PD™ PAG1S supports SR in QR/CrCM and valley switching. The SR sense block supports negative sense detect
and Zero Crossing Detect (ZCD). The voltage at the drain node of the external NFET is sensed using a resistive
divider. The internal resistor is 2 k, the external resistor needs to be chosen such that the voltage at the SR_SEN
pin does not exceed 21.5 V.
The external resistance on SR_SEN pin depends on turns ratio of power transformer. Table 2 provides the values
required for various values of turns ratio.
Table 2
External resistance on SR_SEN vs turns ratio
Primary : Secondary turns ratio
Rext ()
10K
9K
4:1
5:1
6:1
7:1
8:1
9:1
10:1
8K
7K
6K
5K
4K
The fast-negative sense comparator can detect a minimum negative voltage of 100 mV to –200 mV on SR_SEN
pin. Similarly, ZCD can detect a minimum threshold of –16 mV to 0 mV on the SR_SEN pin. See Figure 2 and
Figure 3 for the waveforms representing the SR_GDRV functionality in CrCM and valley switching mode.
Datasheet
5 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Pinout
Both FET OFF
Primary FET OFF,
SR FET ON
Primary FET OFF,
SR FET ON
Primary FET ON,
SR FET OFF
Primary FET ON,
SR FET OFF
Primary Current
Secondary Current
Feed forward sensing
Peak detect
SR_SEN
ZCD
Negative sense
detect
SR_GDRV
Time
Figure 2
SR_SEN and SR_GDRV in QR/CrCM mode
Datasheet
6 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Pinout
Both FET OFF
Primary FET OFF,
SR FET ON
Primary FET OFF,
SR FET ON
Primary FET ON,
SR FET OFF
Primary FET ON,
SR FET OFF
Primary Current
Secondary Current
Feed forward sensing
Valley detect
SR_SEN
ZCD
Negative sense
detect
SR_GDRV
Time
Figure 3
SR_SEN and SR_GDRV in valley switching mode
1.1.1
FB, EA_OUT, CC_COMP_GPIO2
EZ-PD™ PAG1S integrates two error amplifier blocks which handles secondary output sensing and regulation for
CV and CC modes. This block is responsible for both constant voltage and constant current operations. The
output of the error amplifier is routed to the EA_OUT pin. EA_OUT can further drive an opto-isolator to provide
feedback to the primary controller. The negative input of the error amplifier is the feedback (FB) pin and the
positive input is internal reference of 0.744 V. The FB pin has internal resistor divider of 200 k and 35 k, this
divider sets a default voltage of 0.744 V at FB pin when VBUS_IN is at 5V. Based on the desired VBUS_C output,
the voltage at the FB pin will be varied using internal current source/sink IDACs. An external compensation
network is required between FB pin and EA_OUT pin, as shown in Figure 4.
Constant current operation makes use of an internal LSCSA, the output of which feeds into an independent error
amplifier as shown in Figure 4. EZ-PD™ PAG1S error amplifier can ensure constant voltage regulation over 3.3 V
to 21.5 V range and constant current regulation over 1 A to 3 A as required by the USB PD PPS specification.
1.1.2
CC1, CC2
CC1 and CC2 are the communication channels for USB PD protocol. EZ-PD™ PAG1S integrates a USB PD
transceiver consisting of a transmitter and receiver that communicate biphase mark code (BMC) encoded data
over the configuration channel (CC) channels as per the USB PD standard. All communication is half-duplex. The
physical layer implements collision avoidance to minimize communication errors on the channel. This block
includes all termination resistors (Rp) and their switches as required by the USB PD specification. An external
390-pF capacitor is required on both the CC1 and CC2 pins.
Datasheet
7 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Pinout
1.1.3
DP_GPIO4, DM_GPIO5
The DP and DM lines are the standard USB D+ and D– lines. EZ-PD™ PAG1S integrates a charge detect block, which
handles legacy charging protocols such as BC 1.2, Quick Charge, Apple charging, and Samsung AFC. This block
integrates all the terminations required for these charging protocols and no external components are required.
When legacy charging is not required in the system, the same DP and DM lines can be reused as standard GPIOs.
1.1.4
VBUS_IN, VDDD, VCCD
EZ-PD™ PAG1S integrates a high-voltage regulator, which is powered from the VBUS_IN rail, the output of the
regulator powers the VDDD rail. The input to the regulator can range from 3.3 V minimum to 21.5 V maximum.
When the input is between 5.5 V to 21.5 V, the typical output of the regulator is 5 V. For inputs from 3.3 V to 5.5 V,
the regulator output is VBUS_IN – 300 mV.
The regulator can drive a maximum load current of 50 mA, which includes the chip current consumption. This
regulator is not expected to drive any external loads or ICs. EZ-PD™ PAG1S also has an internal configurable
discharge path for the VBUS_IN rail, which is used to discharge the VBUS rail during negative voltage transitions.
The regulated supply VDDD, is either used to directly power some internal analog blocks or further regulated
down to 1.8 V VCCD, which powers majority of the core. VDDD and VCCD is brought out on to pins to connect
external capacitors for regulator stability, these are not meant to be used as power supplies.
1.1.5
VBUS_C, VBUS_CTRL
VBUS_C is used to monitor the voltage at the Type-C connector. VBUS_C has an internal configurable discharge
path, which is used to discharge the VBUS_C rail during negative voltage transitions.
The load switch is between VBUS_IN and VBUS_C. EZ-PD™ PAG1S integrates a NFET gate driver to control this
load switch. VBUS_CTRL is the output of this gate driver. To turn off the external NFET, the gate driver drives low.
To turn on the external NFET, it drives the gate to VBUS_IN + 8 V. In addition, there is a clamp circuit to limit the
gate to VBUS_IN + 8 V.
1.1.6
CSP, CSN
EZ-PD™ PAG1S integrates a LSCSA to monitor the load current. CSP is the positive input pin for the LSCSA and
CSN is the negative input. LSCSA offers wide gain options ranging from 5 to 150. Suggested Rsense for LSCSA is
5 m. LSCSA has an active offset cancellation mechanism to improve accuracy.
1.1.7
GPIO0, GPIO1, and GPIO3
EZ-PD™ PAG1S has six GPIOs, out of which three are dedicated GPIOs and the rest are multiplexed with other
functionalities. During power-on and reset, the I/O pins (except GPIO1) are forced to the tristate so as not to
crowbar any inputs and/or cause excess turn-on current. GPIO1 is driven to zero at power-up.
1.1.8
XRES
The XRES pin can be used to initiate a reset, this pin is internally pulled high and needs to be pulled low externally
to trigger reset.
Datasheet
8 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Application overview
2
Application overview
2.1
USB Power Delivery power adapter
Figure 4 shows a power adapter application diagram implementing a primary side controlled synchronous
flyback system. In this system, EZ-PD™ PAG1S engages the error amplifier to take the feedback from the
secondary side and pass it on to the primary controller over an isolation barrier like an opto-isolator. The primary
side controller can be any standard flyback controller. In this topology, EZ-PD™ PAG1S integrates three key
features: secondary side sensing and regulation, SR, and charging port controller.
Full-bridge
Snubber
VBUS_TypeC
VBUS_IN
Rectifier
EMI
Filter
CC_COMP_GPIO2
GD
CS
CC1
VDD700
CC2
EA_OUT
Primary
Flyback
Controller
DP_GPIO5
DM_GPIO4
EZ-PD· PAG1S
FB
FB
GPIO1
GPIO0
GND
Temperature
Sensor
Primary Side
Secondary Side
Figure 4
Power adapter with primary side control application diagram
Datasheet
9 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Functional description
3
Functional description
3.1
Start-up behavior
On power-up, the primary side flyback controller shall start controlling the primary switch using its internal
primary peak current limited soft start mechanism and provide sufficient current to charge the secondary side
output capacitor and the startup current required for EZ-PD™ PAG1S. The secondary output voltage is the input
power supply source of EZ-PD™ PAG1S. Once this voltage at VBUS_IN crosses 3.3 V, EZ-PD™ PAG1S gets powered
up. EZ-PD™ PAG1S firmware boot-up time is in the order of a few milliseconds. Once the boot-up is complete,
EZ-PD™ PAG1S configures the error-amplifier to achieve 5 V secondary output. The output of the error-amplifier
is passed on to the primary controller through an opto-coupler.
3.2
Fault protection
3.2.1
VBUS UVP and OVP
VBUS undervoltage and overvoltage faults are monitored using internal VBUS_IN/VBUS_C resistor dividers. The
fault thresholds and response times are configurable in EZ-PD™ PAG1S. Configurability includes choosing
between auto-restart or latch-off options for each fault.
3.2.2
VBUS OCP and SCP
VBUS overcurrent and short-circuit faults are monitored using internal current sense amplifiers. Same as OVP and
UVP, the OCP and SCP fault thresholds and response times are configurable as well. Configurability includes
choosing between auto-restart or latch-off options for each fault.
3.2.3
OTP
Overtemperature monitoring is done using an external thermistor and internal ADC. The thermistor can be
connected to any free GPIO.
3.2.4
ESD protection
EZ-PD™ PAG1S offers ESD protection on all the pins. The ESD protection level is 2.2-kV HBM and 500-V CDM.
3.2.5
VBUS to CC short protection
EZ-PD™ PAG1S offers protection against accidental short from VBUS_C pin short to CC.
3.3
Power modes
EZ-PD™ PAG1S supports three power modes - Active, Sleep, and Deep Sleep. Transitions between these modes
is handled by the device depending on the operating conditions.
Datasheet
10 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Electrical specifications
4
Electrical specifications
4.1
Absolute maximum ratings
Table 3
Absolute maximum ratings[1]
Description
Parameter
VBUS_IN_MAX
VDDD_MAX
Min
–
–
Typ
–
–
Max
24
6
Unit Details/conditions
Maximum input supply voltage
Maximum supply voltage
Maximum voltage on SR_SEN
pin
GPIO voltage
–
–
V_SR_DRAIN_MAX
VGPIO_ABS
–
–0.5
–
–
–
–
–
–
24
–
V
VDDD + 0.5
–
Maximum voltage on CC1, CC2
voltage
Current per GPIO
Electrostatic discharge human
body model
Electrostatic discharge charged
device model
VCC_PIN_ABS
IGPIO_ABS
24
25
–
–
–
mA
V
–
–
ESD_HBM
2200
ESD_CDM
I_LU
500
–
–
–
–
–
Pin current for latch-up
–100
100
mA
Note
1. Usage of the absolute maximum conditions listed in Table 3 may cause permanent damage to the device.
Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The
maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the
device may not operate to specification.
Datasheet
11 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Electrical specifications
4.2
Device-level specifications
Table 4
DC specifications
Spec ID
Parameter
Description
Min
Typ Max Unit Details/conditions
VDDD output for 5.5 V
SID.PWR.1
VDDD_REG
4.6
5.0 5.4
V
BUS_IN 21.5 V
ILOAD = 0-50 mA
VDDD output for 3.3 V
BUS_IN 5.5 V
Power supply input voltage
Output voltage for core
logic
Bypass capacitor for VCCD
VBUS_IN
0.3
–
SID.PWR.2
SID.PWR.4
SID.PWR.6
SID.PWR.8
SID.PWR.9
VDDD_MIN
VBUS_IN
VCCD
–
–
–
21.5
–
V
V
3.3
–
–
–
1.8
1
Cefc
0.8
1.8
1.2
2.2
X5R ceramic or
better
Decoupling capacitor for
VDDD
Cexc
–
Decoupling
µF
Decoupling capacitor for
VBUS_IN
SID.PWR.10
Cexv
–
1
–
–
–
capacitor required
near the IC pin.
Capacitor between SR_CPP
and SR_CPN pins
X5R ceramic or
better
SID.PWR.10A Cexcpp
0.1
V
BUS_IN = 5 V,
Active current from VBUS_IN
in Type-C attached state
SID.PWR.15
SID.PWR.16
IDD_A
–
–
25
–
–
TA = 25°C,
CC1/CC2 in TX or RX
VBUS_IN = 5 V,
TA = 25°C,
Type-C attached
Sleep current from VBUS_IN
in Type-C attached state
IDD_S_UA
3.5
mA
VBUS_IN = 5 V,
TA = 25°C,
Type-C unattached,
CPU OFF,
UVOV block ON,
WDT Wakeup ON.
Deep Sleep current from
VBUS_IN (Type-C
SID.PWR#16_A I_DS_UA
–
0.75
–
–
unattached)
Voltage allowed on SR_SEN
pin
SID.PWR.17
V_SR_DRAIN
–0.7
21.5
V
–
Table 5
AC specifications
Spec ID
Parameter
Description
Min
Typ Max Unit Details/conditions
SID.PWR.14
Tsleep
Wakeup from Sleep mode
–
0
–
µs
–
Wakeup from Deep Sleep
mode
SID.PWR.14A Tdeepsleep
–
35
–
µs
–
Datasheet
12 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Electrical specifications
4.3
Functional block specifications
Table 6
ADC specifications
Spec ID
DC specifications
Parameter
Description
Min Typ Max
Unit Details/conditions
SID.ADC.1
Resolution
ADC resolution
–
8
–
–
Bits
–
Reference voltage =
VREF_ADC1
Reference voltage =
VREF_ADC2
SID.ADC.2
INL
–2.5
2.5
Integral nonlinearity
SYS.ADC.3
SYS.ADC.4
INL
–1.5
–2.5
–
–
1.5
2.5
LSB Reference voltage =
VREF_ADC1
DNL
Differential nonlinearity
Gain error
Reference voltage =
VREF_ADC2
–
SYS.ADC.5
SYS.ADC.6
DNL
–1.5
–1.5
–
–
1.5
1.5
Gain Error
Reference voltage
generated from
SYS.ADC.7
SYS.ADC.8
VREF_ADC1
VREF_ADC2
VDDDmin
–
VDDDmax
VDDD
ADC reference voltage
V
Reference voltage
generate from
bandgap
1.96
2.0
2.04
AC specifications
Rate of change of
sampled voltage signal
Guaranteed by
design
SID.ADC.9
Slew_Max
–
–
3
V/ms
Datasheet
13 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Electrical specifications
Table 7
Spec ID
Error amplifier
Parameter
Description
Min Typ Max
Unit Details/conditions
DC specifications
VBUS voltage regulation
accuracy
Off-state EA_OUT
current
SID.DC.VR.1
SID.DC.VR.2
VR
–
–
± 3
2.2
± 5
10
%
–
–
Ika_off
Ika_on
µA
Current through
EA_OUT pin when in
Sink mode for
SID.DC.VR.3
–
–
5
mA
–
optocoupler application
Differential nonlinearity
of NMOS DAC
Integral nonlinearity of
NMOS DAC
SID.DC.VR.4
SID.DC.VR.5
SID.DC.VR.6
SID.DC.VR.7
SID.DC.VR.8
SID.DC.VR.9
DNL_ndac
INL_ndac
–1
–1.5
–8
–
–
–
–
–
–
1
1.5
8
–
–
–
–
–
–
LSB
%
Gain_
error_ndac
Gain error of NMOS DAC
Differential nonlinearity
of PMOS DAC
Integral nonlinearity of
PMOS DAC
DNL_pdac
INL_pdac
–0.5
–1
0.5
1
LSB
%
Gain_
error_pdac
Gain error of PMOS DAC
–8
8
Table 8
Spec ID
LSCSA, SCP
Parameter
Description
Min Typ Max
Unit Details/conditions
DC specifications
SID.LSCSA.1
Cin_inp
CSP input capacitance
CSA accuracy with
5 mV < Vsense < 10 mV
CSA accuracy with
10 mV < Vsense < 15 mV
CSA accuracy with
15 mV < Vsense
Short circuit trip point
with threshold set to 6 A
–
–
–
10
15
pF
%
–
–
SID.LSCSA.2
Csa_Acc1
Csa_Acc2
Csa_Acc3
SCP_6A
–15
SID.LSCSA.3
SID.LSCSA.4
SID.LSCSA.5
–10
–5
–
–
6
10
5
–
–
5.4
6.6
A
Rsense = 5 m
Short circuit trip point
with threshold set to
10 A
CSA gain values
supported: 5,10, 20, 35,
50, 75, 125, 150
SID.LSCSA.6
SID.LSCSA.8
SCP_10A
Av
9
5
10
–
11
150
–
Datasheet
14 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Electrical specifications
Table 8
Spec ID
LSCSA, SCP (continued)
Parameter
Description
Min Typ Max
Unit Details/conditions
AC specifications
Delay from OCP
threshold trip to
external NFET gate turn
off
Delay from SCP
threshold trip to
external NFET gate turn
off
Delay from SCP
threshold trip to
external NFET power
gate turn off
SID.LSCSA.AC.1 Tocp_gate
–
–
–
4
20
–
–
1 nF NFET gate
µs
SID.LSCSA.AC.2 Tscp_gate
SID.LSCSA.AC.3 Tscp_gate_1
3.1
7.5
capacitance
3 nF NFET gate
capacitance
–
Table 9
Spec ID
VBUS UV, OV
Parameter
Description
Min Typ Max
Unit Details/conditions
DC specifications
Over-Voltage threshold
Accuracy, 4 V to 11 V
Over-Voltage threshold
Accuracy, 11 V to 21.5 V
Under-Voltage
threshold Accuracy, 3 V
to 3.3 V
Under-Voltage
threshold Accuracy,
3.3 V to 4.0 V
Under-Voltage
threshold Accuracy,
4.0 V to 11 V
Under-Voltage
threshold Accuracy, 11 V
to 21.5 V
SID.UVOV.1
SID.UVOV.2
VTHOV1
–3
–
–
3
–
–
VTHOV2
VTHUV1
–3.2
3.2
SID.UVOV.3
SID.UVOV.4
SID.UVOV.5
SID.UVOV.6
–4
–3.5
–3
–
–
–
–
4
–
%
–
VTHUV2
VTHUV3
VTHUV4
3.5
3
–
–
–2.9
2.9
AC specifications
Delay from OV threshold
trip to external NFET
Power Gate Turn off
SID.UVOV.AC.1 Tov_gate
–
–
50
µs
–
Datasheet
15 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Electrical specifications
Table 10
Spec ID
PD transceiver
Parameter
Description
Min
Typ Max Unit Details/conditions
DC specifications
Downstream facing port
(DFP) CC termination for
default USB power
SID.PD.1
Rp_std
64
80
96
–
DFP CC termination for
1.5 A USB power
DFP CC termination for
3.0 A USB power
Ground offset tolerated
by BMC receiver
µA
SID.PD.2
SID.PD.3
SID.PD.4
Rp_1.5A
166
304
180
330
–
194
356
500
–
–
Rp_3.0A
Relative to remote
BMC transmitter
Vgndoffset
–500
mV
Table 11
VBUS discharge
Parameter
Spec ID
Description
Min Typ Max Unit Details/conditions
DC specifications
20 V NMOS ON
SID.VBUS.DISC.1 R1
resistance for
500
250
125
62.5
–
–
–
–
2000
1000
500
discharge strength = 1
20 V NMOS ON
SID.VBUS.DISC.2 R2
SID.VBUS.DISC.3 R4
SID.VBUS.DISC.4 R8
SID.VBUS.DISC.5 R16
resistance for
discharge strength = 2
20 V NMOS ON
resistance for
Measured at 0.5 V
discharge strength = 4
20 V NMOS ON
resistance for
250
discharge strength = 8
20 V NMOS ON
resistance for
31.25
–
–
–
125
10
discharge strength = 16
Vbus_stop_
error
Error percentage of
final VBUS value
When VBUS is
discharged to 5 V
SID.VBUS.DISC.6
%
Datasheet
16 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Electrical specifications
Table 12
Spec ID
VBUS NFET gate driver
Parameter
Description
Min Typ Max Unit Details/conditions
DC specifications
Gate to Source
SID.GD.1
GD_VGS
GD_Rpd
overdrive during NFET 4.5 5.75
ON condition
10
2
V
Vbus_in = 21.5 V
–
Resistance when
pull-downisenabledto
turn off external NFET
SID.GD.2
–
0.57
k
AC specifications
VBUS_ctrl Low to High
(1 V to VBUS + 1 V) with
3 nF external
AC.GD.1
AC.GD.2
Ton
Toff
2
–
5
7
10
–
ms
µs
V
V
BUS_IN = 5 V
capacitance
VBUS_ctrl High to Low
(90% to 10%) with 3 nF
external capacitance
BUS_IN = 21.5 V
Table 13
Spec ID
High-voltage regulator
Parameter
Description
Min Typ Max Unit Details/conditions
DC specifications
VOLTAGE_
DETECT
VBUS_IN voltage detect
threshold
SID.VREG.1
1.7 2.1 2.4
50 200
V
–
From VBUS reaching
Total start-up time for the
regulator supply outputs
SID.VREG.2 Tstart
–
µs Voltage_detect level to
95% of final value
Datasheet
17 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Electrical specifications
Table 14
Spec ID
SR sense and driver
Parameter
Description
Min Typ Max Unit Details/conditions
DC specifications
Voltage doubler output for
SR.1
SR.2
VCPP1
5
9
–
–
–
–
–
3.3 V VBUS_IN 5.5 V
V
Voltage doubler output for
5.5 V VBUS_IN 21.5 V
VCPP2
TR_SR
11
Rise time (20% to 80%) of SR
gate driver output with
CL = 6 nF, VBUS_IN = 3.3 V,
including doubler rise time
(with and without double
bypass mode)
Fall time (80% to 20%) of SR
gate driver output with
CL = 6 nF, VBUS_IN = 3.3 V,
including doubler rise time
(with and without double
bypass mode)
SR.3
SR.4
–
–
150
–
–
ns
TF_SR
–
–
–
100
1
Input leakage current on
SR_VSS
Negative sense trip voltage
to turn-ON secondary switch
SR.5
SR.6
IIK_SR_VSS
–1
µA
–
–
VTRIP_
NSN_100
–140 –90 –60
mV
Negative sense trip voltage
to turn-OFF secondary
switch
Turn on propagation delay
from SR_SEN at –100mV to
SR_GDRV reaching 1V
Turn off propagation delay
from SR_SEN at –5mV to
SR_GDRV reaching 1V
SR.7
SR.8
SR.9
SR.10
VTRIP_ZCD
TD_ON
–8
–
–5
25
–3
50
–
–
–
ns
A
TD_OFF
–
100 200
Typical with 3 nF gate
cap (Guaranteed by
design)
Output peak current (Source
and Sink)
IO_SRC_SNK
–
1
–
Datasheet
18 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Electrical specifications
4.4
I/O specifications
Table 15
Spec ID
I/O specifications
Parameter
Description
Min
Typ Max
Unit Details/conditions
DC specifications
SID.GIO.1
SID.GIO.2
SID.GIO.3
SID.GIO.4
I_LU
RPU
RPD
IIL
Latch-up current limits
Pull-up resistor value
Pull-down resistor value
Input leakage current
–140
3.5
3.5
–
–
5.6
5.6
140
8.5
8.5
2
mA
k
nA
–
–
–
–
Capacitance on
DP/DM lines
Capacitance on all
GPIOs, except DP/DM
lines
SID.GIO.5
CPIN_A
–
7.8
3
22
Max pin capacitance
pF
SID.GIO.6
CPIN
–
7
VDDD
0.6
–
SID.GIO.7
SID.GIO.8
SID.GIO.9
Voh_3V
Vol_3V
Output voltage high level
Output voltage low level
Input voltage high
threshold
–
–
–
–
0.6
–
Ioh = –4 mA
Iol = 10 mA
–
–
0.7 ×
VDDD
Vih_CMOS
V
Input voltage low
threshold
0.3 ×
VDDD
SID.GIO.10 Vil_CMOS
–
–
–
SID.GIO.11 Vih_TTL
SID.GIO.12 Vil_TTL
SID.GIO.13 Vhysttl
2
–
100
0.05 ×
VDDD
–
–
–
–
–
–
LVTTL input
0.8
–
Input hysteresis LVTTL
Input hysteresis CMOS
mV
µA
SID.GIO.14 Vhyscmos
–
–
–
Current through
protection diode to
VDDD/VSS
SID.GIO.15 IDIODE
–
–
100
–
Rise time in fast strong
mode
Fall time in fast strong
mode
Rise time in slow strong
mode
Fall time in slow strong
mode
SID.GIO.16 TriseF
SID.GIO.17 TfallF
SID.GIO.18 TriseS
SID.GIO.19 TfallS
2
2
–
–
–
–
12
12
60
60
ns
10
10
Cload = 25 pF
GPIO Fout;
SID.GIO.20 FGPIO_OUT1 3 V VDDD 5.5V;
–
7
–
–
–
16
–
Fast strong mode.
GPIO Fout;
SID.GIO.21 FGPIO_OUT2 3V VDDD 5.5 V;
Slow strong mode.
MHz
GPIO input operating
SID.GIO.22 FGPIO_IN
frequency;
16
–
–
3 V VDDD 5.5 V
Datasheet
19 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Electrical specifications
4.5
System resources specifications
Table 16
Power-on reset (POR) specifications
Spec ID
SID.POR.1
SID.POR.2
Parameter
VRISEIPOR
VFALLIPOR
Description
POR rising trip voltage
POR falling trip voltage
Brown-out-detect
(BOD) trip voltage
active/ sleep modes
Min
0.8
0.7
Typ
–
–
Max
1.5
1.4
Unit
Details/conditions
–
–
V
SID.POR.3
SID.CLK#6
VFALLPPOR
SR_POWER
1.48
0.40
–
–
1.62
67
–
On power-up and
power-down
Power supply slew rate
V/ms
Datasheet
20 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Ordering information
5
Ordering information
Table 17
EZ-PD™ PAG1S ordering information
Application
MPN
Package type
Si ID
Si Rev
CYPD3184A1-24LQXQ
CYPD3184A1-24LQXQT
USB Power Delivery adapter with primary side
control
24-pin QFN
2B00
A1
5.1
Ordering code definitions
XX
X
CY PD
X
XX
XX XX
X
X
XX
X
-
T = Tape and reel
ES (Optional field) = Pre-production Engineering samples only. Non
orderable.
Temperature Range: Q = Extended industrial (-40ºC to +105ºC)
X = Pb-free
Package type: LQ = QFN
Number of pins in the package
Si Rev
Application and feature combination designation
Number of Type-C ports: 1 = 1 port
Product type: 3 = Third generation
Marketing code: PD = Power Delivery product family
Company ID: CY = Infineon
Datasheet
21 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Packaging
6
Packaging
Table 18
Package characteristics
Description
Parameter
Conditions
Min
Typ
Max
Unit
Operating ambient
temperature
Operating junction
temperature
TA
TJ
–40
25
105
Extended industrial
°C
–40
25
120
TJA
TJC
Package JA
Package JC
–
–
–
–
19.98
4.78
–
°C/W
Table 19
Solder reflow peak temperature
Maximum time within 5°C of peak
temperature
Package
24-pin QFN
Maximum peak temperature
260°C
30 seconds
Table 20
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2
Package
MSL
24-pin QFN
MSL 3
Datasheet
22 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Packaging
NOTES
DIMENSIONS
1. ALL DIMENSIONS ARE IN MILLIMETERS.
SYMBOL
MIN. NOM. MAX.
0.60
2. DIE THICKNESS ALLOWABLE IS 0.305 mm MAXIMUM(.012 INCHES MAXIMUM)
3. DIMENSIONING & TOLERANCES CONFORM TO ASME Y14.5M. -1994.
A
A1
4. THE PIN #1 IDENTIFIER MUST BE PLACED ON THE TOP SURFACE OF THE
PACKAGE BY USING INDENTATION MARK OR OTHER FEATURE OF
PACKAGE BODY.
0.00
0.05
A3 (Option 1)
A3 (Option 2)
0.152 REF
0.127 REF
0.25
5. EXACT SHAPE AND SIZE OF THIS FEATURE IS OPTIONAL.
6. PACKAGE WARPAGE MAX 0.08 mm.
0.18
2.65
0.30
2.85
b
7. APPLIED FOR EXPOSED PAD AND TERMINALS. EXCLUDE EMBEDDING PART
OF EXPOSED PAD FROM MEASURING.
D
4.00 BSC
2.75
D2
E
8. APPLIED ONLY TO TERMINALS.
4.00 BSC
2.75
9. JEDEC SPECIFICATION NO. REF: N.A.
E2
L
2.65
0.30
2.85
0.50
10. INDEX FEATURE CAN EITHER BE AN OPTION 1 : "MOUSE BITE" OR
OPTION 2 : CHAMFER.
0.40
e
0.50 BSC
R
0.09
002-16934 *E
24-pin QFN ((4.0 × 4.0 × 0.6 mm), 2.75 × 2.75 mm E-Pad (Sawn)) package outline, 002-16934
Figure 5
Datasheet
23 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Acronyms
7
Acronyms
Table 21
Acronym
ADC
API
Acronyms used in this document
Description
analog-to-digital converter
application programming interface
Arm®
CC
advanced RISC machine, a CPU architecture
constant current
CC
configuration channel
CV
constant voltage
BOD
BMC
CPU
CRC
CrCM
CS
Brown out Detect
biphase mark code
central processing unit
cyclic redundancy check, an error-checking protocol
critical conduction mode
current sense
DCM
DFP
discontinuous conduction mode
downstream facing port
DIO
DRP
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
dual role port
EEPROM electrically erasable programmable read-only memory
a USB cable that includes an IC that reports cable characteristics (e.g., current rating) to the Type-C
ports
EMCA
EMI
ESD
FPB
FS
electromagnetic interference
electrostatic discharge
flash patch and breakpoint
full-speed
GPIO
IC
general-purpose input/output
integrated circuit
IDE
integrated development environment
I2C, or IIC Inter-Integrated Circuit, a communications protocol
ILO
IMO
I/O
LSCSA
LVD
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
input/output, see also GPIO
low-side current sense amplifier
low-voltage detect
LVTTL
MCU
NC
low-voltage transistor-transistor logic
microcontroller unit
no connect
NMI
nonmaskable interrupt
NMOS
N-type metal-oxide-semiconductor
Datasheet
24 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Acronyms
Table 21
Acronym
NVIC
opamp
OCP
OVP
Acronyms used in this document (continued)
Description
nested vectored interrupt controller
operational amplifier
overcurrent protection
overvoltage protection
over-temperature protection
printed circuit board
OTP
PCB
PD
power delivery
PGA
PHY
programmable gain amplifier
physical layer
PMOS
POR
PPS
PRES
PSoC™
PWM
RAM
RISC
RMS
RTC
P-type metal-oxide-semiconductor
power-on reset
programmable power supply
precise power-on reset
programmable system-on-chip
pulse-width modulator
random-access memory
reduced-instruction-set computing
root-mean-square
real-time clock
RX
receive
SAR
SCL
successive approximation register
I2C serial clock
SCP
SDA
short circuit protection
I2C serial data
S/H
sample and hold
SPI
SR
Serial Peripheral Interface, a communications protocol
synchronous rectifier
SRAM
SWD
TX
static random access memory
serial wire debug, a test protocol
transmit
a new standard with a slimmer USB connector and a reversible cable, capable of sourcing up to
100 W of power
Type-C
UART
USB
Universal Asynchronous Transmitter Receiver, a communications protocol
Universal Serial Bus
USBIO
UVP
USB input/output, CCG5 pins used to connect to a USB port
undervoltage protection
WDT
watchdog timer
USBIO
XRES
ZCD
USB input/output, CCG5 pins used to connect to a USB port
external reset I/O pin
zero crossing detect
Datasheet
25 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Document conventions
8
Document conventions
8.1
Units of measure
Table 22
Symbol
°C
Units of measure
Unit of measure
degrees Celsius
hertz
Hz
KB
kHz
k
1024 bytes
kilohertz
kilo ohm
Mbps
MHz
M
Msps
µA
µF
µs
µV
megabits per second
megahertz
mega-ohm
megasamples per second
microampere
microfarad
microsecond
microvolt
µW
mA
ms
mV
nA
microwatt
milliampere
millisecond
millivolt
nanoampere
nanosecond
ohm
ns
pF
picofarad
ppm
ps
s
parts per million
picosecond
second
sps
V
samples per second
volt
Datasheet
26 of 28
002-26809 Rev. *D
2022-06-16
USB PD power adapter SR controller
Revision history
Revision history
Document
Date of release
version
Description of changes
*B
*C
2019-08-22
2022-05-18
Changed document status from Preliminary to Final.
Updated Ordering information:
Updated part numbers.
Updated Packaging:
spec 002-16934 – Changed revision from *B to *E.
Migrated to Infineon template.
Updated Electrical specifications:
Updated Device-level specifications:
Updated Table 4:
Changed maximum value of Cexc parameter from 4.7 µF to 2.2 µF.
Updated System resources specifications:
Updated Table 16:
*D
2022-06-16
Added SR_POWER parameter and its corresponding details.
Completing Sunset Review.
Datasheet
27 of 28
002-26809 Rev. *D
2022-06-16
Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
IMPORTANT NOTICE
For further information on the product, technology,
The information given in this document shall in no
event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”).
Edition 2022-06-16
Published by
delivery terms and conditions and prices please
contact your nearest Infineon Technologies office
(www.infineon.com).
Infineon Technologies AG
81726 Munich, Germany
With respect to any examples, hints or any typical
values stated herein and/or any information
regarding the application of the product, Infineon
Technologies hereby disclaims any and all
warranties and liabilities of any kind, including
without limitation warranties of non-infringement of
intellectual property rights of any third party.
WARNINGS
Due to technical requirements products may contain
dangerous substances. For information on the types
in question please contact your nearest Infineon
Technologies office.
© 2022 Infineon Technologies AG.
All Rights Reserved.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by
In addition, any information given in this document
is subject to customer’s compliance with its
obligations stated in this document and any
applicable legal requirements, norms and standards
concerning customer’s products and any use of the
product of Infineon Technologies in customer’s
applications.
Do you have a question about this
document?
Go to www.infineon.com/support
authorized
representatives
of
Infineon
Technologies, Infineon Technologies’ products may
not be used in any applications where a failure of the
product or any consequences of the use thereof can
reasonably be expected to result in personal injury.
Document reference
002-26809 Rev. *D
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical departments
to evaluate the suitability of the product for the
intended application and the completeness of the
product information given in this document with
respect to such application.
相关型号:
CYPD3184A1-24LQXQT
PG-VQFN-24 tape and reel packing secondary side controller with PD controller and synchronous rectifier with optocoupler-feedback for USB PD charger and adapters
INFINEON
CYPD4255-96BZXI
Microprocessor Circuit, CMOS, PBGA96, 6 X 6 MM, 0.50 MM PITCH, LEAD FREE, MO-225, BGA-96
CYPRESS
©2020 ICPDF网 联系我们和版权申明